| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * switch_ioctl.h: switch(ioctl) set API |
| 3 | */ |
| 4 | |
| 5 | #ifndef SWITCH_IOCTL_H |
| 6 | #define SWITCH_IOCTL_H |
| 7 | |
| 8 | #define ETH_DEVNAME "eth0" |
| 9 | #define BR_DEVNAME "br-lan" |
| 10 | |
| 11 | #define RAETH_MII_READ 0x89F3 |
| 12 | #define RAETH_MII_WRITE 0x89F4 |
| 13 | #define RAETH_ESW_PHY_DUMP 0x89F7 |
| 14 | |
| 15 | struct esw_reg { |
| 16 | unsigned int off; |
| 17 | unsigned int val; |
| 18 | }; |
| 19 | |
| 20 | struct ra_mii_ioctl_data { |
| developer | 2076225 | 2021-05-13 16:38:03 +0800 | [diff] [blame] | 21 | __u16 phy_id; |
| 22 | __u16 reg_num; |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 23 | __u32 val_in; |
| 24 | __u32 val_out; |
| developer | 2076225 | 2021-05-13 16:38:03 +0800 | [diff] [blame] | 25 | /* |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 26 | __u32 port_num; |
| 27 | __u32 dev_addr; |
| 28 | __u32 reg_addr; |
| developer | 2076225 | 2021-05-13 16:38:03 +0800 | [diff] [blame] | 29 | */ |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 30 | }; |
| 31 | |
| 32 | struct ra_switch_ioctl_data { |
| 33 | unsigned int cmd; |
| 34 | unsigned int on_off; |
| 35 | unsigned int port; |
| 36 | unsigned int bw; |
| 37 | unsigned int vid; |
| 38 | unsigned int fid; |
| 39 | unsigned int port_map; |
| 40 | unsigned int rx_port_map; |
| 41 | unsigned int tx_port_map; |
| 42 | unsigned int igmp_query_interval; |
| 43 | unsigned int reg_addr; |
| 44 | unsigned int reg_val; |
| 45 | unsigned int mode; |
| 46 | unsigned int qos_queue_num; |
| 47 | unsigned int qos_type; |
| 48 | unsigned int qos_pri; |
| 49 | unsigned int qos_dscp; |
| 50 | unsigned int qos_table_idx; |
| 51 | unsigned int qos_weight; |
| 52 | unsigned char mac[6]; |
| 53 | }; |
| 54 | |
| 55 | extern int chip_name; |
| 56 | |
| developer | 0c1ae57 | 2021-05-27 15:32:01 +0800 | [diff] [blame] | 57 | int switch_ioctl_init(void); |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 58 | void switch_ioctl_fini(void); |
| 59 | int reg_read_ioctl(unsigned int offset, unsigned int *value); |
| 60 | int reg_write_ioctl(unsigned int offset, unsigned int value); |
| 61 | int phy_dump_ioctl(unsigned int phy_addr); |
| 62 | int mii_mgr_cl22_read_ioctl(unsigned int port_num, unsigned int reg, |
| 63 | unsigned int *value); |
| 64 | int mii_mgr_cl22_write_ioctl(unsigned int port_num, unsigned int reg, |
| 65 | unsigned int value); |
| 66 | int mii_mgr_cl45_read_ioctl(unsigned int port_num, unsigned int dev, |
| 67 | unsigned int reg, unsigned int *value); |
| 68 | int mii_mgr_cl45_write_ioctl(unsigned int port_num, unsigned int dev, |
| 69 | unsigned int reg, unsigned int value); |
| 70 | #endif |