developer | ac95e9f | 2024-03-06 21:54:37 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7981.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7981 RFB"; |
| 5 | compatible = "mediatek,mt7981-spim-snand-2500wan-an8855-rfb"; |
| 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000"; |
| 9 | }; |
| 10 | |
| 11 | memory { |
| 12 | // fpga ddr2: 128MB*2 |
| 13 | reg = <0 0x40000000 0 0x10000000>; |
| 14 | }; |
| 15 | |
| 16 | gpio-keys { |
| 17 | compatible = "gpio-keys"; |
| 18 | reset { |
| 19 | label = "reset"; |
| 20 | linux,code = <KEY_RESTART>; |
| 21 | gpios = <&pio 1 GPIO_ACTIVE_LOW>; |
| 22 | }; |
| 23 | |
| 24 | wps { |
| 25 | label = "wps"; |
| 26 | linux,code = <KEY_WPS_BUTTON>; |
| 27 | gpios = <&pio 0 GPIO_ACTIVE_HIGH>; |
| 28 | }; |
| 29 | }; |
| 30 | |
| 31 | nmbm_spim_nand { |
| 32 | compatible = "generic,nmbm"; |
| 33 | |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <1>; |
| 36 | |
| 37 | lower-mtd-device = <&spi_nand>; |
| 38 | forced-create; |
| 39 | |
| 40 | partitions { |
| 41 | compatible = "fixed-partitions"; |
| 42 | #address-cells = <1>; |
| 43 | #size-cells = <1>; |
| 44 | |
| 45 | partition@0 { |
| 46 | label = "BL2"; |
| 47 | reg = <0x00000 0x0100000>; |
| 48 | read-only; |
| 49 | }; |
| 50 | |
| 51 | partition@100000 { |
| 52 | label = "u-boot-env"; |
| 53 | reg = <0x0100000 0x0080000>; |
| 54 | }; |
| 55 | |
| 56 | factory: partition@180000 { |
| 57 | label = "Factory"; |
| 58 | reg = <0x180000 0x0200000>; |
| 59 | }; |
| 60 | |
| 61 | partition@380000 { |
| 62 | label = "FIP"; |
| 63 | reg = <0x380000 0x0200000>; |
| 64 | }; |
| 65 | |
| 66 | partition@580000 { |
| 67 | label = "ubi"; |
| 68 | reg = <0x580000 0x4000000>; |
| 69 | }; |
| 70 | }; |
| 71 | }; |
| 72 | }; |
| 73 | |
| 74 | &uart0 { |
| 75 | status = "okay"; |
| 76 | }; |
| 77 | |
| 78 | &watchdog { |
| 79 | status = "okay"; |
| 80 | }; |
| 81 | |
| 82 | ð { |
| 83 | status = "okay"; |
| 84 | |
| 85 | gmac0: mac@0 { |
| 86 | compatible = "mediatek,eth-mac"; |
| 87 | reg = <0>; |
| 88 | phy-mode = "2500base-x"; |
| 89 | |
| 90 | fixed-link { |
| 91 | speed = <2500>; |
| 92 | full-duplex; |
| 93 | pause; |
| 94 | }; |
developer | 89456e0 | 2024-03-09 14:25:45 +0800 | [diff] [blame^] | 95 | }; |
developer | ac95e9f | 2024-03-06 21:54:37 +0800 | [diff] [blame] | 96 | |
| 97 | gmac1: mac@1 { |
| 98 | compatible = "mediatek,eth-mac"; |
| 99 | reg = <1>; |
| 100 | phy-mode = "2500base-x"; |
| 101 | phy-handle = <&phy5>; |
| 102 | }; |
| 103 | |
| 104 | mdio: mdio-bus { |
| 105 | #address-cells = <1>; |
| 106 | #size-cells = <0>; |
| 107 | |
| 108 | reset-gpios = <&pio 14 1>; |
| 109 | reset-delay-us = <600>; |
| 110 | |
| 111 | phy5: phy@5 { |
| 112 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 113 | reg = <5>; |
| 114 | }; |
| 115 | |
| 116 | switch@0 { |
| 117 | compatible = "airoha,an8855"; |
| 118 | reg = <1>; |
| 119 | reset-gpios = <&pio 39 0>; |
| 120 | changesmiaddr = <6>; |
| 121 | ports { |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <0>; |
| 124 | |
| 125 | port@0 { |
| 126 | reg = <0>; |
| 127 | label = "lan1"; |
| 128 | }; |
| 129 | |
| 130 | port@1 { |
| 131 | reg = <1>; |
| 132 | label = "lan2"; |
| 133 | }; |
| 134 | |
| 135 | port@2 { |
| 136 | reg = <2>; |
| 137 | label = "lan3"; |
| 138 | }; |
| 139 | |
| 140 | port@3 { |
| 141 | reg = <3>; |
| 142 | label = "lan4"; |
| 143 | }; |
| 144 | |
| 145 | port@5 { |
| 146 | reg = <5>; |
| 147 | label = "cpu"; |
| 148 | ethernet = <&gmac0>; |
| 149 | phy-mode = "2500base-x"; |
| 150 | |
| 151 | fixed-link { |
| 152 | speed = <2500>; |
| 153 | full-duplex; |
| 154 | pause; |
| 155 | }; |
| 156 | }; |
| 157 | }; |
| 158 | }; |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | &hnat { |
| 163 | mtketh-wan = "eth1"; |
| 164 | mtketh-lan = "lan"; |
| 165 | mtketh-max-gmac = <2>; |
| 166 | status = "okay"; |
| 167 | }; |
| 168 | |
| 169 | &spi0 { |
| 170 | pinctrl-names = "default"; |
| 171 | pinctrl-0 = <&spi0_flash_pins>; |
| 172 | status = "okay"; |
| 173 | spi_nand: spi_nand@0 { |
| 174 | #address-cells = <1>; |
| 175 | #size-cells = <1>; |
| 176 | compatible = "spi-nand"; |
| 177 | spi-cal-enable; |
| 178 | spi-cal-mode = "read-data"; |
| 179 | spi-cal-datalen = <7>; |
| 180 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 181 | spi-cal-addrlen = <5>; |
| 182 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 183 | reg = <0>; |
| 184 | spi-max-frequency = <52000000>; |
| 185 | spi-tx-bus-width = <4>; |
| 186 | spi-rx-bus-width = <4>; |
| 187 | }; |
| 188 | }; |
| 189 | |
| 190 | &spi1 { |
| 191 | pinctrl-names = "default"; |
| 192 | pinctrl-0 = <&spic_pins>; |
| 193 | status = "disabled"; |
| 194 | |
| 195 | slb9670: slb9670@0 { |
| 196 | compatible = "infineon,slb9670"; |
| 197 | reg = <0>; /* CE0 */ |
| 198 | #address-cells = <1>; |
| 199 | #size-cells = <0>; |
| 200 | spi-cal-enable; |
| 201 | spi-cal-mode = "read-data"; |
| 202 | spi-cal-datalen = <2>; |
| 203 | spi-cal-data = /bits/ 8 <0x00 0x1b>; |
| 204 | spi-max-frequency = <20000000>; |
| 205 | }; |
| 206 | }; |
| 207 | |
| 208 | &wbsys { |
| 209 | mediatek,mtd-eeprom = <&factory 0x0000>; |
| 210 | status = "okay"; |
| 211 | pinctrl-names = "dbdc"; |
| 212 | pinctrl-0 = <&wf_dbdc_pins>; |
| 213 | }; |
| 214 | |
| 215 | &pio { |
| 216 | |
| 217 | i2c_pins: i2c-pins-g0 { |
| 218 | mux { |
| 219 | function = "i2c"; |
| 220 | groups = "i2c0_0"; |
| 221 | }; |
| 222 | }; |
| 223 | |
| 224 | pcm_pins: pcm-pins-g0 { |
| 225 | mux { |
| 226 | function = "pcm"; |
| 227 | groups = "pcm"; |
| 228 | }; |
| 229 | }; |
| 230 | |
| 231 | pwm0_pin: pwm0-pin-g0 { |
| 232 | mux { |
| 233 | function = "pwm"; |
| 234 | groups = "pwm0_0"; |
| 235 | }; |
| 236 | }; |
| 237 | |
| 238 | pwm1_pin: pwm1-pin-g0 { |
| 239 | mux { |
| 240 | function = "pwm"; |
| 241 | groups = "pwm1_0"; |
| 242 | }; |
| 243 | }; |
| 244 | |
| 245 | pwm2_pin: pwm2-pin { |
| 246 | mux { |
| 247 | function = "pwm"; |
| 248 | groups = "pwm2"; |
| 249 | }; |
| 250 | }; |
| 251 | |
| 252 | spi0_flash_pins: spi0-pins { |
| 253 | mux { |
| 254 | function = "spi"; |
| 255 | groups = "spi0", "spi0_wp_hold"; |
| 256 | }; |
| 257 | |
| 258 | conf-pu { |
| 259 | pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; |
| 260 | drive-strength = <MTK_DRIVE_8mA>; |
| 261 | bias-pull-up = <MTK_PUPD_SET_R1R0_11>; |
| 262 | }; |
| 263 | |
| 264 | conf-pd { |
| 265 | pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; |
| 266 | drive-strength = <MTK_DRIVE_8mA>; |
| 267 | bias-pull-down = <MTK_PUPD_SET_R1R0_11>; |
| 268 | }; |
| 269 | }; |
| 270 | |
| 271 | spic_pins: spi1-pins { |
| 272 | mux { |
| 273 | function = "spi"; |
| 274 | groups = "spi1_1"; |
| 275 | }; |
| 276 | }; |
| 277 | |
| 278 | uart1_pins: uart1-pins-g1 { |
| 279 | mux { |
| 280 | function = "uart"; |
| 281 | groups = "uart1_1"; |
| 282 | }; |
| 283 | }; |
| 284 | |
| 285 | uart2_pins: uart2-pins-g1 { |
| 286 | mux { |
| 287 | function = "uart"; |
| 288 | groups = "uart2_1"; |
| 289 | }; |
| 290 | }; |
| 291 | |
| 292 | wf_dbdc_pins: wf_dbdc-pins { |
| 293 | mux { |
| 294 | function = "eth"; |
| 295 | groups = "wf0_mode1"; |
| 296 | }; |
| 297 | conf { |
| 298 | pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", |
| 299 | "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", |
| 300 | "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", |
| 301 | "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", |
| 302 | "WF_CBA_RESETB", "WF_DIG_RESETB"; |
| 303 | drive-strength = <MTK_DRIVE_4mA>; |
| 304 | }; |
| 305 | }; |
| 306 | }; |
| 307 | |
| 308 | &xhci { |
| 309 | status = "okay"; |
| 310 | }; |