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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 87e071ef5fc5f8ca69491a58ddb89dd66ed8e29d / . / target / linux / mediatek / patches-5.4 / 8008-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
blob: 1223fb6322cd17d731c18c172d38ebd23f225838 [file] [log] [blame]
developer44e1bbf2022-01-28 17:20:00 +0800[diff] [blame]1From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
2From: Zhanyong Wang <zhanyong.wang@mediatek.com>
3Date: Tue, 25 Jan 2022 19:03:34 +0800
4Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
5 support
6
7add auto-load-valid check mechanism support
8
9Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
10---
11 drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
12 1 file changed, 64 insertions(+), 3 deletions(-)
13
14diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
15index 59d6ac3..4adc505 100644
16--- a/drivers/phy/mediatek/phy-mtk-tphy.c
17+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
18@@ -345,9 +345,13 @@ struct mtk_phy_instance {
19 };
20 struct clk *ref_clk; /* reference clock of anolog phy */
21 u32 efuse_sw_en;
22+ bool efuse_alv_en;
23+ u32 efuse_autoloadvalid;
24 u32 efuse_intr;
25 u32 efuse_tx_imp;
26 u32 efuse_rx_imp;
27+ bool efuse_alv_ln1_en;
28+ u32 efuse_ln1_autoloadvalid;
29 u32 efuse_intr_ln1;
30 u32 efuse_tx_imp_ln1;
31 u32 efuse_rx_imp_ln1;
32@@ -980,6 +984,7 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
33 {
34 struct device *dev = &instance->phy->dev;
35 int ret = 0;
36+ bool alv = false;
37
38 dev_err(dev, "try to get sw efuse\n");
39
40@@ -998,6 +1003,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
41
42 switch (instance->type) {
43 case PHY_TYPE_USB2:
44+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
45+ if (alv) {
46+ instance->efuse_alv_en = alv;
47+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
48+ &instance->efuse_autoloadvalid);
49+ if (ret) {
50+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
51+ break;
52+ }
53+ dev_info(dev,
54+ "u2 auto load valid efuse: ENABLE with value: %u\n",
55+ instance->efuse_autoloadvalid);
56+ }
57+
58 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
59 if (ret) {
60 dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
61@@ -1015,6 +1034,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
62 break;
63 case PHY_TYPE_USB3:
64 case PHY_TYPE_PCIE:
65+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
66+ if (alv) {
67+ instance->efuse_alv_en = alv;
68+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
69+ &instance->efuse_autoloadvalid);
70+ if (ret) {
71+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
72+ break;
73+ }
74+ dev_info(dev,
75+ "u3 auto load valid efuse: ENABLE with value: %u\n",
76+ instance->efuse_autoloadvalid);
77+ }
78+
79 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
80 if (ret) {
81 dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
82@@ -1049,6 +1082,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
83 if (tphy->pdata->version != MTK_PHY_V4)
84 break;
85
86+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
87+ if (alv) {
88+ instance->efuse_alv_ln1_en = alv;
89+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
90+ &instance->efuse_ln1_autoloadvalid);
91+ if (ret) {
92+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
93+ break;
94+ }
95+ dev_info(dev,
96+ "pcie auto load valid efuse: ENABLE with value: %u\n",
97+ instance->efuse_ln1_autoloadvalid);
98+ }
99+
100 ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
101 if (ret) {
102 dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
103@@ -1100,6 +1147,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
104
105 switch (instance->type) {
106 case PHY_TYPE_USB2:
107+ if (instance->efuse_alv_en &&
108+ instance->efuse_autoloadvalid == 1)
109+ break;
110+
111 tmp = readl(u2_banks->misc + U3P_MISC_REG1);
112 tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
113 writel(tmp, u2_banks->misc + U3P_MISC_REG1);
114@@ -1112,6 +1163,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
115
116 break;
117 case PHY_TYPE_USB3:
118+ if (instance->efuse_alv_en &&
119+ instance->efuse_autoloadvalid == 1)
120+ break;
121+
122 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
123 tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
124 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
125@@ -1138,6 +1193,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
126
127 break;
128 case PHY_TYPE_PCIE:
129+ if (instance->efuse_alv_en &&
130+ instance->efuse_autoloadvalid == 1)
131+ break;
132+
133 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
134 tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
135 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
136@@ -1162,9 +1221,11 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
137 __func__, instance->efuse_tx_imp,
138 instance->efuse_rx_imp, instance->efuse_intr);
139
140- if (!instance->efuse_intr_ln1 &&
141- !instance->efuse_rx_imp_ln1 &&
142- !instance->efuse_tx_imp_ln1)
143+ if ((!instance->efuse_intr_ln1 &&
144+ !instance->efuse_rx_imp_ln1 &&
145+ !instance->efuse_tx_imp_ln1) ||
146+ (instance->efuse_alv_ln1_en &&
147+ instance->efuse_ln1_autoloadvalid == 1))
148 break;
149
150 tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
151--
1522.18.0
153