developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 MediaTek Inc. |
| 4 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _MT753X_REGS_H_ |
| 8 | #define _MT753X_REGS_H_ |
| 9 | |
| 10 | #include <linux/bitops.h> |
| 11 | |
| 12 | /* Values of Egress TAG Control */ |
| 13 | #define ETAG_CTRL_UNTAG 0 |
| 14 | #define ETAG_CTRL_TAG 2 |
| 15 | #define ETAG_CTRL_SWAP 1 |
| 16 | #define ETAG_CTRL_STACK 3 |
| 17 | |
| 18 | #define VTCR 0x90 |
| 19 | #define VAWD1 0x94 |
| 20 | #define VAWD2 0x98 |
| 21 | |
| 22 | /* Fields of VTCR */ |
| 23 | #define VTCR_BUSY BIT(31) |
| 24 | #define IDX_INVLD BIT(16) |
| 25 | #define VTCR_FUNC_S 12 |
| 26 | #define VTCR_FUNC_M 0xf000 |
| 27 | #define VTCR_VID_S 0 |
| 28 | #define VTCR_VID_M 0xfff |
| 29 | |
| 30 | /* Values of VTCR_FUNC */ |
| 31 | #define VTCR_READ_VLAN_ENTRY 0 |
| 32 | #define VTCR_WRITE_VLAN_ENTRY 1 |
| 33 | #define VTCR_INVD_VLAN_ENTRY 2 |
| 34 | #define VTCR_ENABLE_VLAN_ENTRY 3 |
| 35 | #define VTCR_READ_ACL_ENTRY 4 |
| 36 | #define VTCR_WRITE_ACL_ENTRY 5 |
| 37 | #define VTCR_READ_TRTCM_TABLE 6 |
| 38 | #define VTCR_WRITE_TRTCM_TABLE 7 |
| 39 | #define VTCR_READ_ACL_MASK_ENTRY 8 |
| 40 | #define VTCR_WRITE_ACL_MASK_ENTRY 9 |
| 41 | #define VTCR_READ_ACL_RULE_ENTRY 10 |
| 42 | #define VTCR_WRITE_ACL_RULE_ENTRY 11 |
| 43 | #define VTCR_READ_ACL_RATE_ENTRY 12 |
| 44 | #define VTCR_WRITE_ACL_RATE_ENTRY 13 |
| 45 | |
| 46 | /* VLAN entry fields */ |
| 47 | /* VAWD1 */ |
| 48 | #define PORT_STAG BIT(31) |
| 49 | #define IVL_MAC BIT(30) |
| 50 | #define EG_CON BIT(29) |
| 51 | #define VTAG_EN BIT(28) |
| 52 | #define COPY_PRI BIT(27) |
| 53 | #define USER_PRI_S 24 |
| 54 | #define USER_PRI_M 0x7000000 |
| 55 | #define PORT_MEM_S 16 |
| 56 | #define PORT_MEM_M 0xff0000 |
| 57 | #define S_TAG1_S 4 |
| 58 | #define S_TAG1_M 0xfff0 |
| 59 | #define FID_S 1 |
| 60 | #define FID_M 0x0e |
| 61 | #define VENTRY_VALID BIT(0) |
| 62 | |
| 63 | /* VAWD2 */ |
| 64 | #define S_TAG2_S 16 |
| 65 | #define S_TAG2_M 0xffff0000 |
| 66 | #define PORT_ETAG_S(p) ((p) * 2) |
| 67 | #define PORT_ETAG_M 0x03 |
| 68 | |
| 69 | #define PORT_CTRL_BASE 0x2000 |
| 70 | #define PORT_CTRL_PORT_OFFSET 0x100 |
| 71 | #define PORT_CTRL_REG(p, r) (PORT_CTRL_BASE + \ |
| 72 | (p) * PORT_CTRL_PORT_OFFSET + (r)) |
| 73 | #define CKGCR(p) PORT_CTRL_REG(p, 0x00) |
| 74 | #define PCR(p) PORT_CTRL_REG(p, 0x04) |
| 75 | #define PIC(p) PORT_CTRL_REG(p, 0x08) |
| 76 | #define PSC(p) PORT_CTRL_REG(p, 0x0c) |
| 77 | #define PVC(p) PORT_CTRL_REG(p, 0x10) |
| 78 | #define PPBV1(p) PORT_CTRL_REG(p, 0x14) |
| 79 | #define PPBV2(p) PORT_CTRL_REG(p, 0x18) |
| 80 | #define BSR(p) PORT_CTRL_REG(p, 0x1c) |
| 81 | #define STAG01 PORT_CTRL_REG(p, 0x20) |
| 82 | #define STAG23 PORT_CTRL_REG(p, 0x24) |
| 83 | #define STAG45 PORT_CTRL_REG(p, 0x28) |
| 84 | #define STAG67 PORT_CTRL_REG(p, 0x2c) |
| 85 | |
| 86 | #define PPBV(p, g) (PPBV1(p) + ((g) / 2) * 4) |
| 87 | |
| 88 | /* Fields of PCR */ |
| 89 | #define MLDV2_EN BIT(30) |
| 90 | #define EG_TAG_S 28 |
| 91 | #define EG_TAG_M 0x30000000 |
| 92 | #define PORT_PRI_S 24 |
| 93 | #define PORT_PRI_M 0x7000000 |
| 94 | #define PORT_MATRIX_S 16 |
| 95 | #define PORT_MATRIX_M 0xff0000 |
| 96 | #define UP2DSCP_EN BIT(12) |
| 97 | #define UP2TAG_EN BIT(11) |
| 98 | #define ACL_EN BIT(10) |
| 99 | #define PORT_TX_MIR BIT(9) |
| 100 | #define PORT_RX_MIR BIT(8) |
| 101 | #define ACL_MIR BIT(7) |
| 102 | #define MIS_PORT_FW_S 4 |
| 103 | #define MIS_PORT_FW_M 0x70 |
| 104 | #define VLAN_MIS BIT(2) |
| 105 | #define PORT_VLAN_S 0 |
| 106 | #define PORT_VLAN_M 0x03 |
| 107 | |
| 108 | /* Values of PORT_VLAN */ |
| 109 | #define PORT_MATRIX_MODE 0 |
| 110 | #define FALLBACK_MODE 1 |
| 111 | #define CHECK_MODE 2 |
| 112 | #define SECURITY_MODE 3 |
| 113 | |
| 114 | /* Fields of PVC */ |
| 115 | #define STAG_VPID_S 16 |
| 116 | #define STAG_VPID_M 0xffff0000 |
| 117 | #define DIS_PVID BIT(15) |
| 118 | #define FORCE_PVID BIT(14) |
| 119 | #define PT_VPM BIT(12) |
| 120 | #define PT_OPTION BIT(11) |
| 121 | #define PVC_EG_TAG_S 8 |
| 122 | #define PVC_EG_TAG_M 0x700 |
| 123 | #define VLAN_ATTR_S 6 |
| 124 | #define VLAN_ATTR_M 0xc0 |
| 125 | #define PVC_PORT_STAG BIT(5) |
| 126 | #define BC_LKYV_EN BIT(4) |
| 127 | #define MC_LKYV_EN BIT(3) |
| 128 | #define UC_LKYV_EN BIT(2) |
| 129 | #define ACC_FRM_S 0 |
| 130 | #define ACC_FRM_M 0x03 |
| 131 | |
| 132 | /* Values of VLAN_ATTR */ |
| 133 | #define VA_USER_PORT 0 |
| 134 | #define VA_STACK_PORT 1 |
| 135 | #define VA_TRANSLATION_PORT 2 |
| 136 | #define VA_TRANSPARENT_PORT 3 |
| 137 | |
| 138 | /* Fields of PPBV */ |
| 139 | #define GRP_PORT_PRI_S(g) (((g) % 2) * 16 + 13) |
| 140 | #define GRP_PORT_PRI_M 0x07 |
| 141 | #define GRP_PORT_VID_S(g) (((g) % 2) * 16) |
| 142 | #define GRP_PORT_VID_M 0xfff |
| 143 | |
| 144 | #define PORT_MAC_CTRL_BASE 0x3000 |
| 145 | #define PORT_MAC_CTRL_PORT_OFFSET 0x100 |
| 146 | #define PORT_MAC_CTRL_REG(p, r) (PORT_MAC_CTRL_BASE + \ |
| 147 | (p) * PORT_MAC_CTRL_PORT_OFFSET + (r)) |
| 148 | #define PMCR(p) PORT_MAC_CTRL_REG(p, 0x00) |
| 149 | #define PMEEECR(p) PORT_MAC_CTRL_REG(p, 0x04) |
| 150 | #define PMSR(p) PORT_MAC_CTRL_REG(p, 0x08) |
| 151 | #define PINT_EN(p) PORT_MAC_CTRL_REG(p, 0x10) |
| 152 | #define PINT_STS(p) PORT_MAC_CTRL_REG(p, 0x14) |
| 153 | |
| 154 | #define GMACCR (PORT_MAC_CTRL_BASE + 0xe0) |
| 155 | #define TXCRC_EN BIT(19) |
| 156 | #define RXCRC_EN BIT(18) |
| 157 | #define PRMBL_LMT_EN BIT(17) |
| 158 | #define MTCC_LMT_S 9 |
| 159 | #define MTCC_LMT_M 0x1e00 |
| 160 | #define MAX_RX_JUMBO_S 2 |
| 161 | #define MAX_RX_JUMBO_M 0x3c |
| 162 | #define MAX_RX_PKT_LEN_S 0 |
| 163 | #define MAX_RX_PKT_LEN_M 0x3 |
| 164 | |
| 165 | /* Values of MAX_RX_PKT_LEN */ |
| 166 | #define RX_PKT_LEN_1518 0 |
| 167 | #define RX_PKT_LEN_1536 1 |
| 168 | #define RX_PKT_LEN_1522 2 |
| 169 | #define RX_PKT_LEN_MAX_JUMBO 3 |
| 170 | |
| 171 | /* Fields of PMCR */ |
| 172 | #define IPG_CFG_S 18 |
| 173 | #define IPG_CFG_M 0xc0000 |
| 174 | #define EXT_PHY BIT(17) |
| 175 | #define MAC_MODE BIT(16) |
| 176 | #define MAC_TX_EN BIT(14) |
| 177 | #define MAC_RX_EN BIT(13) |
| 178 | #define MAC_PRE BIT(11) |
| 179 | #define BKOFF_EN BIT(9) |
| 180 | #define BACKPR_EN BIT(8) |
| 181 | #define FORCE_EEE1G BIT(7) |
| 182 | #define FORCE_EEE1000 BIT(6) |
| 183 | #define FORCE_RX_FC BIT(5) |
| 184 | #define FORCE_TX_FC BIT(4) |
| 185 | #define FORCE_SPD_S 2 |
| 186 | #define FORCE_SPD_M 0x0c |
| 187 | #define FORCE_DPX BIT(1) |
| 188 | #define FORCE_LINK BIT(0) |
| 189 | |
| 190 | /* Fields of PMSR */ |
| 191 | #define EEE1G_STS BIT(7) |
| 192 | #define EEE100_STS BIT(6) |
| 193 | #define RX_FC_STS BIT(5) |
| 194 | #define TX_FC_STS BIT(4) |
| 195 | #define MAC_SPD_STS_S 2 |
| 196 | #define MAC_SPD_STS_M 0x0c |
| 197 | #define MAC_DPX_STS BIT(1) |
| 198 | #define MAC_LNK_STS BIT(0) |
| 199 | |
| 200 | /* Values of MAC_SPD_STS */ |
| 201 | #define MAC_SPD_10 0 |
| 202 | #define MAC_SPD_100 1 |
| 203 | #define MAC_SPD_1000 2 |
| 204 | #define MAC_SPD_2500 3 |
| 205 | |
| 206 | /* Values of IPG_CFG */ |
| 207 | #define IPG_96BIT 0 |
| 208 | #define IPG_96BIT_WITH_SHORT_IPG 1 |
| 209 | #define IPG_64BIT 2 |
| 210 | |
| 211 | #define MIB_COUNTER_BASE 0x4000 |
| 212 | #define MIB_COUNTER_PORT_OFFSET 0x100 |
| 213 | #define MIB_COUNTER_REG(p, r) (MIB_COUNTER_BASE + \ |
| 214 | (p) * MIB_COUNTER_PORT_OFFSET + (r)) |
| 215 | #define STATS_TDPC 0x00 |
| 216 | #define STATS_TCRC 0x04 |
| 217 | #define STATS_TUPC 0x08 |
| 218 | #define STATS_TMPC 0x0C |
| 219 | #define STATS_TBPC 0x10 |
| 220 | #define STATS_TCEC 0x14 |
| 221 | #define STATS_TSCEC 0x18 |
| 222 | #define STATS_TMCEC 0x1C |
| 223 | #define STATS_TDEC 0x20 |
| 224 | #define STATS_TLCEC 0x24 |
| 225 | #define STATS_TXCEC 0x28 |
| 226 | #define STATS_TPPC 0x2C |
| 227 | #define STATS_TL64PC 0x30 |
| 228 | #define STATS_TL65PC 0x34 |
| 229 | #define STATS_TL128PC 0x38 |
| 230 | #define STATS_TL256PC 0x3C |
| 231 | #define STATS_TL512PC 0x40 |
| 232 | #define STATS_TL1024PC 0x44 |
| 233 | #define STATS_TOC 0x48 |
| 234 | #define STATS_RDPC 0x60 |
| 235 | #define STATS_RFPC 0x64 |
| 236 | #define STATS_RUPC 0x68 |
| 237 | #define STATS_RMPC 0x6C |
| 238 | #define STATS_RBPC 0x70 |
| 239 | #define STATS_RAEPC 0x74 |
| 240 | #define STATS_RCEPC 0x78 |
| 241 | #define STATS_RUSPC 0x7C |
| 242 | #define STATS_RFEPC 0x80 |
| 243 | #define STATS_ROSPC 0x84 |
| 244 | #define STATS_RJEPC 0x88 |
| 245 | #define STATS_RPPC 0x8C |
| 246 | #define STATS_RL64PC 0x90 |
| 247 | #define STATS_RL65PC 0x94 |
| 248 | #define STATS_RL128PC 0x98 |
| 249 | #define STATS_RL256PC 0x9C |
| 250 | #define STATS_RL512PC 0xA0 |
| 251 | #define STATS_RL1024PC 0xA4 |
| 252 | #define STATS_ROC 0xA8 |
| 253 | #define STATS_RDPC_CTRL 0xB0 |
| 254 | #define STATS_RDPC_ING 0xB4 |
| 255 | #define STATS_RDPC_ARL 0xB8 |
| 256 | |
| 257 | #define SYS_CTRL 0x7000 |
| 258 | #define SW_PHY_RST BIT(2) |
| 259 | #define SW_SYS_RST BIT(1) |
| 260 | #define SW_REG_RST BIT(0) |
| 261 | |
| 262 | #define SYS_INT_EN 0x7008 |
| 263 | #define SYS_INT_STS 0x700c |
| 264 | #define MAC_PC_INT BIT(16) |
| 265 | #define PHY_INT(p) BIT((p) + 8) |
| 266 | #define PHY_LC_INT(p) BIT(p) |
| 267 | |
| 268 | #define PHY_IAC 0x701c |
| 269 | #define PHY_ACS_ST BIT(31) |
| 270 | #define MDIO_REG_ADDR_S 25 |
| 271 | #define MDIO_REG_ADDR_M 0x3e000000 |
| 272 | #define MDIO_PHY_ADDR_S 20 |
| 273 | #define MDIO_PHY_ADDR_M 0x1f00000 |
| 274 | #define MDIO_CMD_S 18 |
| 275 | #define MDIO_CMD_M 0xc0000 |
| 276 | #define MDIO_ST_S 16 |
| 277 | #define MDIO_ST_M 0x30000 |
| 278 | #define MDIO_RW_DATA_S 0 |
| 279 | #define MDIO_RW_DATA_M 0xffff |
| 280 | |
| 281 | /* MDIO_CMD: MDIO commands */ |
| 282 | #define MDIO_CMD_ADDR 0 |
| 283 | #define MDIO_CMD_WRITE 1 |
| 284 | #define MDIO_CMD_READ 2 |
| 285 | #define MDIO_CMD_READ_C45 3 |
| 286 | |
| 287 | /* MDIO_ST: MDIO start field */ |
| 288 | #define MDIO_ST_C45 0 |
| 289 | #define MDIO_ST_C22 1 |
| 290 | |
| 291 | #define HWSTRAP 0x7800 |
| 292 | #define MHWSTRAP 0x7804 |
| 293 | |
| 294 | /* Internal GPHY Page Control Register */ |
| 295 | #define PHY_CL22_PAGE_CTRL 0x1f |
| 296 | #define PHY_TR_PAGE 0x52b5 |
| 297 | |
| 298 | /* Internal GPHY Token Ring Access Registers */ |
| 299 | #define PHY_TR_CTRL 0x10 |
| 300 | #define PHY_TR_LOW_DATA 0x11 |
| 301 | #define PHY_TR_HIGH_DATA 0x12 |
| 302 | |
| 303 | /* Fields of PHY_TR_CTRL */ |
| 304 | #define PHY_TR_PKT_XMT_STA BIT(15) |
| 305 | #define PHY_TR_WR_S 13 |
| 306 | #define PHY_TR_CH_ADDR_S 11 |
| 307 | #define PHY_TR_NODE_ADDR_S 7 |
| 308 | #define PHY_TR_DATA_ADDR_S 1 |
| 309 | |
| 310 | enum phy_tr_wr { |
| 311 | PHY_TR_WRITE = 0, |
| 312 | PHY_TR_READ = 1, |
| 313 | }; |
| 314 | |
| 315 | /* Helper macro for GPHY Token Ring Access */ |
| 316 | #define PHY_TR_LOW_VAL(x) ((x) & 0xffff) |
| 317 | #define PHY_TR_HIGH_VAL(x) (((x) & 0xff0000) >> 16) |
| 318 | |
| 319 | /* Token Ring Channels */ |
| 320 | #define PMA_CH 0x1 |
| 321 | #define DSP_CH 0x2 |
| 322 | |
| 323 | /* Token Ring Nodes */ |
| 324 | #define PMA_NOD 0xf |
| 325 | #define DSP_NOD 0xd |
| 326 | |
| 327 | /* Token Ring register range */ |
| 328 | enum tr_pma_reg_addr { |
| 329 | PMA_MIN = 0x0, |
| 330 | PMA_01 = 0x1, |
| 331 | PMA_17 = 0x17, |
| 332 | PMA_18 = 0x18, |
| 333 | PMA_MAX = 0x3d, |
| 334 | }; |
| 335 | |
| 336 | enum tr_dsp_reg_addr { |
| 337 | DSP_MIN = 0x0, |
| 338 | DSP_06 = 0x6, |
| 339 | DSP_08 = 0x8, |
| 340 | DSP_0f = 0xf, |
| 341 | DSP_10 = 0x10, |
| 342 | DSP_MAX = 0x3e, |
| 343 | }; |
| 344 | #endif /* _MT753X_REGS_H_ */ |