blob: 7c468d8b2271a52eec8582e136f20ee0f9ac908e [file] [log] [blame]
developer2cdaeb12022-10-04 20:25:05 +08001Index: linux-5.4.203/drivers/net/dsa/mt7530.c
2===================================================================
3--- linux-5.4.203.orig/drivers/net/dsa/mt7530.c
4+++ linux-5.4.203/drivers/net/dsa/mt7530.c
5@@ -19,6 +19,7 @@
6 #include <linux/reset.h>
7 #include <linux/gpio/consumer.h>
8 #include <net/dsa.h>
9+#include <linux/of_address.h>
10
11 #include "mt7530.h"
12 #include "mt7530_nl.h"
13@@ -170,28 +171,44 @@ core_clear(struct mt7530_priv *priv, u32
14 core_rmw(priv, reg, val, 0);
15 }
16
17+static void
18+mtk_w32(struct mt7530_priv *priv, u32 val, unsigned reg)
19+{
20+ __raw_writel(val, priv->base + reg);
21+}
22+
23+static u32
24+mtk_r32(struct mt7530_priv *priv, unsigned reg)
25+{
26+ return __raw_readl(priv->base + reg);
27+}
28+
29 static int
30 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
31 {
32 struct mii_bus *bus = priv->bus;
33 u16 page, r, lo, hi;
34- int ret;
35-
36- page = (reg >> 6) & 0x3ff;
37- r = (reg >> 2) & 0xf;
38- lo = val & 0xffff;
39- hi = val >> 16;
40-
41- /* MT7530 uses 31 as the pseudo port */
42- ret = bus->write(bus, 0x1f, 0x1f, page);
43- if (ret < 0)
44- goto err;
45+ int ret = 0;
46
47- ret = bus->write(bus, 0x1f, r, lo);
48- if (ret < 0)
49- goto err;
50+ if (priv->direct_access){
51+ mtk_w32(priv, val, reg);
52+ } else {
53+ page = (reg >> 6) & 0x3ff;
54+ r = (reg >> 2) & 0xf;
55+ lo = val & 0xffff;
56+ hi = val >> 16;
57+
58+ /* MT7530 uses 31 as the pseudo port */
59+ ret = bus->write(bus, 0x1f, 0x1f, page);
60+ if (ret < 0)
61+ goto err;
62+
63+ ret = bus->write(bus, 0x1f, r, lo);
64+ if (ret < 0)
65+ goto err;
66
67- ret = bus->write(bus, 0x1f, 0x10, hi);
68+ ret = bus->write(bus, 0x1f, 0x10, hi);
69+ }
70 err:
71 if (ret < 0)
72 dev_err(&bus->dev,
73@@ -206,21 +223,25 @@ mt7530_mii_read(struct mt7530_priv *priv
74 u16 page, r, lo, hi;
75 int ret;
76
77- page = (reg >> 6) & 0x3ff;
78- r = (reg >> 2) & 0xf;
79+ if (priv->direct_access){
80+ return mtk_r32(priv, reg);
81+ } else {
82+ page = (reg >> 6) & 0x3ff;
83+ r = (reg >> 2) & 0xf;
84
85- /* MT7530 uses 31 as the pseudo port */
86- ret = bus->write(bus, 0x1f, 0x1f, page);
87- if (ret < 0) {
88- dev_err(&bus->dev,
89- "failed to read mt7530 register\n");
90- return ret;
91- }
92+ /* MT7530 uses 31 as the pseudo port */
93+ ret = bus->write(bus, 0x1f, 0x1f, page);
94+ if (ret < 0) {
95+ dev_err(&bus->dev,
96+ "failed to read mt7530 register\n");
97+ return ret;
98+ }
99
100- lo = bus->read(bus, 0x1f, r);
101- hi = bus->read(bus, 0x1f, 0x10);
102+ lo = bus->read(bus, 0x1f, r);
103+ hi = bus->read(bus, 0x1f, 0x10);
104
105- return (hi << 16) | (lo & 0xffff);
106+ return (hi << 16) | (lo & 0xffff);
107+ }
108 }
109
110 void
111@@ -1906,9 +1927,9 @@ mt7531_phy_supported(struct dsa_switch *
112 if (mt7531_is_rgmii_port(priv, port))
113 return phy_interface_mode_is_rgmii(state->interface);
114 fallthrough;
115- case 6: /* 1st cpu port supports sgmii/8023z only */
116- if (state->interface != PHY_INTERFACE_MODE_SGMII &&
117- !phy_interface_mode_is_8023z(state->interface))
118+ case 6: /* 1st cpu port supports sgmii/8023z/usxgmii/10gkr */
119+ if (state->interface != PHY_INTERFACE_MODE_SGMII && state->interface != PHY_INTERFACE_MODE_USXGMII &&
120+ state->interface != PHY_INTERFACE_MODE_10GKR && !phy_interface_mode_is_8023z(state->interface))
121 goto unsupported;
122 break;
123 default:
124@@ -2017,6 +2038,13 @@ static void mt7531_sgmii_validate(struct
125 phylink_set(supported, 1000baseX_Full);
126 phylink_set(supported, 2500baseX_Full);
127 phylink_set(supported, 2500baseT_Full);
128+ phylink_set(supported, 10000baseKR_Full);
129+ phylink_set(supported, 10000baseT_Full);
130+ phylink_set(supported, 10000baseCR_Full);
131+ phylink_set(supported, 10000baseSR_Full);
132+ phylink_set(supported, 10000baseLR_Full);
133+ phylink_set(supported, 10000baseLRM_Full);
134+ phylink_set(supported, 10000baseER_Full);
135 }
136 }
137
138@@ -2165,6 +2193,8 @@ mt7531_mac_config(struct dsa_switch *ds,
139 case PHY_INTERFACE_MODE_NA:
140 case PHY_INTERFACE_MODE_1000BASEX:
141 case PHY_INTERFACE_MODE_2500BASEX:
142+ case PHY_INTERFACE_MODE_USXGMII:
143+ case PHY_INTERFACE_MODE_10GKR:
144 if (phylink_autoneg_inband(mode))
145 return -EINVAL;
146
147@@ -2302,8 +2332,8 @@ static void mt753x_phylink_mac_link_up(s
148 /* MT753x MAC works in 1G full duplex mode for all up-clocked
149 * variants.
150 */
151- if (interface == PHY_INTERFACE_MODE_TRGMII ||
152- (phy_interface_mode_is_8023z(interface))) {
153+ if (interface == PHY_INTERFACE_MODE_TRGMII || interface == PHY_INTERFACE_MODE_USXGMII ||
154+ interface == PHY_INTERFACE_MODE_10GKR || (phy_interface_mode_is_8023z(interface))) {
155 speed = SPEED_1000;
156 duplex = DUPLEX_FULL;
157 }
158@@ -2402,8 +2432,8 @@ mt753x_phylink_validate(struct dsa_switc
159
160 phylink_set_port_modes(mask);
161
162- if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
163- !phy_interface_mode_is_8023z(state->interface)) {
164+ if (state->interface != PHY_INTERFACE_MODE_TRGMII || state->interface != PHY_INTERFACE_MODE_USXGMII ||
165+ state->interface != PHY_INTERFACE_MODE_10GKR || !phy_interface_mode_is_8023z(state->interface)) {
166 phylink_set(mask, 10baseT_Half);
167 phylink_set(mask, 10baseT_Full);
168 phylink_set(mask, 100baseT_Half);
169@@ -2607,6 +2637,66 @@ mt753x_phy_write(struct dsa_switch *ds,
170 return priv->info->phy_write(ds, port, regnum, val);
171 }
172
173+static int
174+mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
175+{
176+ return 0;
177+}
178+
179+static int
180+mt7988_setup(struct dsa_switch *ds)
181+{
182+ struct mt7530_priv *priv = ds->priv;
183+ u32 unused_pm = 0;
184+ int ret, i;
185+
186+ /* Reset the switch through internal reset */
187+ mt7530_write(priv, MT7530_SYS_CTRL,
188+ SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST);
189+
190+ /* BPDU to CPU port */
191+ mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
192+ BIT(MT7530_CPU_PORT));
193+ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
194+ MT753X_BPDU_CPU_ONLY);
195+
196+ /* Enable and reset MIB counters */
197+ mt7530_mib_reset(ds);
198+
199+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
200+ /* Disable forwarding by default on all ports */
201+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
202+ PCR_MATRIX_CLR);
203+
204+ mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
205+
206+ if (dsa_is_unused_port(ds, i))
207+ unused_pm |= BIT(i);
208+ else if (dsa_is_cpu_port(ds, i))
209+ mt753x_cpu_port_enable(ds, i);
210+ else
211+ mt7530_port_disable(ds, i);
212+
213+ /* Enable consistent egress tag */
214+ mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
215+ PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
216+ }
217+
218+ mt7531_phy_setup(ds);
219+
220+ /* Group and enable unused ports as a standalone dumb switch. */
221+ setup_unused_ports(ds, unused_pm);
222+
223+ ds->configure_vlan_while_not_filtering = true;
224+
225+ /* Flush the FDB table */
226+ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
227+ if (ret < 0)
228+ return ret;
229+
230+ return 0;
231+}
232+
233 static const struct dsa_switch_ops mt7530_switch_ops = {
234 .get_tag_protocol = mtk_get_tag_protocol,
235 .setup = mt753x_setup,
236@@ -2676,12 +2766,28 @@ static const struct mt753x_info mt753x_t
237 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
238 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
239 },
240+ [ID_MT7988] = {
241+ .id = ID_MT7988,
242+ .sw_setup = mt7988_setup,
243+ .phy_read = mt7531_ind_phy_read,
244+ .phy_write = mt7531_ind_phy_write,
245+ .pad_setup = mt7988_pad_setup,
246+ .cpu_port_config = mt7531_cpu_port_config,
247+ .phy_mode_supported = mt7531_phy_supported,
248+ .mac_port_validate = mt7531_mac_port_validate,
249+ .mac_port_get_state = mt7531_phylink_mac_link_state,
250+ .mac_port_config = mt7531_mac_config,
251+ .mac_pcs_an_restart = mt7531_sgmii_restart_an,
252+ .mac_pcs_link_up = mt7531_sgmii_link_up_force,
253+ },
254+
255 };
256
257 static const struct of_device_id mt7530_of_match[] = {
258 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
259 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
260 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
261+ { .compatible = "mediatek,mt7988", .data = &mt753x_table[ID_MT7988], },
262 { /* sentinel */ },
263 };
264 MODULE_DEVICE_TABLE(of, mt7530_of_match);
265@@ -2691,6 +2797,7 @@ mt7530_probe(struct mdio_device *mdiodev
266 {
267 struct mt7530_priv *priv;
268 struct device_node *dn;
269+ struct device_node *switch_node = NULL;
270 int ret;
271
272 dn = mdiodev->dev.of_node;
273@@ -2760,6 +2867,16 @@ mt7530_probe(struct mdio_device *mdiodev
274 }
275 }
276
277+ switch_node = of_find_node_by_name(NULL, "switch0");
278+ if(switch_node) {
279+ priv->base = of_iomap(switch_node, 0);
280+ if(priv->base == NULL){
281+ dev_err(&mdiodev->dev, "of_iomap failed\n");
282+ return -ENOMEM;
283+ }
284+ priv->direct_access = 1;
285+ }
286+
287 priv->bus = mdiodev->bus;
288 priv->dev = &mdiodev->dev;
289 priv->ds->priv = priv;
290@@ -2768,9 +2885,12 @@ mt7530_probe(struct mdio_device *mdiodev
291 dev_set_drvdata(&mdiodev->dev, priv);
292
293 ret = dsa_register_switch(priv->ds);
294- if (ret)
295- return ret;
296-
297+ if (ret) {
298+ if(priv->base)
299+ iounmap(priv->base);
300+
301+ return ret;
302+ }
303 mt7530_nl_init(&priv);
304
305 return 0;
306@@ -2795,6 +2915,9 @@ mt7530_remove(struct mdio_device *mdiode
307 dsa_unregister_switch(priv->ds);
308 mutex_destroy(&priv->reg_mutex);
309
310+ if(priv->base)
311+ iounmap(priv->base);
312+
313 mt7530_nl_exit();
314 }
315
316Index: linux-5.4.203/drivers/net/dsa/mt7530.h
317===================================================================
318--- linux-5.4.203.orig/drivers/net/dsa/mt7530.h
319+++ linux-5.4.203/drivers/net/dsa/mt7530.h
320@@ -16,6 +16,7 @@ enum mt753x_id {
321 ID_MT7530 = 0,
322 ID_MT7621 = 1,
323 ID_MT7531 = 2,
324+ ID_MT7988 = 3,
325 };
326
327 #define NUM_TRGMII_CTRL 5
328@@ -51,11 +52,11 @@ enum mt753x_id {
329 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
330 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
331
332-#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
333+#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
334 MT7531_CFC : MT7530_MFC)
335-#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
336+#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
337 MT7531_MIRROR_EN : MIRROR_EN)
338-#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
339+#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
340 MT7531_MIRROR_MASK : MIRROR_MASK)
341
342 /* Registers for BPDU and PAE frame control*/
343@@ -261,7 +262,7 @@ enum mt7530_vlan_port_attr {
344 MT7531_FORCE_DPX | \
345 MT7531_FORCE_RX_FC | \
346 MT7531_FORCE_TX_FC)
347-#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
348+#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
349 MT7531_FORCE_MODE : \
350 PMCR_FORCE_MODE)
351 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
352@@ -733,6 +734,8 @@ struct mt7530_priv {
353 struct regulator *core_pwr;
354 struct regulator *io_pwr;
355 struct gpio_desc *reset;
356+ void __iomem *base;
357+ int direct_access;
358 const struct mt753x_info *info;
359 unsigned int id;
360 bool mcm;