blob: 2ef225a8b30d36bb6bf942ddac0714c8557e1914 [file] [log] [blame]
developer4721e252022-06-21 16:41:28 +08001From f4838210b5e80adfa3af028721ee040edff79a48 Mon Sep 17 00:00:00 2001
developerf7d25b02022-04-12 16:20:16 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerbd398d52022-06-06 20:53:24 +08003Date: Mon, 6 Jun 2022 20:22:35 +0800
4Subject: [PATCH] mt76:remove WED support patch for build err
developerf7d25b02022-04-12 16:20:16 +08005
developerf7d25b02022-04-12 16:20:16 +08006---
developer4721e252022-06-21 16:41:28 +08007 dma.c | 160 ++++++++++--------------------------------------
8 mac80211.c | 4 +-
9 mmio.c | 9 +--
10 mt76.h | 25 ++------
11 mt7603/dma.c | 8 +--
12 mt7615/dma.c | 6 +-
13 mt76x02_mmio.c | 4 +-
14 mt7915/dma.c | 43 ++-----------
15 mt7915/mac.c | 139 ++++++++++-------------------------------
16 mt7915/mac.h | 2 -
17 mt7915/main.c | 36 -----------
18 mt7915/mcu.c | 3 -
19 mt7915/mmio.c | 29 +++------
20 mt7915/mt7915.h | 2 -
21 mt7915/pci.c | 96 +++--------------------------
22 mt7915/regs.h | 17 +----
23 mt7921/dma.c | 2 +-
24 tx.c | 16 +----
developerf64861f2022-06-22 11:44:53 +080025 18 files changed, 105 insertions(+), 496 deletions(-)
developerf7d25b02022-04-12 16:20:16 +080026
27diff --git a/dma.c b/dma.c
developer4721e252022-06-21 16:41:28 +080028index f6f5f12..3f7456b 100644
developerf7d25b02022-04-12 16:20:16 +080029--- a/dma.c
30+++ b/dma.c
31@@ -7,36 +7,9 @@
32 #include "mt76.h"
33 #include "dma.h"
34
35-#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
36-
37-#define Q_READ(_dev, _q, _field) ({ \
38- u32 _offset = offsetof(struct mt76_queue_regs, _field); \
39- u32 _val; \
40- if ((_q)->flags & MT_QFLAG_WED) \
41- _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \
42- ((_q)->wed_regs + \
43- _offset)); \
44- else \
45- _val = readl(&(_q)->regs->_field); \
46- _val; \
47-})
48-
49-#define Q_WRITE(_dev, _q, _field, _val) do { \
50- u32 _offset = offsetof(struct mt76_queue_regs, _field); \
51- if ((_q)->flags & MT_QFLAG_WED) \
52- mtk_wed_device_reg_write(&(_dev)->mmio.wed, \
53- ((_q)->wed_regs + _offset), \
54- _val); \
55- else \
56- writel(_val, &(_q)->regs->_field); \
57-} while (0)
58-
59-#else
60-
61-#define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field)
62-#define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field)
63+#define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field)
64+#define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field)
65
66-#endif
67
68 static struct mt76_txwi_cache *
69 mt76_alloc_txwi(struct mt76_dev *dev)
70@@ -138,6 +111,36 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
71 mt76_dma_sync_idx(dev, q);
72 }
73
74+static int
75+mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
76+ int idx, int n_desc, int bufsize,
77+ u32 ring_base)
78+{
79+ int size;
80+
81+ spin_lock_init(&q->lock);
82+ spin_lock_init(&q->cleanup_lock);
83+
84+ q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
85+ q->ndesc = n_desc;
86+ q->buf_size = bufsize;
87+ q->hw_idx = idx;
88+
89+ size = q->ndesc * sizeof(struct mt76_desc);
90+ q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
91+ if (!q->desc)
92+ return -ENOMEM;
93+
94+ size = q->ndesc * sizeof(*q->entry);
95+ q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
96+ if (!q->entry)
97+ return -ENOMEM;
98+
99+ mt76_dma_queue_reset(dev, q);
100+
101+ return 0;
102+}
103+
104 static int
105 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
106 struct mt76_queue_buf *buf, int nbufs, u32 info,
developer4c6b6002022-05-30 16:36:44 +0800107@@ -482,85 +485,6 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developerf7d25b02022-04-12 16:20:16 +0800108 return frames;
109 }
110
111-static int
112-mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
113-{
114-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
115- struct mtk_wed_device *wed = &dev->mmio.wed;
116- int ret, type, ring;
117- u8 flags = q->flags;
118-
119- if (!mtk_wed_device_active(wed))
120- q->flags &= ~MT_QFLAG_WED;
121-
122- if (!(q->flags & MT_QFLAG_WED))
123- return 0;
124-
125- type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
126- ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags);
127-
128- switch (type) {
129- case MT76_WED_Q_TX:
130- ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs);
131- if (!ret)
132- q->wed_regs = wed->tx_ring[ring].reg_base;
133- break;
134- case MT76_WED_Q_TXFREE:
135- /* WED txfree queue needs ring to be initialized before setup */
136- q->flags = 0;
137- mt76_dma_queue_reset(dev, q);
138- mt76_dma_rx_fill(dev, q);
139- q->flags = flags;
140-
141- ret = mtk_wed_device_txfree_ring_setup(wed, q->regs);
142- if (!ret)
143- q->wed_regs = wed->txfree_ring.reg_base;
144- break;
145- default:
146- ret = -EINVAL;
147- }
148-
149- return ret;
150-#else
151- return 0;
152-#endif
153-}
154-
155-static int
156-mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
157- int idx, int n_desc, int bufsize,
158- u32 ring_base)
159-{
160- int ret, size;
161-
162- spin_lock_init(&q->lock);
163- spin_lock_init(&q->cleanup_lock);
164-
165- q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
166- q->ndesc = n_desc;
167- q->buf_size = bufsize;
168- q->hw_idx = idx;
169-
170- size = q->ndesc * sizeof(struct mt76_desc);
171- q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
172- if (!q->desc)
173- return -ENOMEM;
174-
175- size = q->ndesc * sizeof(*q->entry);
176- q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
177- if (!q->entry)
178- return -ENOMEM;
179-
180- ret = mt76_dma_wed_setup(dev, q);
181- if (ret)
182- return ret;
183-
184- if (q->flags != MT_WED_Q_TXFREE)
185- mt76_dma_queue_reset(dev, q);
186-
187- return 0;
188-}
189-
190 static void
191 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
192 {
developer4c6b6002022-05-30 16:36:44 +0800193@@ -642,29 +566,14 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developerf7d25b02022-04-12 16:20:16 +0800194 static int
195 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
196 {
197- int len, data_len, done = 0, dma_idx;
198+ int len, data_len, done = 0;
199 struct sk_buff *skb;
200 unsigned char *data;
201- bool check_ddone = false;
202 bool more;
203
204- if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) &&
205- q->flags == MT_WED_Q_TXFREE) {
206- dma_idx = Q_READ(dev, q, dma_idx);
207- check_ddone = true;
208- }
209-
210 while (done < budget) {
211 u32 info;
212
213- if (check_ddone) {
214- if (q->tail == dma_idx)
215- dma_idx = Q_READ(dev, q, dma_idx);
216-
217- if (q->tail == dma_idx)
218- break;
219- }
220-
221 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
222 if (!data)
223 break;
developer4c6b6002022-05-30 16:36:44 +0800224@@ -805,8 +714,5 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
developerf7d25b02022-04-12 16:20:16 +0800225 }
226
227 mt76_free_pending_txwi(dev);
228-
229- if (mtk_wed_device_active(&dev->mmio.wed))
230- mtk_wed_device_detach(&dev->mmio.wed);
231 }
232 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
233diff --git a/mac80211.c b/mac80211.c
developer4721e252022-06-21 16:41:28 +0800234index 5600a09..7878446 100644
developerf7d25b02022-04-12 16:20:16 +0800235--- a/mac80211.c
236+++ b/mac80211.c
developerf64861f2022-06-22 11:44:53 +0800237@@ -1605,7 +1605,7 @@ EXPORT_SYMBOL_GPL(mt76_get_antenna);
developerf7d25b02022-04-12 16:20:16 +0800238
239 struct mt76_queue *
240 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
241- int ring_base, u32 flags)
242+ int ring_base)
243 {
244 struct mt76_queue *hwq;
245 int err;
developerf64861f2022-06-22 11:44:53 +0800246@@ -1614,8 +1614,6 @@ mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
developerf7d25b02022-04-12 16:20:16 +0800247 if (!hwq)
248 return ERR_PTR(-ENOMEM);
249
250- hwq->flags = flags;
251-
252 err = dev->queue_ops->alloc(dev, hwq, idx, n_desc, 0, ring_base);
253 if (err < 0)
254 return ERR_PTR(err);
255diff --git a/mmio.c b/mmio.c
developer4721e252022-06-21 16:41:28 +0800256index 86e3d2a..26353b6 100644
developerf7d25b02022-04-12 16:20:16 +0800257--- a/mmio.c
258+++ b/mmio.c
259@@ -73,13 +73,8 @@ void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr,
260 spin_lock_irqsave(&dev->mmio.irq_lock, flags);
261 dev->mmio.irqmask &= ~clear;
262 dev->mmio.irqmask |= set;
263- if (addr) {
264- if (mtk_wed_device_active(&dev->mmio.wed))
265- mtk_wed_device_irq_set_mask(&dev->mmio.wed,
266- dev->mmio.irqmask);
267- else
268- mt76_mmio_wr(dev, addr, dev->mmio.irqmask);
269- }
270+ if (addr)
271+ mt76_mmio_wr(dev, addr, dev->mmio.irqmask);
272 spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);
273 }
274 EXPORT_SYMBOL_GPL(mt76_set_irq_mask);
275diff --git a/mt76.h b/mt76.h
developer4721e252022-06-21 16:41:28 +0800276index 062c5ce..ed1924c 100644
developerf7d25b02022-04-12 16:20:16 +0800277--- a/mt76.h
278+++ b/mt76.h
279@@ -13,7 +13,6 @@
280 #include <linux/leds.h>
281 #include <linux/usb.h>
282 #include <linux/average.h>
283-#include <linux/soc/mediatek/mtk_wed.h>
284 #include <net/mac80211.h>
285 #include "util.h"
286 #include "testmode.h"
287@@ -27,16 +26,6 @@
288
289 #define MT76_TOKEN_FREE_THR 64
290
291-#define MT_QFLAG_WED_RING GENMASK(1, 0)
292-#define MT_QFLAG_WED_TYPE GENMASK(3, 2)
293-#define MT_QFLAG_WED BIT(4)
294-
295-#define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
296- FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
297- FIELD_PREP(MT_QFLAG_WED_RING, _n))
298-#define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
299-#define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
300-
301 struct mt76_dev;
302 struct mt76_phy;
303 struct mt76_wcid;
304@@ -186,9 +175,6 @@ struct mt76_queue {
305 u8 buf_offset;
306 u8 hw_idx;
307 u8 qid;
308- u8 flags;
309-
310- u32 wed_regs;
311
312 dma_addr_t desc_dma;
313 struct sk_buff *rx_head;
314@@ -556,8 +542,6 @@ struct mt76_mmio {
315 void __iomem *regs;
316 spinlock_t irq_lock;
317 u32 irqmask;
318-
319- struct mtk_wed_device wed;
320 };
321
322 struct mt76_rx_status {
developer4c6b6002022-05-30 16:36:44 +0800323@@ -782,7 +766,6 @@ struct mt76_dev {
developerf7d25b02022-04-12 16:20:16 +0800324
325 spinlock_t token_lock;
326 struct idr token;
327- u16 wed_token_count;
328 u16 token_count;
329 u16 token_size;
330
developer4c6b6002022-05-30 16:36:44 +0800331@@ -1008,14 +991,14 @@ int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len);
developerf7d25b02022-04-12 16:20:16 +0800332
333 struct mt76_queue *
334 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
335- int ring_base, u32 flags);
336+ int ring_base);
337 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx);
338 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
339- int n_desc, int ring_base, u32 flags)
340+ int n_desc, int ring_base)
341 {
342 struct mt76_queue *q;
343
344- q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags);
345+ q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base);
346 if (IS_ERR(q))
347 return PTR_ERR(q);
348
developer4c6b6002022-05-30 16:36:44 +0800349@@ -1030,7 +1013,7 @@ static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
developerf7d25b02022-04-12 16:20:16 +0800350 {
351 struct mt76_queue *q;
352
353- q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0);
354+ q = mt76_init_queue(dev, qid, idx, n_desc, ring_base);
355 if (IS_ERR(q))
356 return PTR_ERR(q);
357
358diff --git a/mt7603/dma.c b/mt7603/dma.c
developer4721e252022-06-21 16:41:28 +0800359index 590cff9..37b092e 100644
developerf7d25b02022-04-12 16:20:16 +0800360--- a/mt7603/dma.c
361+++ b/mt7603/dma.c
362@@ -173,13 +173,13 @@ int mt7603_dma_init(struct mt7603_dev *dev)
363
364 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
365 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],
366- MT7603_TX_RING_SIZE, MT_TX_RING_BASE, 0);
367+ MT7603_TX_RING_SIZE, MT_TX_RING_BASE);
368 if (ret)
369 return ret;
370 }
371
372 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
373- MT7603_PSD_RING_SIZE, MT_TX_RING_BASE, 0);
374+ MT7603_PSD_RING_SIZE, MT_TX_RING_BASE);
375 if (ret)
376 return ret;
377
378@@ -189,12 +189,12 @@ int mt7603_dma_init(struct mt7603_dev *dev)
379 return ret;
380
381 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_BEACON, MT_TX_HW_QUEUE_BCN,
382- MT_MCU_RING_SIZE, MT_TX_RING_BASE, 0);
383+ MT_MCU_RING_SIZE, MT_TX_RING_BASE);
384 if (ret)
385 return ret;
386
387 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_CAB, MT_TX_HW_QUEUE_BMC,
388- MT_MCU_RING_SIZE, MT_TX_RING_BASE, 0);
389+ MT_MCU_RING_SIZE, MT_TX_RING_BASE);
390 if (ret)
391 return ret;
392
393diff --git a/mt7615/dma.c b/mt7615/dma.c
developer4721e252022-06-21 16:41:28 +0800394index 3a79a2d..00aefea 100644
developerf7d25b02022-04-12 16:20:16 +0800395--- a/mt7615/dma.c
396+++ b/mt7615/dma.c
397@@ -26,14 +26,14 @@ mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
398 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
399 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],
400 MT7615_TX_RING_SIZE / 2,
401- MT_TX_RING_BASE, 0);
402+ MT_TX_RING_BASE);
403 if (ret)
404 return ret;
405 }
406
407 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT,
408 MT7615_TX_MGMT_RING_SIZE,
409- MT_TX_RING_BASE, 0);
410+ MT_TX_RING_BASE);
411 if (ret)
412 return ret;
413
414@@ -55,7 +55,7 @@ mt7615_init_tx_queues(struct mt7615_dev *dev)
415 return mt7622_init_tx_queues_multi(dev);
416
417 ret = mt76_init_tx_queue(&dev->mphy, 0, 0, MT7615_TX_RING_SIZE,
418- MT_TX_RING_BASE, 0);
419+ MT_TX_RING_BASE);
420 if (ret)
421 return ret;
422
423diff --git a/mt76x02_mmio.c b/mt76x02_mmio.c
developer4721e252022-06-21 16:41:28 +0800424index 0fa3c7c..8bcd8af 100644
developerf7d25b02022-04-12 16:20:16 +0800425--- a/mt76x02_mmio.c
426+++ b/mt76x02_mmio.c
427@@ -191,13 +191,13 @@ int mt76x02_dma_init(struct mt76x02_dev *dev)
428 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
429 ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),
430 MT76x02_TX_RING_SIZE,
431- MT_TX_RING_BASE, 0);
432+ MT_TX_RING_BASE);
433 if (ret)
434 return ret;
435 }
436
437 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
438- MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE, 0);
439+ MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE);
440 if (ret)
441 return ret;
442
443diff --git a/mt7915/dma.c b/mt7915/dma.c
developer4721e252022-06-21 16:41:28 +0800444index 9e3d14d..4358e9b 100644
developerf7d25b02022-04-12 16:20:16 +0800445--- a/mt7915/dma.c
446+++ b/mt7915/dma.c
447@@ -8,16 +8,9 @@
448 static int
449 mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base)
450 {
451- struct mt7915_dev *dev = phy->dev;
452 int i, err;
453
454- if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) {
455- ring_base = MT_WED_TX_RING_BASE;
456- idx -= MT_TXQ_ID(0);
457- }
458-
459- err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, ring_base,
460- MT_WED_Q_TX(idx));
461+ err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, ring_base);
462 if (err < 0)
463 return err;
464
465@@ -326,14 +319,6 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
466 if (dev->dbdc_support || dev->phy.band_idx)
467 irq_mask |= MT_INT_BAND1_RX_DONE;
468
469- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
470- u32 wed_irq_mask = irq_mask;
471-
472- wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
473- mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
474- mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
475- }
476-
477 mt7915_irq_enable(dev, irq_mask);
478
479 return 0;
480@@ -342,7 +327,6 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
481 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
482 {
483 struct mt76_dev *mdev = &dev->mt76;
484- u32 wa_rx_base, wa_rx_idx;
485 u32 hif1_ofs = 0;
486 int ret;
487
488@@ -355,17 +339,6 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
489
490 mt7915_dma_disable(dev, true);
491
492- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
493- mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
494-
495- mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
496- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
497- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
498- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
499- } else {
500- mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
501- }
502-
503 /* init tx queue */
504 ret = mt7915_init_tx_queues(&dev->phy,
505 MT_TXQ_ID(dev->phy.band_idx),
506@@ -417,17 +390,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
507 return ret;
508
509 /* event from WA */
510- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
511- wa_rx_base = MT_WED_RX_RING_BASE;
512- wa_rx_idx = MT7915_RXQ_MCU_WA;
513- dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE;
514- } else {
515- wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA);
516- wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA);
517- }
518 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
519- wa_rx_idx, MT7915_RX_MCU_RING_SIZE,
520- MT_RX_BUF_SIZE, wa_rx_base);
521+ MT_RXQ_ID(MT_RXQ_MCU_WA),
522+ MT7915_RX_MCU_RING_SIZE,
523+ MT_RX_BUF_SIZE,
524+ MT_RXQ_RING_BASE(MT_RXQ_MCU_WA));
525 if (ret)
526 return ret;
527
528diff --git a/mt7915/mac.c b/mt7915/mac.c
developer4721e252022-06-21 16:41:28 +0800529index fd0dd50..1bf3b41 100644
developerf7d25b02022-04-12 16:20:16 +0800530--- a/mt7915/mac.c
531+++ b/mt7915/mac.c
developerf64861f2022-06-22 11:44:53 +0800532@@ -815,29 +815,6 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developerf7d25b02022-04-12 16:20:16 +0800533 return 0;
534 }
535
536-u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
537-{
developerf64861f2022-06-22 11:44:53 +0800538- struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE;
developerf7d25b02022-04-12 16:20:16 +0800539- __le32 *txwi = ptr;
540- u32 val;
541-
542- memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp));
543-
544- val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) |
545- FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT);
546- txwi[0] = cpu_to_le32(val);
547-
548- val = MT_TXD1_LONG_FORMAT |
549- FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3);
550- txwi[1] = cpu_to_le32(val);
551-
552- txp->token = cpu_to_le16(token_id);
553- txp->nbuf = 1;
554- txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp));
555-
556- return MT_TXD_SIZE + sizeof(*txp);
557-}
558-
559 static void
560 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
561 {
developerf64861f2022-06-22 11:44:53 +0800562@@ -863,12 +840,23 @@ mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
563 ieee80211_start_tx_ba_session(sta, tid, 0);
developerf7d25b02022-04-12 16:20:16 +0800564 }
565
developerf64861f2022-06-22 11:44:53 +0800566+/* static void */
567+/* mt7915_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t) */
568+/* { */
569+/* struct mt76_connac_fw_txp *txp; */
570+/* int i; */
571+
572+/* txp = mt76_connac_txwi_to_txp(dev, t); */
573+/* for (i = 0; i < txp->nbuf; i++) */
574+/* dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), */
575+/* le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); */
576+/* } */
577+
578 static void
579 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t,
developerf7d25b02022-04-12 16:20:16 +0800580 struct ieee80211_sta *sta, struct list_head *free_list)
581 {
582 struct mt76_dev *mdev = &dev->mt76;
583- struct mt7915_sta *msta;
584 struct mt76_wcid *wcid;
585 __le32 *txwi;
586 u16 wcid_idx;
developerf64861f2022-06-22 11:44:53 +0800587@@ -881,24 +869,13 @@ mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t,
developerf7d25b02022-04-12 16:20:16 +0800588 if (sta) {
589 wcid = (struct mt76_wcid *)sta->drv_priv;
590 wcid_idx = wcid->idx;
591+
592+ if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE)))
593+ mt7915_tx_check_aggr(sta, txwi);
594 } else {
595 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX);
596- wcid = rcu_dereference(dev->mt76.wcid[wcid_idx]);
597-
598- if (wcid && wcid->sta) {
599- msta = container_of(wcid, struct mt7915_sta, wcid);
600- sta = container_of((void *)msta, struct ieee80211_sta,
601- drv_priv);
602- spin_lock_bh(&dev->sta_poll_lock);
603- if (list_empty(&msta->poll_list))
604- list_add_tail(&msta->poll_list, &dev->sta_poll_list);
605- spin_unlock_bh(&dev->sta_poll_lock);
606- }
607 }
608
609- if (sta && likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE)))
610- mt7915_tx_check_aggr(sta, txwi);
611-
612 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list);
613
614 out:
developerf64861f2022-06-22 11:44:53 +0800615@@ -906,57 +883,31 @@ out:
developerf7d25b02022-04-12 16:20:16 +0800616 mt76_put_txwi(mdev, t);
617 }
618
619-static void
620-mt7915_mac_tx_free_prepare(struct mt7915_dev *dev)
621-{
622- struct mt76_dev *mdev = &dev->mt76;
623- struct mt76_phy *mphy_ext = mdev->phy2;
624-
625- /* clean DMA queues and unmap buffers first */
626- mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
627- mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
628- if (mphy_ext) {
629- mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false);
630- mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
631- }
632-}
633-
634-static void
635-mt7915_mac_tx_free_done(struct mt7915_dev *dev,
636- struct list_head *free_list, bool wake)
637-{
638- struct sk_buff *skb, *tmp;
639-
640- mt7915_mac_sta_poll(dev);
641-
642- if (wake)
643- mt76_set_tx_blocked(&dev->mt76, false);
644-
645- mt76_worker_schedule(&dev->mt76.tx_worker);
646-
647- list_for_each_entry_safe(skb, tmp, free_list, list) {
648- skb_list_del_init(skb);
649- napi_consume_skb(skb, 1);
650- }
651-}
652-
653 static void
654 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len)
655 {
developerf64861f2022-06-22 11:44:53 +0800656 struct mt76_connac_tx_free *free = data;
657 __le32 *tx_info = (__le32 *)(data + sizeof(*free));
developerf7d25b02022-04-12 16:20:16 +0800658 struct mt76_dev *mdev = &dev->mt76;
659+ struct mt76_phy *mphy_ext = mdev->phy2;
660 struct mt76_txwi_cache *txwi;
661 struct ieee80211_sta *sta = NULL;
developer68e1eb22022-05-09 17:02:12 +0800662 struct mt7915_sta *msta = NULL;
developerf7d25b02022-04-12 16:20:16 +0800663 LIST_HEAD(free_list);
664+ struct sk_buff *skb, *tmp;
665 void *end = data + len;
666 bool v3, wake = false;
667 u16 total, count = 0;
668 u32 txd = le32_to_cpu(free->txd);
669 __le32 *cur_info;
670
671- mt7915_mac_tx_free_prepare(dev);
672+ /* clean DMA queues and unmap buffers first */
673+ mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
674+ mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
675+ if (mphy_ext) {
676+ mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false);
677+ mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
678+ }
679
680 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT);
681 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4);
developerf64861f2022-06-22 11:44:53 +0800682@@ -1013,38 +964,17 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len)
developerf7d25b02022-04-12 16:20:16 +0800683 }
684 }
685
686- mt7915_mac_tx_free_done(dev, &free_list, wake);
687-}
688-
689-static void
690-mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len)
691-{
developerf64861f2022-06-22 11:44:53 +0800692- struct mt76_connac_tx_free *free = data;
693- __le16 *info = (__le16 *)(data + sizeof(*free));
developerf7d25b02022-04-12 16:20:16 +0800694- struct mt76_dev *mdev = &dev->mt76;
developerf7d25b02022-04-12 16:20:16 +0800695- void *end = data + len;
696- LIST_HEAD(free_list);
697- bool wake = false;
698- u8 i, count;
699-
700- mt7915_mac_tx_free_prepare(dev);
701-
702- count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl));
703- if (WARN_ON_ONCE((void *)&info[count] > end))
704- return;
705+ mt7915_mac_sta_poll(dev);
706
707- for (i = 0; i < count; i++) {
708- struct mt76_txwi_cache *txwi;
709- u16 msdu = le16_to_cpu(info[i]);
710+ if (wake)
711+ mt76_set_tx_blocked(&dev->mt76, false);
712
713- txwi = mt76_token_release(mdev, msdu, &wake);
714- if (!txwi)
715- continue;
716+ mt76_worker_schedule(&dev->mt76.tx_worker);
717
718- mt7915_txwi_free(dev, txwi, NULL, &free_list);
719+ list_for_each_entry_safe(skb, tmp, &free_list, list) {
720+ skb_list_del_init(skb);
721+ napi_consume_skb(skb, 1);
722 }
723-
724- mt7915_mac_tx_free_done(dev, &free_list, wake);
725 }
726
developerf64861f2022-06-22 11:44:53 +0800727 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data)
728@@ -1102,9 +1032,6 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developerf7d25b02022-04-12 16:20:16 +0800729 case PKT_TYPE_TXRX_NOTIFY:
730 mt7915_mac_tx_free(dev, data, len);
731 return false;
732- case PKT_TYPE_TXRX_NOTIFY_V0:
733- mt7915_mac_tx_free_v0(dev, data, len);
734- return false;
735 case PKT_TYPE_TXS:
736 for (rxd += 2; rxd + 8 <= end; rxd += 8)
737 mt7915_mac_add_txs(dev, rxd);
developerf64861f2022-06-22 11:44:53 +0800738@@ -1132,10 +1059,6 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developerf7d25b02022-04-12 16:20:16 +0800739 mt7915_mac_tx_free(dev, skb->data, skb->len);
740 napi_consume_skb(skb, 1);
741 break;
742- case PKT_TYPE_TXRX_NOTIFY_V0:
743- mt7915_mac_tx_free_v0(dev, skb->data, skb->len);
744- napi_consume_skb(skb, 1);
745- break;
746 case PKT_TYPE_RX_EVENT:
747 mt7915_mcu_rx_event(dev, skb);
748 break;
749diff --git a/mt7915/mac.h b/mt7915/mac.h
developer4721e252022-06-21 16:41:28 +0800750index 6fa9c79..9986c03 100644
developerf7d25b02022-04-12 16:20:16 +0800751--- a/mt7915/mac.h
752+++ b/mt7915/mac.h
developerf64861f2022-06-22 11:44:53 +0800753@@ -26,12 +26,10 @@ enum rx_pkt_type {
developerf7d25b02022-04-12 16:20:16 +0800754 PKT_TYPE_TXRX_NOTIFY,
755 PKT_TYPE_RX_EVENT,
756 PKT_TYPE_RX_FW_MONITOR = 0x0c,
757- PKT_TYPE_TXRX_NOTIFY_V0 = 0x18,
758 };
759
developerf7d25b02022-04-12 16:20:16 +0800760 #define MT_TX_FREE_VER GENMASK(18, 16)
761 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
762-#define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0)
763 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
764 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
765 /* 0: success, others: dropped */
766diff --git a/mt7915/main.c b/mt7915/main.c
developer4721e252022-06-21 16:41:28 +0800767index ebff255..79127b4 100644
developerf7d25b02022-04-12 16:20:16 +0800768--- a/mt7915/main.c
769+++ b/mt7915/main.c
developer4721e252022-06-21 16:41:28 +0800770@@ -1422,39 +1422,6 @@ out:
developerf7d25b02022-04-12 16:20:16 +0800771 return ret;
772 }
773
774-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
775-static int
776-mt7915_net_fill_forward_path(struct ieee80211_hw *hw,
777- struct ieee80211_vif *vif,
778- struct ieee80211_sta *sta,
779- struct net_device_path_ctx *ctx,
780- struct net_device_path *path)
781-{
782- struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
783- struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
784- struct mt7915_dev *dev = mt7915_hw_dev(hw);
785- struct mt7915_phy *phy = mt7915_hw_phy(hw);
786- struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
787-
788- if (!mtk_wed_device_active(wed))
789- return -ENODEV;
790-
791- if (msta->wcid.idx > 0xff)
792- return -EIO;
793-
794- path->type = DEV_PATH_MTK_WDMA;
795- path->dev = ctx->dev;
796- path->mtk_wdma.wdma_idx = wed->wdma_idx;
797- path->mtk_wdma.bss = mvif->mt76.idx;
798- path->mtk_wdma.wcid = msta->wcid.idx;
799- path->mtk_wdma.queue = phy != &dev->phy;
800-
801- ctx->dev = NULL;
802-
803- return 0;
804-}
805-#endif
806-
807 const struct ieee80211_ops mt7915_ops = {
808 .tx = mt7915_tx,
809 .start = mt7915_start,
developer4721e252022-06-21 16:41:28 +0800810@@ -1502,7 +1469,4 @@ const struct ieee80211_ops mt7915_ops = {
developerf7d25b02022-04-12 16:20:16 +0800811 .sta_add_debugfs = mt7915_sta_add_debugfs,
812 #endif
813 .set_radar_background = mt7915_set_radar_background,
814-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
815- .net_fill_forward_path = mt7915_net_fill_forward_path,
816-#endif
817 };
818diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer4721e252022-06-21 16:41:28 +0800819index a16081d..46eef36 100644
developerf7d25b02022-04-12 16:20:16 +0800820--- a/mt7915/mcu.c
821+++ b/mt7915/mcu.c
developerf64861f2022-06-22 11:44:53 +0800822@@ -2365,9 +2365,6 @@ int mt7915_run_firmware(struct mt7915_dev *dev)
developerf7d25b02022-04-12 16:20:16 +0800823 if (ret)
824 return ret;
825
826- if (mtk_wed_device_active(&dev->mt76.mmio.wed))
827- mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), 0, 0, 0);
828-
829 ret = mt7915_mcu_set_mwds(dev, 1);
830 if (ret)
831 return ret;
832diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer4721e252022-06-21 16:41:28 +0800833index a84970d..1f58b2f 100644
developerf7d25b02022-04-12 16:20:16 +0800834--- a/mt7915/mmio.c
835+++ b/mt7915/mmio.c
developerbd398d52022-06-06 20:53:24 +0800836@@ -560,21 +560,15 @@ static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
developerf7d25b02022-04-12 16:20:16 +0800837 static void mt7915_irq_tasklet(struct tasklet_struct *t)
838 {
839 struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet);
840- struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
841 u32 intr, intr1, mask;
842
843- if (mtk_wed_device_active(wed)) {
844- mtk_wed_device_irq_set_mask(wed, 0);
845- intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
846- } else {
847- mt76_wr(dev, MT_INT_MASK_CSR, 0);
848- if (dev->hif2)
849- mt76_wr(dev, MT_INT1_MASK_CSR, 0);
850+ mt76_wr(dev, MT_INT_MASK_CSR, 0);
851+ if (dev->hif2)
852+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
853
854- intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
855- intr &= dev->mt76.mmio.irqmask;
856- mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
857- }
858+ intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
859+ intr &= dev->mt76.mmio.irqmask;
860+ mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
861
862 if (dev->hif2) {
863 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
developerbd398d52022-06-06 20:53:24 +0800864@@ -628,15 +622,10 @@ static void mt7915_irq_tasklet(struct tasklet_struct *t)
developerf7d25b02022-04-12 16:20:16 +0800865 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
866 {
867 struct mt7915_dev *dev = dev_instance;
868- struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
869
870- if (mtk_wed_device_active(wed)) {
871- mtk_wed_device_irq_set_mask(wed, 0);
872- } else {
873- mt76_wr(dev, MT_INT_MASK_CSR, 0);
874- if (dev->hif2)
875- mt76_wr(dev, MT_INT1_MASK_CSR, 0);
876- }
877+ mt76_wr(dev, MT_INT_MASK_CSR, 0);
878+ if (dev->hif2)
879+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
880
881 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
882 return IRQ_NONE;
883diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer4721e252022-06-21 16:41:28 +0800884index 6235014..ca95948 100644
developerf7d25b02022-04-12 16:20:16 +0800885--- a/mt7915/mt7915.h
886+++ b/mt7915/mt7915.h
developer4721e252022-06-21 16:41:28 +0800887@@ -527,8 +527,6 @@ struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
developerf7d25b02022-04-12 16:20:16 +0800888 void mt7915_wfsys_reset(struct mt7915_dev *dev);
889 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
890 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
891-u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
892-
893 int mt7915_register_device(struct mt7915_dev *dev);
894 void mt7915_unregister_device(struct mt7915_dev *dev);
895 int mt7915_eeprom_init(struct mt7915_dev *dev);
896diff --git a/mt7915/pci.c b/mt7915/pci.c
developer4721e252022-06-21 16:41:28 +0800897index d74f609..7cea49f 100644
developerf7d25b02022-04-12 16:20:16 +0800898--- a/mt7915/pci.c
899+++ b/mt7915/pci.c
900@@ -12,9 +12,6 @@
901 #include "mac.h"
902 #include "../trace.h"
903
904-static bool wed_enable = false;
905-module_param(wed_enable, bool, 0644);
906-
907 static LIST_HEAD(hif_list);
908 static DEFINE_SPINLOCK(hif_lock);
909 static u32 hif_idx;
910@@ -95,79 +92,12 @@ static int mt7915_pci_hif2_probe(struct pci_dev *pdev)
911 return 0;
912 }
913
914-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
915-static int mt7915_wed_offload_enable(struct mtk_wed_device *wed)
916-{
917- struct mt7915_dev *dev;
918- int ret;
919-
920- dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
921-
922- spin_lock_bh(&dev->mt76.token_lock);
923- dev->mt76.token_size = wed->wlan.token_start;
924- spin_unlock_bh(&dev->mt76.token_lock);
925-
926- ret = wait_event_timeout(dev->mt76.tx_wait,
927- !dev->mt76.wed_token_count, HZ);
928- if (!ret)
929- return -EAGAIN;
930-
931- return 0;
932-}
933-
934-static void mt7915_wed_offload_disable(struct mtk_wed_device *wed)
935-{
936- struct mt7915_dev *dev;
937-
938- dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
939-
940- spin_lock_bh(&dev->mt76.token_lock);
941- dev->mt76.token_size = MT7915_TOKEN_SIZE;
942- spin_unlock_bh(&dev->mt76.token_lock);
943-}
944-#endif
945-
946-static int
947-mt7915_pci_wed_init(struct mt7915_dev *dev, struct pci_dev *pdev, int *irq)
948-{
949-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
950- struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
951- int ret;
952-
953- if (!wed_enable)
954- return 0;
955-
956- wed->wlan.pci_dev = pdev;
957- wed->wlan.wpdma_phys = pci_resource_start(pdev, 0) +
958- MT_WFDMA_EXT_CSR_BASE;
959- wed->wlan.nbuf = 4096;
960- wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
961- wed->wlan.init_buf = mt7915_wed_init_buf;
962- wed->wlan.offload_enable = mt7915_wed_offload_enable;
963- wed->wlan.offload_disable = mt7915_wed_offload_disable;
964-
965- if (mtk_wed_device_attach(wed) != 0)
966- return 0;
967-
968- *irq = wed->irq;
969- dev->mt76.dma_dev = wed->dev;
970-
971- ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
972- if (ret)
973- return ret;
974-
975- return 1;
976-#else
977- return 0;
978-#endif
979-}
980-
981 static int mt7915_pci_probe(struct pci_dev *pdev,
982 const struct pci_device_id *id)
983 {
984- struct mt7915_hif *hif2 = NULL;
985 struct mt7915_dev *dev;
986 struct mt76_dev *mdev;
987+ struct mt7915_hif *hif2;
988 int irq;
989 int ret;
990
991@@ -199,24 +129,15 @@ static int mt7915_pci_probe(struct pci_dev *pdev,
992 mt7915_wfsys_reset(dev);
993 hif2 = mt7915_pci_init_hif2(pdev);
994
995- ret = mt7915_pci_wed_init(dev, pdev, &irq);
996+ ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
997 if (ret < 0)
998- goto free_wed_or_irq_vector;
999-
1000- if (!ret) {
1001- hif2 = mt7915_pci_init_hif2(pdev);
1002-
1003- ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1004- if (ret < 0)
1005- goto free_device;
1006-
1007- irq = pdev->irq;
1008- }
1009+ goto free_device;
1010
1011+ irq = pdev->irq;
1012 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler,
1013 IRQF_SHARED, KBUILD_MODNAME, dev);
1014 if (ret)
1015- goto free_wed_or_irq_vector;
1016+ goto free_irq_vector;
1017
developerbd398d52022-06-06 20:53:24 +08001018 /* master switch of PCIe tnterrupt enable */
1019 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
1020@@ -251,11 +172,8 @@ free_hif2:
developerf7d25b02022-04-12 16:20:16 +08001021 if (dev->hif2)
1022 put_device(dev->hif2->dev);
1023 devm_free_irq(mdev->dev, irq, dev);
1024-free_wed_or_irq_vector:
1025- if (mtk_wed_device_active(&mdev->mmio.wed))
1026- mtk_wed_device_detach(&mdev->mmio.wed);
1027- else
1028- pci_free_irq_vectors(pdev);
1029+free_irq_vector:
1030+ pci_free_irq_vectors(pdev);
1031 free_device:
1032 mt76_free_device(&dev->mt76);
1033
1034diff --git a/mt7915/regs.h b/mt7915/regs.h
developer4721e252022-06-21 16:41:28 +08001035index 444440e..1e7fbce 100644
developerf7d25b02022-04-12 16:20:16 +08001036--- a/mt7915/regs.h
1037+++ b/mt7915/regs.h
developerbd398d52022-06-06 20:53:24 +08001038@@ -603,31 +603,18 @@ enum offs_rev {
developerf7d25b02022-04-12 16:20:16 +08001039
1040 /* WFDMA CSR */
1041 #define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR)
1042-#define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000
1043 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
1044-#define MT_WFDMA_EXT_CSR_PHYS(ofs) (MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs))
1045
1046-#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30)
1047+#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)
1048 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
1049-#define MT_WFDMA_HOST_CONFIG_WED BIT(1)
1050
1051-#define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34)
1052-#define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0)
1053-#define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8)
1054-#define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16)
1055-
1056-#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44)
1057+#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
1058 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
1059
1060 #define MT_PCIE_RECOG_ID 0xd7090
1061 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
1062 #define MT_PCIE_RECOG_ID_SEM BIT(31)
1063
1064-#define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204)
1065-
1066-#define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300)
1067-#define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400)
1068-
1069 /* WFDMA0 PCIE1 */
1070 #define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR)
1071 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
1072diff --git a/mt7921/dma.c b/mt7921/dma.c
developer4721e252022-06-21 16:41:28 +08001073index 2939cf9..ca7e20f 100644
developerf7d25b02022-04-12 16:20:16 +08001074--- a/mt7921/dma.c
1075+++ b/mt7921/dma.c
1076@@ -9,7 +9,7 @@ static int mt7921_init_tx_queues(struct mt7921_phy *phy, int idx, int n_desc)
1077 {
1078 int i, err;
1079
1080- err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE, 0);
1081+ err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE);
1082 if (err < 0)
1083 return err;
1084
1085diff --git a/tx.c b/tx.c
developer4721e252022-06-21 16:41:28 +08001086index 0457c3e..656b709 100644
developerf7d25b02022-04-12 16:20:16 +08001087--- a/tx.c
1088+++ b/tx.c
1089@@ -725,12 +725,6 @@ int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
1090 if (token >= 0)
1091 dev->token_count++;
1092
1093-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1094- if (mtk_wed_device_active(&dev->mmio.wed) &&
1095- token >= dev->mmio.wed.wlan.token_start)
1096- dev->wed_token_count++;
1097-#endif
1098-
1099 if (dev->token_count >= dev->token_size - MT76_TOKEN_FREE_THR)
1100 __mt76_set_tx_blocked(dev, true);
1101
1102@@ -748,17 +742,9 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
1103 spin_lock_bh(&dev->token_lock);
1104
1105 txwi = idr_remove(&dev->token, token);
1106- if (txwi) {
1107+ if (txwi)
1108 dev->token_count--;
1109
1110-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1111- if (mtk_wed_device_active(&dev->mmio.wed) &&
1112- token >= dev->mmio.wed.wlan.token_start &&
1113- --dev->wed_token_count == 0)
1114- wake_up(&dev->tx_wait);
1115-#endif
1116- }
1117-
1118 if (dev->token_count < dev->token_size - MT76_TOKEN_FREE_THR &&
1119 dev->phy.q_tx[0]->blocked)
1120 *wake = true;
1121--
developer4721e252022-06-21 16:41:28 +080011222.18.0
developerf7d25b02022-04-12 16:20:16 +08001123