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developer7e2761e2023-10-12 08:11:13 +08001From 531d586b936634fad23651d18d2bbc832692c520 Mon Sep 17 00:00:00 2001
developerc2cfe0f2023-09-22 04:11:09 +08002From: "sujuan.chen" <sujuan.chen@mediatek.com>
3Date: Fri, 11 Aug 2023 18:26:39 +0800
developer7e2761e2023-10-12 08:11:13 +08004Subject: [PATCH 74/98] wifi: mt76: mt7996: add rro timeout setting
developerc2cfe0f2023-09-22 04:11:09 +08005
6Signed-off-by: sujuan.chen <sujuan.chen@mediatek.com>
7---
8 mt7996/init.c | 5 +++++
9 mt7996/mcu.c | 11 ++++++++++-
10 mt7996/mt7996.h | 2 +-
11 mt7996/regs.h | 2 ++
12 4 files changed, 18 insertions(+), 2 deletions(-)
13
14diff --git a/mt7996/init.c b/mt7996/init.c
developer7e2761e2023-10-12 08:11:13 +080015index 1ece390..51649dd 100644
developerc2cfe0f2023-09-22 04:11:09 +080016--- a/mt7996/init.c
17+++ b/mt7996/init.c
developer7e2761e2023-10-12 08:11:13 +080018@@ -506,6 +506,11 @@ void mt7996_mac_init(struct mt7996_dev *dev)
developerc2cfe0f2023-09-22 04:11:09 +080019 /* rro module init */
20 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
developer7e2761e2023-10-12 08:11:13 +080021 if (dev->has_rro) {
developerc2cfe0f2023-09-22 04:11:09 +080022+ u16 timeout;
23+
24+ timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_VER1 ? 512 : 128;
25+
26+ mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout);
27 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1);
28 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0);
29 } else {
30diff --git a/mt7996/mcu.c b/mt7996/mcu.c
developer7e2761e2023-10-12 08:11:13 +080031index ce38a5e..bebd020 100644
developerc2cfe0f2023-09-22 04:11:09 +080032--- a/mt7996/mcu.c
33+++ b/mt7996/mcu.c
34@@ -4626,7 +4626,7 @@ int mt7996_mcu_trigger_assert(struct mt7996_dev *dev)
35 &req, sizeof(req), false);
36 }
37
38-int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val)
39+int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val)
40 {
41 struct {
42 u8 __rsv1[4];
43@@ -4648,6 +4648,11 @@ int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val)
44 u8 path;
45 u8 __rsv2[3];
46 } __packed txfree_path;
47+ struct {
48+ u16 flush_one;
49+ u16 flush_all;
50+ u8 __rsv2[4];
51+ } __packed timeout;
52 };
53 } __packed req = {
54 .tag = cpu_to_le16(tag),
55@@ -4664,6 +4669,10 @@ int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val)
56 case UNI_RRO_SET_TXFREE_PATH:
57 req.txfree_path.path = val;
58 break;
59+ case UNI_RRO_SET_FLUSH_TIMEOUT:
60+ req.timeout.flush_one = val;
61+ req.timeout.flush_all = val * 2;
62+ break;
63 default:
64 return -EINVAL;
65 }
66diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developer7e2761e2023-10-12 08:11:13 +080067index af67c59..06e00f4 100644
developerc2cfe0f2023-09-22 04:11:09 +080068--- a/mt7996/mt7996.h
69+++ b/mt7996/mt7996.h
developer7e2761e2023-10-12 08:11:13 +080070@@ -676,7 +676,7 @@ int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,
developerc2cfe0f2023-09-22 04:11:09 +080071 u16 rate_idx, bool beacon);
72 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
73 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
74-int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val);
75+int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
developer7e2761e2023-10-12 08:11:13 +080076 int mt7996_mcu_reset_rro_sessions(struct mt7996_dev *dev, u16 seid);
developerc2cfe0f2023-09-22 04:11:09 +080077 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
developer7e2761e2023-10-12 08:11:13 +080078 int mt7996_mcu_red_config(struct mt7996_dev *dev, bool enable);
developerc2cfe0f2023-09-22 04:11:09 +080079diff --git a/mt7996/regs.h b/mt7996/regs.h
developer7e2761e2023-10-12 08:11:13 +080080index a0b5270..77a2f9d 100644
developerc2cfe0f2023-09-22 04:11:09 +080081--- a/mt7996/regs.h
82+++ b/mt7996/regs.h
developer7e2761e2023-10-12 08:11:13 +080083@@ -667,6 +667,8 @@ enum offs_rev {
84 #define MT_PAD_GPIO_ADIE_NUM_7992 BIT(15)
developerc2cfe0f2023-09-22 04:11:09 +080085
86 #define MT_HW_REV 0x70010204
87+#define MT_HW_VER1 0x8a00
88+
89 #define MT_WF_SUBSYS_RST 0x70028600
90
91 /* PCIE MAC */
92--
developer7e2761e2023-10-12 08:11:13 +0800932.18.0
developerc2cfe0f2023-09-22 04:11:09 +080094