blob: 2ba1f4ef1937299387443aaaff68bad648868a04 [file] [log] [blame]
developer7e2761e2023-10-12 08:11:13 +08001From 487a6e92fb6ce81d043b5a7632133379b8bcfbcb Mon Sep 17 00:00:00 2001
developer064da3c2023-06-13 15:57:26 +08002From: mtk27745 <rex.lu@mediatek.com>
3Date: Tue, 23 May 2023 12:06:29 +0800
developer7e2761e2023-10-12 08:11:13 +08004Subject: [PATCH 71/98] wifi: mt76: add SER support for wed3.0
developer064da3c2023-06-13 15:57:26 +08005
6Change-Id: I2711b9dc336fca9a1ae32a8fbf27810a7e27b1e3
7---
developer7e2761e2023-10-12 08:11:13 +08008 dma.c | 4 +++-
developerc2cfe0f2023-09-22 04:11:09 +08009 mt7996/dma.c | 42 +++++++++++++++++++++++++++++++++++++++---
developer7e2761e2023-10-12 08:11:13 +080010 mt7996/mac.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++-
11 mt7996/mmio.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
12 4 files changed, 136 insertions(+), 5 deletions(-)
developer064da3c2023-06-13 15:57:26 +080013
14diff --git a/dma.c b/dma.c
developer7e2761e2023-10-12 08:11:13 +080015index f48ec57..141a97b 100644
developer064da3c2023-06-13 15:57:26 +080016--- a/dma.c
17+++ b/dma.c
developer7e2761e2023-10-12 08:11:13 +080018@@ -898,7 +898,9 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer064da3c2023-06-13 15:57:26 +080019
20 /* reset WED rx queues */
21 mt76_dma_wed_setup(dev, q, true);
developer7e2761e2023-10-12 08:11:13 +080022- if (!mt76_queue_is_wed_tx_free(q)) {
23+ if (!mt76_queue_is_wed_tx_free(q) &&
24+ !(mt76_queue_is_wed_rro(q) &&
developer064da3c2023-06-13 15:57:26 +080025+ mtk_wed_device_active(&dev->mmio.wed))) {
26 mt76_dma_sync_idx(dev, q);
27 mt76_dma_rx_fill(dev, q);
28 }
29diff --git a/mt7996/dma.c b/mt7996/dma.c
developer7e2761e2023-10-12 08:11:13 +080030index 2397fe5..b2c7ae6 100644
developer064da3c2023-06-13 15:57:26 +080031--- a/mt7996/dma.c
32+++ b/mt7996/dma.c
developer7e2761e2023-10-12 08:11:13 +080033@@ -615,11 +615,35 @@ int mt7996_dma_init(struct mt7996_dev *dev)
developer064da3c2023-06-13 15:57:26 +080034 return 0;
35 }
36
37+static void mt7996_dma_wed_reset(struct mt7996_dev *dev)
38+{
39+ struct mt76_dev *mdev = &dev->mt76;
40+
41+ if (!test_bit(MT76_STATE_WED_RESET, &dev->mphy.state))
42+ return;
43+
44+ complete(&mdev->mmio.wed_reset);
45+
46+ if (!wait_for_completion_timeout(&dev->mt76.mmio.wed_reset_complete,
47+ 3 * HZ))
48+ dev_err(dev->mt76.dev, "wed reset complete timeout\n");
49+}
50+
51+static void
52+mt7996_dma_reset_tx_queue(struct mt7996_dev *dev, struct mt76_queue *q)
53+{
developer7e2761e2023-10-12 08:11:13 +080054+ mt76_queue_reset(dev, q);
developer064da3c2023-06-13 15:57:26 +080055+ if (mtk_wed_device_active(&dev->mt76.mmio.wed))
56+ mt76_dma_wed_setup(&dev->mt76, q, true);
57+}
58+
59 void mt7996_dma_reset(struct mt7996_dev *dev, bool force)
60 {
61 struct mt76_phy *phy2 = dev->mt76.phys[MT_BAND1];
62 struct mt76_phy *phy3 = dev->mt76.phys[MT_BAND2];
63 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
64+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
developer7e2761e2023-10-12 08:11:13 +080065+ struct mtk_wed_device *wed_hif2 = &dev->mt76.mmio.wed_hif2;
developer064da3c2023-06-13 15:57:26 +080066 int i;
67
68 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
developer7e2761e2023-10-12 08:11:13 +080069@@ -653,21 +677,33 @@ void mt7996_dma_reset(struct mt7996_dev *dev, bool force)
developer064da3c2023-06-13 15:57:26 +080070 if (force)
71 mt7996_wfsys_reset(dev);
72
developer7e2761e2023-10-12 08:11:13 +080073+ if (dev->hif2 && mtk_wed_device_active(wed_hif2))
74+ mtk_wed_device_dma_reset(wed_hif2);
developer064da3c2023-06-13 15:57:26 +080075+
76+ if (mtk_wed_device_active(wed))
77+ mtk_wed_device_dma_reset(wed);
78+
79 mt7996_dma_disable(dev, force);
80+ mt7996_dma_wed_reset(dev);
81
82 /* reset hw queues */
83 for (i = 0; i < __MT_TXQ_MAX; i++) {
developer7e2761e2023-10-12 08:11:13 +080084- mt76_queue_reset(dev, dev->mphy.q_tx[i]);
developer064da3c2023-06-13 15:57:26 +080085+ mt7996_dma_reset_tx_queue(dev, dev->mphy.q_tx[i]);
86 if (phy2)
developer7e2761e2023-10-12 08:11:13 +080087- mt76_queue_reset(dev, phy2->q_tx[i]);
developer064da3c2023-06-13 15:57:26 +080088+ mt7996_dma_reset_tx_queue(dev, phy2->q_tx[i]);
89 if (phy3)
developer7e2761e2023-10-12 08:11:13 +080090- mt76_queue_reset(dev, phy3->q_tx[i]);
developer064da3c2023-06-13 15:57:26 +080091+ mt7996_dma_reset_tx_queue(dev, phy3->q_tx[i]);
92 }
93
94 for (i = 0; i < __MT_MCUQ_MAX; i++)
developer7e2761e2023-10-12 08:11:13 +080095 mt76_queue_reset(dev, dev->mt76.q_mcu[i]);
developer064da3c2023-06-13 15:57:26 +080096
97 mt76_for_each_q_rx(&dev->mt76, i) {
98+ if (mtk_wed_device_active(wed) &&
developer7e2761e2023-10-12 08:11:13 +080099+ (mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]) ||
100+ mt76_queue_is_wed_tx_free(&dev->mt76.q_rx[i])))
developer064da3c2023-06-13 15:57:26 +0800101+ continue;
102+
developer7e2761e2023-10-12 08:11:13 +0800103 mt76_queue_reset(dev, &dev->mt76.q_rx[i]);
developer064da3c2023-06-13 15:57:26 +0800104 }
105
106diff --git a/mt7996/mac.c b/mt7996/mac.c
developer7e2761e2023-10-12 08:11:13 +0800107index 60ca23b..22cff71 100644
developer064da3c2023-06-13 15:57:26 +0800108--- a/mt7996/mac.c
109+++ b/mt7996/mac.c
developer7e2761e2023-10-12 08:11:13 +0800110@@ -1762,6 +1762,10 @@ mt7996_mac_restart(struct mt7996_dev *dev)
developer064da3c2023-06-13 15:57:26 +0800111 /* disable all tx/rx napi */
112 mt76_worker_disable(&dev->mt76.tx_worker);
113 mt76_for_each_q_rx(mdev, i) {
114+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
developer7e2761e2023-10-12 08:11:13 +0800115+ mt76_queue_is_wed_rro(&mdev->q_rx[i]))
developer064da3c2023-06-13 15:57:26 +0800116+ continue;
117+
118 if (mdev->q_rx[i].ndesc)
119 napi_disable(&dev->mt76.napi[i]);
120 }
developer7e2761e2023-10-12 08:11:13 +0800121@@ -1775,6 +1779,10 @@ mt7996_mac_restart(struct mt7996_dev *dev)
developer064da3c2023-06-13 15:57:26 +0800122
123 local_bh_disable();
124 mt76_for_each_q_rx(mdev, i) {
125+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
developer7e2761e2023-10-12 08:11:13 +0800126+ mt76_queue_is_wed_rro(&mdev->q_rx[i]))
developer064da3c2023-06-13 15:57:26 +0800127+ continue;
128+
129 if (mdev->q_rx[i].ndesc) {
130 napi_enable(&dev->mt76.napi[i]);
131 napi_schedule(&dev->mt76.napi[i]);
developer7e2761e2023-10-12 08:11:13 +0800132@@ -1949,6 +1957,13 @@ void mt7996_mac_reset_work(struct work_struct *work)
developer064da3c2023-06-13 15:57:26 +0800133
134 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.",
135 wiphy_name(dev->mt76.hw->wiphy));
136+
developer7e2761e2023-10-12 08:11:13 +0800137+ if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2))
138+ mtk_wed_device_stop(&dev->mt76.mmio.wed_hif2);
developer064da3c2023-06-13 15:57:26 +0800139+
140+ if (mtk_wed_device_active(&dev->mt76.mmio.wed))
141+ mtk_wed_device_stop(&dev->mt76.mmio.wed);
142+
143 ieee80211_stop_queues(mt76_hw(dev));
144 if (phy2)
145 ieee80211_stop_queues(phy2->mt76->hw);
developer7e2761e2023-10-12 08:11:13 +0800146@@ -1972,8 +1987,13 @@ void mt7996_mac_reset_work(struct work_struct *work)
developer064da3c2023-06-13 15:57:26 +0800147 cancel_delayed_work_sync(&phy3->mt76->mac_work);
148 }
149 mt76_worker_disable(&dev->mt76.tx_worker);
150- mt76_for_each_q_rx(&dev->mt76, i)
151+ mt76_for_each_q_rx(&dev->mt76, i) {
152+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
developer7e2761e2023-10-12 08:11:13 +0800153+ mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]))
developer064da3c2023-06-13 15:57:26 +0800154+ continue;
155+
156 napi_disable(&dev->mt76.napi[i]);
157+ }
158 napi_disable(&dev->mt76.tx_napi);
159
160 mutex_lock(&dev->mt76.mutex);
developer7e2761e2023-10-12 08:11:13 +0800161@@ -1996,6 +2016,27 @@ void mt7996_mac_reset_work(struct work_struct *work)
developerc2cfe0f2023-09-22 04:11:09 +0800162 /* enable DMA Tx/Tx and interrupt */
163 mt7996_dma_start(dev, false, false);
developer064da3c2023-06-13 15:57:26 +0800164
165+
166+ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
167+ u32 wed_irq_mask = dev->mt76.mmio.irqmask |
168+ MT_INT_RRO_RX_DONE |
169+ MT_INT_TX_DONE_BAND2;
170+
171+ if (mtk_wed_get_rx_capa(&dev->mt76.mmio.wed))
172+ wed_irq_mask &= ~MT_INT_RX_DONE_RRO_IND;
173+
174+ mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
175+
176+ mtk_wed_device_start_hwrro(&dev->mt76.mmio.wed, wed_irq_mask, true);
177+ mt7996_irq_enable(dev, wed_irq_mask);
178+ mt7996_irq_disable(dev, 0);
179+ }
180+
developer7e2761e2023-10-12 08:11:13 +0800181+ if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) {
182+ mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TRX_DONE_EXT);
183+ mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, MT_INT_TRX_DONE_EXT);
developer064da3c2023-06-13 15:57:26 +0800184+ }
185+
186 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
187 clear_bit(MT76_RESET, &dev->mphy.state);
188 if (phy2)
developer7e2761e2023-10-12 08:11:13 +0800189@@ -2005,6 +2046,10 @@ void mt7996_mac_reset_work(struct work_struct *work)
developer064da3c2023-06-13 15:57:26 +0800190
191 local_bh_disable();
192 mt76_for_each_q_rx(&dev->mt76, i) {
193+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
developer7e2761e2023-10-12 08:11:13 +0800194+ mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]))
developer064da3c2023-06-13 15:57:26 +0800195+ continue;
196+
197 napi_enable(&dev->mt76.napi[i]);
198 napi_schedule(&dev->mt76.napi[i]);
199 }
200diff --git a/mt7996/mmio.c b/mt7996/mmio.c
developer7e2761e2023-10-12 08:11:13 +0800201index 2e395d1..631d905 100644
developer064da3c2023-06-13 15:57:26 +0800202--- a/mt7996/mmio.c
203+++ b/mt7996/mmio.c
204@@ -6,9 +6,11 @@
205 #include <linux/kernel.h>
206 #include <linux/module.h>
207 #include <linux/pci.h>
208+#include <linux/rtnetlink.h>
209
210 #include "mt7996.h"
211 #include "mac.h"
212+#include "mcu.h"
213 #include "../trace.h"
214 #include "../dma.h"
215
developer7e2761e2023-10-12 08:11:13 +0800216@@ -271,6 +273,45 @@ static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
217 return val;
developer064da3c2023-06-13 15:57:26 +0800218 }
developer7e2761e2023-10-12 08:11:13 +0800219
220+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
developer064da3c2023-06-13 15:57:26 +0800221+static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed)
222+{
223+ struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed);
224+ struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
225+ struct mt76_phy *mphy = &dev->mphy;
226+ int ret;
227+
228+ ASSERT_RTNL();
229+
230+ if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
231+ return -EBUSY;
232+
233+ ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_L1,
234+ mphy->band_idx);
235+ if (ret)
236+ goto out;
237+
238+ rtnl_unlock();
239+ if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) {
240+ dev_err(mdev->dev, "wed reset timeout\n");
241+ ret = -ETIMEDOUT;
242+ }
243+ rtnl_lock();
244+out:
245+ clear_bit(MT76_STATE_WED_RESET, &mphy->state);
246+
247+ return ret;
248+}
249+
250+static void mt7996_mmio_wed_reset_complete(struct mtk_wed_device *wed)
251+{
252+ struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);
253+
254+ complete(&dev->mmio.wed_reset_complete);
255+}
256+
developer7e2761e2023-10-12 08:11:13 +0800257+#endif
258+
developer064da3c2023-06-13 15:57:26 +0800259 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
developer7e2761e2023-10-12 08:11:13 +0800260 bool hif2, int *irq)
261 {
262@@ -387,6 +428,13 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
263 wed->wlan.release_rx_buf = mt76_mmio_wed_release_rx_buf;
264 wed->wlan.offload_enable = mt76_mmio_wed_offload_enable;
265 wed->wlan.offload_disable = mt76_mmio_wed_offload_disable;
developer064da3c2023-06-13 15:57:26 +0800266+ if (hif2) {
267+ wed->wlan.reset = NULL;
268+ wed->wlan.reset_complete = NULL;
269+ } else {
270+ wed->wlan.reset = mt7996_mmio_wed_reset;
271+ wed->wlan.reset_complete = mt7996_mmio_wed_reset_complete;
272+ }
developer064da3c2023-06-13 15:57:26 +0800273
274 if (mtk_wed_device_attach(wed))
275 return 0;
276--
developer7e2761e2023-10-12 08:11:13 +08002772.18.0
developer064da3c2023-06-13 15:57:26 +0800278