| developer | 7e2761e | 2023-10-12 08:11:13 +0800 | [diff] [blame] | 1 | From 161fde22deceee4e676f62b9d3b0366ffe52dc07 Mon Sep 17 00:00:00 2001 |
| 2 | From: "sujuan.chen" <sujuan.chen@mediatek.com> |
| 3 | Date: Fri, 6 Oct 2023 14:01:41 +0800 |
| 4 | Subject: [PATCH 69/98] wifi: mt76 : wed : change pcie0 R5 to pcie1 to get 6G |
| 5 | ICS |
| 6 | |
| 7 | --- |
| 8 | mt7996/dma.c | 4 ++++ |
| 9 | mt7996/init.c | 6 ++---- |
| 10 | mt7996/mmio.c | 5 ++++- |
| 11 | mt7996/regs.h | 6 ++++++ |
| 12 | 4 files changed, 16 insertions(+), 5 deletions(-) |
| 13 | |
| 14 | diff --git a/mt7996/dma.c b/mt7996/dma.c |
| 15 | index 23f6f16..2397fe5 100644 |
| 16 | --- a/mt7996/dma.c |
| 17 | +++ b/mt7996/dma.c |
| 18 | @@ -519,6 +519,10 @@ int mt7996_dma_init(struct mt7996_dev *dev) |
| 19 | if (mt7996_band_valid(dev, MT_BAND2)) { |
| 20 | /* rx data queue for band2 */ |
| 21 | rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs; |
| 22 | + if (mtk_wed_device_active(wed_hif2) && mtk_wed_get_rx_capa(wed_hif2)) { |
| 23 | + dev->mt76.q_rx[MT_RXQ_BAND2].flags = MT_WED_Q_RX(0); |
| 24 | + dev->mt76.q_rx[MT_RXQ_BAND2].wed = wed_hif2; |
| 25 | + } |
| 26 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2], |
| 27 | MT_RXQ_ID(MT_RXQ_BAND2), |
| 28 | MT7996_RX_RING_SIZE, |
| 29 | diff --git a/mt7996/init.c b/mt7996/init.c |
| 30 | index 1f01f24..5627605 100644 |
| 31 | --- a/mt7996/init.c |
| 32 | +++ b/mt7996/init.c |
| 33 | @@ -619,10 +619,8 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, |
| 34 | goto error; |
| 35 | |
| 36 | if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { |
| 37 | - u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; |
| 38 | - |
| 39 | - mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); |
| 40 | - mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); |
| 41 | + mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TRX_DONE_EXT); |
| 42 | + mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, MT_INT_TRX_DONE_EXT); |
| 43 | } |
| 44 | |
| 45 | return 0; |
| 46 | diff --git a/mt7996/mmio.c b/mt7996/mmio.c |
| 47 | index 2132b2e..2e395d1 100644 |
| 48 | --- a/mt7996/mmio.c |
| 49 | +++ b/mt7996/mmio.c |
| 50 | @@ -504,12 +504,15 @@ static void mt7996_irq_tasklet(struct tasklet_struct *t) |
| 51 | dev->mt76.mmio.irqmask); |
| 52 | if (intr1 & MT_INT_RX_TXFREE_EXT) |
| 53 | napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); |
| 54 | + |
| 55 | + if (intr1 & MT_INT_RX_DONE_BAND2_EXT) |
| 56 | + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]); |
| 57 | } |
| 58 | |
| 59 | if (mtk_wed_device_active(wed)) { |
| 60 | mtk_wed_device_irq_set_mask(wed, 0); |
| 61 | intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); |
| 62 | - intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT); |
| 63 | + intr |= (intr1 & ~MT_INT_TRX_DONE_EXT); |
| 64 | } else { |
| 65 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 66 | if (dev->hif2) |
| 67 | diff --git a/mt7996/regs.h b/mt7996/regs.h |
| 68 | index 38467d9..a0b5270 100644 |
| 69 | --- a/mt7996/regs.h |
| 70 | +++ b/mt7996/regs.h |
| 71 | @@ -501,6 +501,8 @@ enum offs_rev { |
| 72 | #define MT_INT_RX_TXFREE_MAIN BIT(17) |
| 73 | #define MT_INT_RX_TXFREE_TRI BIT(15) |
| 74 | #define MT_INT_MCU_CMD BIT(29) |
| 75 | + |
| 76 | +#define MT_INT_RX_DONE_BAND2_EXT BIT(23) |
| 77 | #define MT_INT_RX_TXFREE_EXT BIT(26) |
| 78 | |
| 79 | #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) |
| 80 | @@ -551,6 +553,10 @@ enum offs_rev { |
| 81 | #define MT_INT_TX_DONE_BAND1 BIT(31) |
| 82 | #define MT_INT_TX_DONE_BAND2 BIT(15) |
| 83 | |
| 84 | +#define MT_INT_TRX_DONE_EXT (MT_INT_TX_DONE_BAND2 | \ |
| 85 | + MT_INT_RX_DONE_BAND2_EXT | \ |
| 86 | + MT_INT_RX_TXFREE_EXT) |
| 87 | + |
| 88 | #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ |
| 89 | MT_INT_TX_MCU(MT_MCUQ_WM) | \ |
| 90 | MT_INT_TX_MCU(MT_MCUQ_FWDL)) |
| 91 | -- |
| 92 | 2.18.0 |
| 93 | |