| developer | 4721e25 | 2022-06-21 16:41:28 +0800 | [diff] [blame] | 1 | From 3b52f9553517631ce961a5ca808619a918ec5edc Mon Sep 17 00:00:00 2001 |
| developer | 20d6771 | 2022-03-02 14:09:32 +0800 | [diff] [blame] | 2 | From: Shayne Chen <shayne.chen@mediatek.com> |
| 3 | Date: Wed, 19 Jan 2022 15:51:01 +0800 |
| developer | 4721e25 | 2022-06-21 16:41:28 +0800 | [diff] [blame] | 4 | Subject: [PATCH 04/12] mt76: mt7915: fix tx descriptor |
| developer | 20d6771 | 2022-03-02 14:09:32 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
| developer | 4721e25 | 2022-06-21 16:41:28 +0800 | [diff] [blame] | 7 | mt7915/mac.c | 1 + |
| developer | 20d6771 | 2022-03-02 14:09:32 +0800 | [diff] [blame] | 8 | 1 file changed, 1 insertion(+) |
| 9 | |
| 10 | diff --git a/mt7915/mac.c b/mt7915/mac.c |
| developer | 4721e25 | 2022-06-21 16:41:28 +0800 | [diff] [blame] | 11 | index b280b0e..9092b40 100644 |
| developer | 20d6771 | 2022-03-02 14:09:32 +0800 | [diff] [blame] | 12 | --- a/mt7915/mac.c |
| 13 | +++ b/mt7915/mac.c |
| developer | f64861f | 2022-06-22 11:44:53 +0800 | [diff] [blame] | 14 | @@ -653,6 +653,7 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, |
| developer | 20d6771 | 2022-03-02 14:09:32 +0800 | [diff] [blame] | 15 | if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) |
| 16 | val |= MT_TXD6_LDPC; |
| 17 | |
| 18 | + txwi[1] &= ~cpu_to_le32(MT_TXD1_VTA); |
| 19 | txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); |
| 20 | txwi[6] |= cpu_to_le32(val); |
| 21 | txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, |
| 22 | -- |
| developer | 4721e25 | 2022-06-21 16:41:28 +0800 | [diff] [blame] | 23 | 2.18.0 |
| developer | 20d6771 | 2022-03-02 14:09:32 +0800 | [diff] [blame] | 24 | |