blob: 9ef5fcccc8b1e2e5b8bb740017356184a443977e [file] [log] [blame]
developerb11a5392022-03-31 00:34:47 +08001// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/etherdevice.h>
5#include <linux/hwmon.h>
6#include <linux/hwmon-sysfs.h>
7#include <linux/thermal.h>
developer7800b8d2022-06-23 22:15:56 +08008#include "besra.h"
developerb11a5392022-03-31 00:34:47 +08009#include "mac.h"
10#include "mcu.h"
11#include "eeprom.h"
12
13static const struct ieee80211_iface_limit if_limits[] = {
14 {
15 .max = 1,
16 .types = BIT(NL80211_IFTYPE_ADHOC)
17 }, {
18 .max = 16,
19 .types = BIT(NL80211_IFTYPE_AP)
20#ifdef CONFIG_MAC80211_MESH
21 | BIT(NL80211_IFTYPE_MESH_POINT)
22#endif
23 }, {
developer7800b8d2022-06-23 22:15:56 +080024 .max = BESRA_MAX_INTERFACES,
developerb11a5392022-03-31 00:34:47 +080025 .types = BIT(NL80211_IFTYPE_STATION)
26 }
27};
28
29static const struct ieee80211_iface_combination if_comb[] = {
30 {
31 .limits = if_limits,
32 .n_limits = ARRAY_SIZE(if_limits),
developer7800b8d2022-06-23 22:15:56 +080033 .max_interfaces = BESRA_MAX_INTERFACES,
developerb11a5392022-03-31 00:34:47 +080034 .num_different_channels = 1,
35 .beacon_int_infra_match = true,
36 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
37 BIT(NL80211_CHAN_WIDTH_20) |
38 BIT(NL80211_CHAN_WIDTH_40) |
39 BIT(NL80211_CHAN_WIDTH_80) |
40 BIT(NL80211_CHAN_WIDTH_160) |
41 BIT(NL80211_CHAN_WIDTH_80P80),
42 }
43};
44
developer7800b8d2022-06-23 22:15:56 +080045static ssize_t besra_thermal_temp_show(struct device *dev,
developerb11a5392022-03-31 00:34:47 +080046 struct device_attribute *attr,
47 char *buf)
48{
developer7800b8d2022-06-23 22:15:56 +080049 struct besra_phy *phy = dev_get_drvdata(dev);
developerb11a5392022-03-31 00:34:47 +080050 int i = to_sensor_dev_attr(attr)->index;
51 int temperature;
52
developer66cd2092022-05-10 15:43:01 +080053 switch (i) {
54 case 0:
developer7800b8d2022-06-23 22:15:56 +080055 temperature = besra_mcu_get_temperature(phy);
developer66cd2092022-05-10 15:43:01 +080056 if (temperature < 0)
57 return temperature;
58 /* display in millidegree celcius */
59 return sprintf(buf, "%u\n", temperature * 1000);
60 case 1:
61 case 2:
62 return sprintf(buf, "%u\n",
63 phy->throttle_temp[i - 1] * 1000);
64 case 3:
65 return sprintf(buf, "%hhu\n", phy->throttle_state);
66 default:
67 return -EINVAL;
68 }
developerb11a5392022-03-31 00:34:47 +080069}
70
developer7800b8d2022-06-23 22:15:56 +080071static ssize_t besra_thermal_temp_store(struct device *dev,
developerb11a5392022-03-31 00:34:47 +080072 struct device_attribute *attr,
73 const char *buf, size_t count)
74{
developer7800b8d2022-06-23 22:15:56 +080075 struct besra_phy *phy = dev_get_drvdata(dev);
developerb11a5392022-03-31 00:34:47 +080076 int ret, i = to_sensor_dev_attr(attr)->index;
77 long val;
78
79 ret = kstrtol(buf, 10, &val);
80 if (ret < 0)
81 return ret;
82
83 mutex_lock(&phy->dev->mt76.mutex);
84 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130);
85 phy->throttle_temp[i - 1] = val;
86 mutex_unlock(&phy->dev->mt76.mutex);
87
88 return count;
89}
90
developer7800b8d2022-06-23 22:15:56 +080091static SENSOR_DEVICE_ATTR_RO(temp1_input, besra_thermal_temp, 0);
92static SENSOR_DEVICE_ATTR_RW(temp1_crit, besra_thermal_temp, 1);
93static SENSOR_DEVICE_ATTR_RW(temp1_max, besra_thermal_temp, 2);
94static SENSOR_DEVICE_ATTR_RO(throttle1, besra_thermal_temp, 3);
developerb11a5392022-03-31 00:34:47 +080095
developer7800b8d2022-06-23 22:15:56 +080096static struct attribute *besra_hwmon_attrs[] = {
developerb11a5392022-03-31 00:34:47 +080097 &sensor_dev_attr_temp1_input.dev_attr.attr,
98 &sensor_dev_attr_temp1_crit.dev_attr.attr,
99 &sensor_dev_attr_temp1_max.dev_attr.attr,
developer66cd2092022-05-10 15:43:01 +0800100 &sensor_dev_attr_throttle1.dev_attr.attr,
developerb11a5392022-03-31 00:34:47 +0800101 NULL,
102};
developer7800b8d2022-06-23 22:15:56 +0800103ATTRIBUTE_GROUPS(besra_hwmon);
developerb11a5392022-03-31 00:34:47 +0800104
105static int
developer7800b8d2022-06-23 22:15:56 +0800106besra_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
developerb11a5392022-03-31 00:34:47 +0800107 unsigned long *state)
108{
developer7800b8d2022-06-23 22:15:56 +0800109 *state = BESRA_CDEV_THROTTLE_MAX;
developerb11a5392022-03-31 00:34:47 +0800110
111 return 0;
112}
113
114static int
developer7800b8d2022-06-23 22:15:56 +0800115besra_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
developerb11a5392022-03-31 00:34:47 +0800116 unsigned long *state)
117{
developer7800b8d2022-06-23 22:15:56 +0800118 struct besra_phy *phy = cdev->devdata;
developerb11a5392022-03-31 00:34:47 +0800119
developer66cd2092022-05-10 15:43:01 +0800120 *state = phy->cdev_state;
developerb11a5392022-03-31 00:34:47 +0800121
122 return 0;
123}
124
125static int
developer7800b8d2022-06-23 22:15:56 +0800126besra_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
developerb11a5392022-03-31 00:34:47 +0800127 unsigned long state)
128{
developer7800b8d2022-06-23 22:15:56 +0800129 struct besra_phy *phy = cdev->devdata;
130 u8 throttling = BESRA_THERMAL_THROTTLE_MAX - state;
developerb11a5392022-03-31 00:34:47 +0800131 int ret;
132
developer7800b8d2022-06-23 22:15:56 +0800133 if (state > BESRA_CDEV_THROTTLE_MAX)
developerb11a5392022-03-31 00:34:47 +0800134 return -EINVAL;
135
136 if (phy->throttle_temp[0] > phy->throttle_temp[1])
137 return 0;
138
developer66cd2092022-05-10 15:43:01 +0800139 if (state == phy->cdev_state)
developerb11a5392022-03-31 00:34:47 +0800140 return 0;
141
developer66cd2092022-05-10 15:43:01 +0800142 /*
143 * cooling_device convention: 0 = no cooling, more = more cooling
144 * mcu convention: 1 = max cooling, more = less cooling
145 */
developer7800b8d2022-06-23 22:15:56 +0800146 ret = besra_mcu_set_thermal_throttling(phy, throttling);
developerb11a5392022-03-31 00:34:47 +0800147 if (ret)
148 return ret;
149
developer66cd2092022-05-10 15:43:01 +0800150 phy->cdev_state = state;
developerb11a5392022-03-31 00:34:47 +0800151
152 return 0;
153}
154
developer7800b8d2022-06-23 22:15:56 +0800155static const struct thermal_cooling_device_ops besra_thermal_ops = {
156 .get_max_state = besra_thermal_get_max_throttle_state,
157 .get_cur_state = besra_thermal_get_cur_throttle_state,
158 .set_cur_state = besra_thermal_set_cur_throttle_state,
developerb11a5392022-03-31 00:34:47 +0800159};
160
developer7800b8d2022-06-23 22:15:56 +0800161static void besra_unregister_thermal(struct besra_phy *phy)
developerb11a5392022-03-31 00:34:47 +0800162{
163 struct wiphy *wiphy = phy->mt76->hw->wiphy;
164
165 if (!phy->cdev)
166 return;
167
168 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device");
169 thermal_cooling_device_unregister(phy->cdev);
170}
171
developer7800b8d2022-06-23 22:15:56 +0800172static int besra_thermal_init(struct besra_phy *phy)
developerb11a5392022-03-31 00:34:47 +0800173{
174 struct wiphy *wiphy = phy->mt76->hw->wiphy;
175 struct thermal_cooling_device *cdev;
176 struct device *hwmon;
177 const char *name;
178
developer7800b8d2022-06-23 22:15:56 +0800179 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "besra_%s",
developerb11a5392022-03-31 00:34:47 +0800180 wiphy_name(wiphy));
181
developer7800b8d2022-06-23 22:15:56 +0800182 cdev = thermal_cooling_device_register(name, phy, &besra_thermal_ops);
developerb11a5392022-03-31 00:34:47 +0800183 if (!IS_ERR(cdev)) {
184 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
185 "cooling_device") < 0)
186 thermal_cooling_device_unregister(cdev);
187 else
188 phy->cdev = cdev;
189 }
190
191 if (!IS_REACHABLE(CONFIG_HWMON))
192 return 0;
193
194 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
developer7800b8d2022-06-23 22:15:56 +0800195 besra_hwmon_groups);
developerb11a5392022-03-31 00:34:47 +0800196 if (IS_ERR(hwmon))
197 return PTR_ERR(hwmon);
198
199 /* initialize critical/maximum high temperature */
200 phy->throttle_temp[0] = 110;
201 phy->throttle_temp[1] = 120;
202
developer7800b8d2022-06-23 22:15:56 +0800203 return besra_mcu_set_thermal_throttling(phy,
204 BESRA_THERMAL_THROTTLE_MAX);
developerb11a5392022-03-31 00:34:47 +0800205}
206
developer7800b8d2022-06-23 22:15:56 +0800207static void besra_led_set_config(struct led_classdev *led_cdev,
developerb11a5392022-03-31 00:34:47 +0800208 u8 delay_on, u8 delay_off)
209{
developer7800b8d2022-06-23 22:15:56 +0800210 struct besra_dev *dev;
developerb11a5392022-03-31 00:34:47 +0800211 struct mt76_dev *mt76;
212 u32 val;
213
214 mt76 = container_of(led_cdev, struct mt76_dev, led_cdev);
developer7800b8d2022-06-23 22:15:56 +0800215 dev = container_of(mt76, struct besra_dev, mt76);
developerb11a5392022-03-31 00:34:47 +0800216
217 /* select TX blink mode, 2: only data frames */
218 mt76_rmw_field(dev, MT_TMAC_TCR0(0), MT_TMAC_TCR0_TX_BLINK, 2);
219
220 /* enable LED */
221 mt76_wr(dev, MT_LED_EN(0), 1);
222
223 /* set LED Tx blink on/off time */
224 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) |
225 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off);
226 mt76_wr(dev, MT_LED_TX_BLINK(0), val);
227
228 /* control LED */
229 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK;
230 if (dev->mt76.led_al)
231 val |= MT_LED_CTRL_POLARITY;
232
233 mt76_wr(dev, MT_LED_CTRL(0), val);
234 mt76_clear(dev, MT_LED_CTRL(0), MT_LED_CTRL_KICK);
235}
236
developer7800b8d2022-06-23 22:15:56 +0800237static int besra_led_set_blink(struct led_classdev *led_cdev,
developerb11a5392022-03-31 00:34:47 +0800238 unsigned long *delay_on,
239 unsigned long *delay_off)
240{
241 u16 delta_on = 0, delta_off = 0;
242
243#define HW_TICK 10
244#define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
245
246 if (*delay_on)
247 delta_on = TO_HW_TICK(*delay_on);
248 if (*delay_off)
249 delta_off = TO_HW_TICK(*delay_off);
250
developer7800b8d2022-06-23 22:15:56 +0800251 besra_led_set_config(led_cdev, delta_on, delta_off);
developerb11a5392022-03-31 00:34:47 +0800252
253 return 0;
254}
255
developer7800b8d2022-06-23 22:15:56 +0800256static void besra_led_set_brightness(struct led_classdev *led_cdev,
developerb11a5392022-03-31 00:34:47 +0800257 enum led_brightness brightness)
258{
259 if (!brightness)
developer7800b8d2022-06-23 22:15:56 +0800260 besra_led_set_config(led_cdev, 0, 0xff);
developerb11a5392022-03-31 00:34:47 +0800261 else
developer7800b8d2022-06-23 22:15:56 +0800262 besra_led_set_config(led_cdev, 0xff, 0);
developerb11a5392022-03-31 00:34:47 +0800263}
264
265static void
developer7800b8d2022-06-23 22:15:56 +0800266besra_init_txpower(struct besra_dev *dev,
developerb11a5392022-03-31 00:34:47 +0800267 struct ieee80211_supported_band *sband)
268{
269 int i, n_chains = hweight8(dev->mphy.antenna_mask);
270 int nss_delta = mt76_tx_power_nss_delta(n_chains);
developer7800b8d2022-06-23 22:15:56 +0800271 int pwr_delta = besra_eeprom_get_power_delta(dev, sband->band);
developerb11a5392022-03-31 00:34:47 +0800272 struct mt76_power_limits limits;
273
274 for (i = 0; i < sband->n_channels; i++) {
275 struct ieee80211_channel *chan = &sband->channels[i];
276 u32 target_power = 0;
277 int j;
278
279 for (j = 0; j < n_chains; j++) {
280 u32 val;
281
developer7800b8d2022-06-23 22:15:56 +0800282 val = besra_eeprom_get_target_power(dev, chan, j);
developerb11a5392022-03-31 00:34:47 +0800283 target_power = max(target_power, val);
284 }
285
286 target_power += pwr_delta;
287 target_power = mt76_get_rate_power_limits(&dev->mphy, chan,
288 &limits,
289 target_power);
290 target_power += nss_delta;
291 target_power = DIV_ROUND_UP(target_power, 2);
292 chan->max_power = min_t(int, chan->max_reg_power,
293 target_power);
294 chan->orig_mpwr = target_power;
295 }
296}
297
298static void
developer7800b8d2022-06-23 22:15:56 +0800299besra_regd_notifier(struct wiphy *wiphy,
developerb11a5392022-03-31 00:34:47 +0800300 struct regulatory_request *request)
301{
302 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
developer7800b8d2022-06-23 22:15:56 +0800303 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800304 struct mt76_phy *mphy = hw->priv;
developer7800b8d2022-06-23 22:15:56 +0800305 struct besra_phy *phy = mphy->priv;
developerb11a5392022-03-31 00:34:47 +0800306
307 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
308 dev->mt76.region = request->dfs_region;
309
310 if (dev->mt76.region == NL80211_DFS_UNSET)
developer7800b8d2022-06-23 22:15:56 +0800311 besra_mcu_rdd_background_enable(phy, NULL);
developerb11a5392022-03-31 00:34:47 +0800312
developer7800b8d2022-06-23 22:15:56 +0800313 besra_init_txpower(dev, &mphy->sband_2g.sband);
314 besra_init_txpower(dev, &mphy->sband_5g.sband);
developerb11a5392022-03-31 00:34:47 +0800315
316 mphy->dfs_state = MT_DFS_STATE_UNKNOWN;
developer7800b8d2022-06-23 22:15:56 +0800317 besra_dfs_init_radar_detector(phy);
developerb11a5392022-03-31 00:34:47 +0800318}
319
320static void
developer7800b8d2022-06-23 22:15:56 +0800321besra_init_wiphy(struct ieee80211_hw *hw)
developerb11a5392022-03-31 00:34:47 +0800322{
developer7800b8d2022-06-23 22:15:56 +0800323 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800324 struct mt76_dev *mdev = &phy->dev->mt76;
325 struct wiphy *wiphy = hw->wiphy;
326
327 hw->queues = 4;
328 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF;
329 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF;
330 hw->netdev_features = NETIF_F_RXCSUM;
331
332 hw->radiotap_timestamp.units_pos =
333 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
334
335 phy->slottime = 9;
336
developer7800b8d2022-06-23 22:15:56 +0800337 hw->sta_data_size = sizeof(struct besra_sta);
338 hw->vif_data_size = sizeof(struct besra_vif);
developerb11a5392022-03-31 00:34:47 +0800339
340 wiphy->iface_combinations = if_comb;
341 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
developer7800b8d2022-06-23 22:15:56 +0800342 wiphy->reg_notifier = besra_regd_notifier;
developerb11a5392022-03-31 00:34:47 +0800343 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
344
345 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
346 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
347 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
348 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
349 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
350 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
351
352 if (!mdev->dev->of_node ||
353 !of_property_read_bool(mdev->dev->of_node,
354 "mediatek,disable-radar-background"))
355 wiphy_ext_feature_set(wiphy,
356 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
357
358 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
359 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
360 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
361 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
362
363 hw->max_tx_fragments = 4;
364
365 if (!phy->dev->dbdc_support)
366 wiphy->txq_memory_limit = 32 << 20; /* 32 MiB */
367
368 if (phy->mt76->cap.has_2ghz)
369 phy->mt76->sband_2g.sband.ht_cap.cap |=
370 IEEE80211_HT_CAP_LDPC_CODING |
371 IEEE80211_HT_CAP_MAX_AMSDU;
372
373 if (phy->mt76->cap.has_5ghz) {
374 phy->mt76->sband_5g.sband.ht_cap.cap |=
375 IEEE80211_HT_CAP_LDPC_CODING |
376 IEEE80211_HT_CAP_MAX_AMSDU;
377
378 phy->mt76->sband_5g.sband.vht_cap.cap |=
379 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
380 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
381
382 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */
383 phy->mt76->sband_5g.sband.vht_cap.cap |=
384 IEEE80211_VHT_CAP_SHORT_GI_160 |
385 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
386 }
387
388 mt76_set_stream_caps(phy->mt76, true);
developer7800b8d2022-06-23 22:15:56 +0800389 besra_set_stream_vht_txbf_caps(phy);
390 besra_set_stream_he_caps(phy);
developerb11a5392022-03-31 00:34:47 +0800391
392 wiphy->available_antennas_rx = phy->mt76->antenna_mask;
393 wiphy->available_antennas_tx = phy->mt76->antenna_mask;
394}
395
396static void
developer7800b8d2022-06-23 22:15:56 +0800397besra_mac_init_band(struct besra_dev *dev, u8 band)
developerb11a5392022-03-31 00:34:47 +0800398{
399 u32 mask, set;
400
401 mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
402 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
403 mt76_set(dev, MT_TMAC_CTCR0(band),
404 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
405 MT_TMAC_CTCR0_INS_DDLMT_EN);
406
407 mask = MT_MDP_RCFR0_MCU_RX_MGMT |
408 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR |
409 MT_MDP_RCFR0_MCU_RX_CTL_BAR;
410 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) |
411 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) |
412 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF);
413 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set);
414
415 mask = MT_MDP_RCFR1_MCU_RX_BYPASS |
416 MT_MDP_RCFR1_RX_DROPPED_UCAST |
417 MT_MDP_RCFR1_RX_DROPPED_MCAST;
418 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) |
419 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) |
420 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF);
421 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
422
423 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
424
developer7800b8d2022-06-23 22:15:56 +0800425 /* besra: disable rx rate report by default due to hw issues */
developerb11a5392022-03-31 00:34:47 +0800426 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
427}
428
developer7800b8d2022-06-23 22:15:56 +0800429static void besra_mac_init(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +0800430{
431 int i;
432
433 /* TODO: to be checked which are necessary */
434 /* config pse qid6 wfdma port selection */
435 /* mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, */
436 /* MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); */
437
438 /* mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, 0x680); */
439
developer66cd2092022-05-10 15:43:01 +0800440 /* mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); */
441
developerb11a5392022-03-31 00:34:47 +0800442 /* enable hardware de-agg */
443 /* mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); */
444
developer7800b8d2022-06-23 22:15:56 +0800445 for (i = 0; i < BESRA_WTBL_SIZE; i++)
446 besra_mac_wtbl_update(dev, i,
developerb11a5392022-03-31 00:34:47 +0800447 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
448 /* TODO: to be checked which are necessary */
449 /* for (i = 0; i < __MT_MAX_BAND; i++) */
developer7800b8d2022-06-23 22:15:56 +0800450 /* besra_mac_init_band(dev, i); */
developerb11a5392022-03-31 00:34:47 +0800451
452 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
453 i = dev->mt76.led_pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2;
454 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
455 }
456}
457
developer7800b8d2022-06-23 22:15:56 +0800458static int besra_txbf_init(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +0800459{
460 int ret;
461
462 if (dev->dbdc_support) {
developer7800b8d2022-06-23 22:15:56 +0800463 ret = besra_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE);
developerb11a5392022-03-31 00:34:47 +0800464 if (ret)
465 return ret;
466 }
467
468 /* trigger sounding packets */
developer7800b8d2022-06-23 22:15:56 +0800469 ret = besra_mcu_set_txbf(dev, MT_BF_SOUNDING_ON);
developerb11a5392022-03-31 00:34:47 +0800470 if (ret)
471 return ret;
472
473 /* enable eBF */
developer7800b8d2022-06-23 22:15:56 +0800474 return besra_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
developerb11a5392022-03-31 00:34:47 +0800475}
476
developer7800b8d2022-06-23 22:15:56 +0800477static int besra_register_ext_phy(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +0800478{
developer7800b8d2022-06-23 22:15:56 +0800479 struct besra_phy *phy = besra_ext_phy(dev);
developerb11a5392022-03-31 00:34:47 +0800480 struct mt76_phy *mphy;
481 int ret;
482
483 if (!dev->dbdc_support)
484 return 0;
485
486 if (phy)
487 return 0;
488
developer7800b8d2022-06-23 22:15:56 +0800489 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &besra_ops, MT_BAND1);
developerb11a5392022-03-31 00:34:47 +0800490 if (!mphy)
491 return -ENOMEM;
492
493 phy = mphy->priv;
494 phy->dev = dev;
495 phy->mt76 = mphy;
496 phy->band_idx = MT_BAND1;
497 mphy->dev->phy2 = mphy;
498
developer7800b8d2022-06-23 22:15:56 +0800499 INIT_DELAYED_WORK(&mphy->mac_work, besra_mac_work);
developerb11a5392022-03-31 00:34:47 +0800500
developer7800b8d2022-06-23 22:15:56 +0800501 besra_eeprom_parse_hw_cap(dev, phy);
developerb11a5392022-03-31 00:34:47 +0800502
503 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
504 ETH_ALEN);
505 /* Make the secondary PHY MAC address local without overlapping with
506 * the usual MAC address allocation scheme on multiple virtual interfaces
507 */
508 if (!is_valid_ether_addr(mphy->macaddr)) {
509 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
510 ETH_ALEN);
511 mphy->macaddr[0] |= 2;
512 mphy->macaddr[0] ^= BIT(7);
513 }
514 mt76_eeprom_override(mphy);
515
516 /* init wiphy according to mphy and phy */
developer7800b8d2022-06-23 22:15:56 +0800517 besra_init_wiphy(mphy->hw);
518 ret = besra_init_tx_queues(phy, MT_TXQ_ID(phy->band_idx),
519 BESRA_TX_RING_SIZE,
developerb11a5392022-03-31 00:34:47 +0800520 MT_TXQ_RING_BASE(1));
521 if (ret)
522 goto error;
523
524 ret = mt76_register_phy(mphy, true, mt76_rates,
525 ARRAY_SIZE(mt76_rates));
526 if (ret)
527 goto error;
528
developer7800b8d2022-06-23 22:15:56 +0800529 ret = besra_thermal_init(phy);
developerb11a5392022-03-31 00:34:47 +0800530 if (ret)
531 goto error;
532
developer7800b8d2022-06-23 22:15:56 +0800533 ret = besra_init_debugfs(phy);
developerb11a5392022-03-31 00:34:47 +0800534 if (ret)
535 goto error;
536
537 return 0;
538
539error:
540 mphy->dev->phy2 = NULL;
541 ieee80211_free_hw(mphy->hw);
542 return ret;
543}
544
developer7800b8d2022-06-23 22:15:56 +0800545static int besra_register_tri_phy(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +0800546{
developer7800b8d2022-06-23 22:15:56 +0800547 struct besra_phy *phy = besra_tri_phy(dev);
developerb11a5392022-03-31 00:34:47 +0800548 struct mt76_phy *mphy;
549 int ret;
550
551 if (!dev->tbtc_support)
552 return 0;
553
554 if (phy)
555 return 0;
556
developer7800b8d2022-06-23 22:15:56 +0800557 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &besra_ops, MT_BAND2);
developerb11a5392022-03-31 00:34:47 +0800558 if (!mphy)
559 return -ENOMEM;
560
561 phy = mphy->priv;
562 phy->dev = dev;
563 phy->mt76 = mphy;
564 phy->band_idx = MT_BAND2;
565 mphy->dev->phy3 = mphy;
566
developer7800b8d2022-06-23 22:15:56 +0800567 INIT_DELAYED_WORK(&mphy->mac_work, besra_mac_work);
developerb11a5392022-03-31 00:34:47 +0800568
developer7800b8d2022-06-23 22:15:56 +0800569 besra_eeprom_parse_hw_cap(dev, phy);
developerb11a5392022-03-31 00:34:47 +0800570
571 /* Make the secondary PHY MAC address local without overlapping with
572 * the usual MAC address allocation scheme on multiple virtual interfaces
573 */
574 if (!is_valid_ether_addr(mphy->macaddr)) {
575 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
576 ETH_ALEN);
577 mphy->macaddr[0] |= 2;
578 mphy->macaddr[0] ^= BIT(6);
579 mphy->macaddr[0] ^= BIT(7);
580 }
581 mt76_eeprom_override(mphy);
582
583 /* init wiphy according to mphy and phy */
developer7800b8d2022-06-23 22:15:56 +0800584 besra_init_wiphy(mphy->hw);
585 ret = besra_init_tx_queues(phy, MT_TXQ_ID(phy->band_idx),
586 BESRA_TX_RING_SIZE,
developerb11a5392022-03-31 00:34:47 +0800587 MT_TXQ_RING_BASE(2));
588 if (ret)
589 goto error;
590
591 ret = mt76_register_phy(mphy, true, mt76_rates,
592 ARRAY_SIZE(mt76_rates));
593 if (ret)
594 goto error;
595
developer7800b8d2022-06-23 22:15:56 +0800596 ret = besra_thermal_init(phy);
developerb11a5392022-03-31 00:34:47 +0800597 if (ret)
598 goto error;
599
developer7800b8d2022-06-23 22:15:56 +0800600 ret = besra_init_debugfs(phy);
developerb11a5392022-03-31 00:34:47 +0800601 if (ret)
602 goto error;
603
604 return 0;
605
606error:
607 mphy->dev->phy3 = NULL;
608 ieee80211_free_hw(mphy->hw);
609 return ret;
610}
611
developer7800b8d2022-06-23 22:15:56 +0800612static void besra_init_work(struct work_struct *work)
developerb11a5392022-03-31 00:34:47 +0800613{
developer7800b8d2022-06-23 22:15:56 +0800614 struct besra_dev *dev = container_of(work, struct besra_dev,
developerb11a5392022-03-31 00:34:47 +0800615 init_work);
616
developer7800b8d2022-06-23 22:15:56 +0800617 besra_mcu_set_eeprom(dev);
618 besra_mac_init(dev);
619 besra_init_txpower(dev, &dev->mphy.sband_2g.sband);
620 besra_init_txpower(dev, &dev->mphy.sband_5g.sband);
621 besra_txbf_init(dev);
developerb11a5392022-03-31 00:34:47 +0800622}
623
developer7800b8d2022-06-23 22:15:56 +0800624void besra_wfsys_reset(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +0800625{
626 if (is_mt7902(&dev->mt76))
627 return;
628
629 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
630 msleep(20);
631
632 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
633 msleep(20);
634}
635
developer7800b8d2022-06-23 22:15:56 +0800636static bool besra_band_config(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +0800637{
638 dev->phy.band_idx = MT_BAND0;
639 dev->mphy.band_idx = MT_BAND0;
640 dev->tbtc_support = false;
641
642 if (is_mt7902(&dev->mt76)) {
643 dev->tbtc_support = true;
644 /* TODO: bellwether the band1 is unused */
645 return false;
646 }
647
648 return true;
649}
650
developer7800b8d2022-06-23 22:15:56 +0800651static int besra_init_hardware(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +0800652{
653 int ret, idx;
654
655 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
656
developer7800b8d2022-06-23 22:15:56 +0800657 INIT_WORK(&dev->init_work, besra_init_work);
developerb11a5392022-03-31 00:34:47 +0800658
developer7800b8d2022-06-23 22:15:56 +0800659 dev->dbdc_support = besra_band_config(dev);
developerb11a5392022-03-31 00:34:47 +0800660
661 /* bellwether do rom dl */
662 if (is_mt7902(&dev->mt76)) {
developer7800b8d2022-06-23 22:15:56 +0800663 ret = besra_rom_start(dev);
developerb11a5392022-03-31 00:34:47 +0800664 if (ret)
665 return ret;
666 }
667
developer7800b8d2022-06-23 22:15:56 +0800668 ret = besra_dma_init(dev);
developerb11a5392022-03-31 00:34:47 +0800669 if (ret)
670 return ret;
671
672 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
673
developer7800b8d2022-06-23 22:15:56 +0800674 ret = besra_mcu_init(dev);
developer66cd2092022-05-10 15:43:01 +0800675 if (ret)
676 return ret;
developerb11a5392022-03-31 00:34:47 +0800677
developer7800b8d2022-06-23 22:15:56 +0800678 ret = besra_eeprom_init(dev);
developerb11a5392022-03-31 00:34:47 +0800679 if (ret < 0)
680 return ret;
681
682 if (dev->flash_mode) {
developer7800b8d2022-06-23 22:15:56 +0800683 ret = besra_mcu_apply_group_cal(dev);
developerb11a5392022-03-31 00:34:47 +0800684 if (ret)
685 return ret;
686 }
687
688 /* Beacon and mgmt frames should occupy wcid 0 */
developer7800b8d2022-06-23 22:15:56 +0800689 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, BESRA_WTBL_STA);
developerb11a5392022-03-31 00:34:47 +0800690 if (idx)
691 return -ENOSPC;
692
693 dev->mt76.global_wcid.idx = idx;
694 dev->mt76.global_wcid.hw_key_idx = -1;
695 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
696 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
697
698 return 0;
699}
700
developer7800b8d2022-06-23 22:15:56 +0800701void besra_set_stream_vht_txbf_caps(struct besra_phy *phy)
developerb11a5392022-03-31 00:34:47 +0800702{
703 int nss;
704 u32 *cap;
705
706 if (!phy->mt76->cap.has_5ghz)
707 return;
708
709 nss = hweight8(phy->mt76->chainmask);
710 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
711
712 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
713 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
714 (3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
715
716 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
717 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
718 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
719
720 if (nss < 2)
721 return;
722
723 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
724 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
725 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
726 nss - 1);
727}
728
729static void
developer7800b8d2022-06-23 22:15:56 +0800730besra_set_stream_he_txbf_caps(struct ieee80211_sta_he_cap *he_cap,
developerb11a5392022-03-31 00:34:47 +0800731 int vif, int nss)
732{
733 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
734 u8 c;
735
736#ifdef CONFIG_MAC80211_MESH
737 if (vif == NL80211_IFTYPE_MESH_POINT)
738 return;
739#endif
740
741 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
742 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
743
744 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK |
745 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
746 elem->phy_cap_info[5] &= ~c;
747
748 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
749 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
750 elem->phy_cap_info[6] &= ~c;
751
752 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
753
754 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
755 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO |
756 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO;
757 elem->phy_cap_info[2] |= c;
758
759 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
760 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
761 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
762 elem->phy_cap_info[4] |= c;
763
764 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
765 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
766 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
767
768 if (vif == NL80211_IFTYPE_STATION)
769 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
770
771 elem->phy_cap_info[6] |= c;
772
773 if (nss < 2)
774 return;
775
776 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
777 elem->phy_cap_info[7] |= min_t(int, nss - 1, 2) << 3;
778
779 if (vif != NL80211_IFTYPE_AP)
780 return;
781
782 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
783 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
784
developer66cd2092022-05-10 15:43:01 +0800785 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
786 nss - 1) |
787 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
788 nss - 1);
developerb11a5392022-03-31 00:34:47 +0800789 elem->phy_cap_info[5] |= c;
790
791 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
792 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
793 elem->phy_cap_info[6] |= c;
developer66cd2092022-05-10 15:43:01 +0800794
795 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
796 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
797 elem->phy_cap_info[7] |= c;
developerb11a5392022-03-31 00:34:47 +0800798}
799
800static void
developer7800b8d2022-06-23 22:15:56 +0800801besra_gen_ppe_thresh(u8 *he_ppet, int nss)
developerb11a5392022-03-31 00:34:47 +0800802{
803 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */
developer66cd2092022-05-10 15:43:01 +0800804 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71};
developerb11a5392022-03-31 00:34:47 +0800805
806 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) |
807 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK,
808 ru_bit_mask);
809
810 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE *
811 nss * hweight8(ru_bit_mask) * 2;
812 ppet_size = DIV_ROUND_UP(ppet_bits, 8);
813
814 for (i = 0; i < ppet_size - 1; i++)
815 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3];
816
817 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] &
818 (0xff >> (8 - (ppet_bits - 1) % 8));
819}
820
821static int
developer7800b8d2022-06-23 22:15:56 +0800822besra_init_he_caps(struct besra_phy *phy, enum nl80211_band band,
developerb11a5392022-03-31 00:34:47 +0800823 struct ieee80211_sband_iftype_data *data)
824{
825 int i, idx = 0, nss = hweight8(phy->mt76->chainmask);
826 u16 mcs_map = 0;
827 u16 mcs_map_160 = 0;
828 u8 nss_160;
829
developer7800b8d2022-06-23 22:15:56 +0800830 /* Can do 1/2 of NSS streams in 160Mhz mode for besra */
developerb11a5392022-03-31 00:34:47 +0800831 nss_160 = nss;
832
833 for (i = 0; i < 8; i++) {
834 if (i < nss)
835 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
836 else
837 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
838
839 if (i < nss_160)
840 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
841 else
842 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
843 }
844
845 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
846 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap;
847 struct ieee80211_he_cap_elem *he_cap_elem =
848 &he_cap->he_cap_elem;
849 struct ieee80211_he_mcs_nss_supp *he_mcs =
850 &he_cap->he_mcs_nss_supp;
851
852 switch (i) {
853 case NL80211_IFTYPE_STATION:
854 case NL80211_IFTYPE_AP:
855#ifdef CONFIG_MAC80211_MESH
856 case NL80211_IFTYPE_MESH_POINT:
857#endif
858 break;
859 default:
860 continue;
861 }
862
863 data[idx].types_mask = BIT(i);
864 he_cap->has_he = true;
865
866 he_cap_elem->mac_cap_info[0] =
867 IEEE80211_HE_MAC_CAP0_HTC_HE;
868 he_cap_elem->mac_cap_info[3] =
869 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
870 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
871 he_cap_elem->mac_cap_info[4] =
872 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
873
874 if (band == NL80211_BAND_2GHZ)
875 he_cap_elem->phy_cap_info[0] =
876 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
developer66cd2092022-05-10 15:43:01 +0800877 else
developerb11a5392022-03-31 00:34:47 +0800878 he_cap_elem->phy_cap_info[0] =
879 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
880 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G |
881 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G;
882
883 he_cap_elem->phy_cap_info[1] =
884 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
885 he_cap_elem->phy_cap_info[2] =
886 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
887 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
888
889 switch (i) {
890 case NL80211_IFTYPE_AP:
891 he_cap_elem->mac_cap_info[0] |=
892 IEEE80211_HE_MAC_CAP0_TWT_RES;
893 he_cap_elem->mac_cap_info[2] |=
894 IEEE80211_HE_MAC_CAP2_BSR;
895 he_cap_elem->mac_cap_info[4] |=
896 IEEE80211_HE_MAC_CAP4_BQR;
897 he_cap_elem->mac_cap_info[5] |=
898 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
899 he_cap_elem->phy_cap_info[3] |=
900 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
901 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
902 he_cap_elem->phy_cap_info[6] |=
903 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
904 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
905 he_cap_elem->phy_cap_info[9] |=
906 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
907 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
908 break;
909 case NL80211_IFTYPE_STATION:
910 he_cap_elem->mac_cap_info[1] |=
911 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
912
913 if (band == NL80211_BAND_2GHZ)
914 he_cap_elem->phy_cap_info[0] |=
915 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
developer66cd2092022-05-10 15:43:01 +0800916 else
developerb11a5392022-03-31 00:34:47 +0800917 he_cap_elem->phy_cap_info[0] |=
918 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
919
920 he_cap_elem->phy_cap_info[1] |=
921 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
922 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
923 he_cap_elem->phy_cap_info[3] |=
924 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
925 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
926 he_cap_elem->phy_cap_info[6] |=
927 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
928 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
929 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
930 he_cap_elem->phy_cap_info[7] |=
931 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
932 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
933 he_cap_elem->phy_cap_info[8] |=
934 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
935 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
936 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
937 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
938 he_cap_elem->phy_cap_info[9] |=
939 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
940 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
941 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
942 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
943 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
944 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
945 break;
946 }
947
948 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
949 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
950 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160);
951 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160);
952 he_mcs->rx_mcs_80p80 = cpu_to_le16(mcs_map_160);
953 he_mcs->tx_mcs_80p80 = cpu_to_le16(mcs_map_160);
954
developer7800b8d2022-06-23 22:15:56 +0800955 besra_set_stream_he_txbf_caps(he_cap, i, nss);
developerb11a5392022-03-31 00:34:47 +0800956
957 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
958 if (he_cap_elem->phy_cap_info[6] &
959 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
developer7800b8d2022-06-23 22:15:56 +0800960 besra_gen_ppe_thresh(he_cap->ppe_thres, nss);
developerb11a5392022-03-31 00:34:47 +0800961 } else {
962 he_cap_elem->phy_cap_info[9] |=
963 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US;
964 }
developer66cd2092022-05-10 15:43:01 +0800965
966 if (band == NL80211_BAND_6GHZ) {
967 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
968 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
969
970 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_8,
971 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
972 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
973 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
974 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
975 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
976
977 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap);
978 }
979
developerb11a5392022-03-31 00:34:47 +0800980 idx++;
981 }
982
983 return idx;
984}
985
developer7800b8d2022-06-23 22:15:56 +0800986void besra_set_stream_he_caps(struct besra_phy *phy)
developerb11a5392022-03-31 00:34:47 +0800987{
988 struct ieee80211_sband_iftype_data *data;
989 struct ieee80211_supported_band *band;
990 int n;
991
992 if (phy->mt76->cap.has_2ghz) {
993 data = phy->iftype[NL80211_BAND_2GHZ];
developer7800b8d2022-06-23 22:15:56 +0800994 n = besra_init_he_caps(phy, NL80211_BAND_2GHZ, data);
developerb11a5392022-03-31 00:34:47 +0800995
996 band = &phy->mt76->sband_2g.sband;
997 band->iftype_data = data;
998 band->n_iftype_data = n;
999 }
1000
1001 if (phy->mt76->cap.has_5ghz) {
1002 data = phy->iftype[NL80211_BAND_5GHZ];
developer7800b8d2022-06-23 22:15:56 +08001003 n = besra_init_he_caps(phy, NL80211_BAND_5GHZ, data);
developerb11a5392022-03-31 00:34:47 +08001004
1005 band = &phy->mt76->sband_5g.sband;
1006 band->iftype_data = data;
1007 band->n_iftype_data = n;
1008 }
developer66cd2092022-05-10 15:43:01 +08001009
1010 if (phy->mt76->cap.has_6ghz) {
1011 data = phy->iftype[NL80211_BAND_6GHZ];
developer7800b8d2022-06-23 22:15:56 +08001012 n = besra_init_he_caps(phy, NL80211_BAND_6GHZ, data);
developer66cd2092022-05-10 15:43:01 +08001013
1014 band = &phy->mt76->sband_6g.sband;
1015 band->iftype_data = data;
1016 band->n_iftype_data = n;
1017 }
developerb11a5392022-03-31 00:34:47 +08001018}
1019
developer7800b8d2022-06-23 22:15:56 +08001020static void besra_unregister_ext_phy(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +08001021{
developer7800b8d2022-06-23 22:15:56 +08001022 struct besra_phy *phy = besra_ext_phy(dev);
developerb11a5392022-03-31 00:34:47 +08001023 struct mt76_phy *mphy = dev->mt76.phy2;
1024
1025 if (!phy)
1026 return;
1027
developer7800b8d2022-06-23 22:15:56 +08001028 besra_unregister_thermal(phy);
developerb11a5392022-03-31 00:34:47 +08001029 mt76_unregister_phy(mphy);
1030 ieee80211_free_hw(mphy->hw);
1031 dev->mt76.phy2 = NULL;
1032}
1033
developer7800b8d2022-06-23 22:15:56 +08001034static void besra_unregister_tri_phy(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +08001035{
developer7800b8d2022-06-23 22:15:56 +08001036 struct besra_phy *phy = besra_tri_phy(dev);
developerb11a5392022-03-31 00:34:47 +08001037 struct mt76_phy *mphy = dev->mt76.phy3;
1038
1039 if (!phy)
1040 return;
1041
developer7800b8d2022-06-23 22:15:56 +08001042 besra_unregister_thermal(phy);
developerb11a5392022-03-31 00:34:47 +08001043 mt76_unregister_phy(mphy);
1044 ieee80211_free_hw(mphy->hw);
1045 dev->mt76.phy3 = NULL;
1046}
1047
developer7800b8d2022-06-23 22:15:56 +08001048int besra_register_device(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +08001049{
1050 struct ieee80211_hw *hw = mt76_hw(dev);
1051 int ret;
1052
1053 dev->phy.dev = dev;
1054 dev->phy.mt76 = &dev->mt76.phy;
1055 dev->mt76.phy.priv = &dev->phy;
developer7800b8d2022-06-23 22:15:56 +08001056 INIT_WORK(&dev->rc_work, besra_mac_sta_rc_work);
1057 INIT_DELAYED_WORK(&dev->mphy.mac_work, besra_mac_work);
developerb11a5392022-03-31 00:34:47 +08001058 INIT_LIST_HEAD(&dev->sta_rc_list);
1059 INIT_LIST_HEAD(&dev->sta_poll_list);
1060 INIT_LIST_HEAD(&dev->twt_list);
1061 spin_lock_init(&dev->sta_poll_lock);
1062
1063 init_waitqueue_head(&dev->reset_wait);
developer7800b8d2022-06-23 22:15:56 +08001064 INIT_WORK(&dev->reset_work, besra_mac_reset_work);
developerb11a5392022-03-31 00:34:47 +08001065
developer7800b8d2022-06-23 22:15:56 +08001066 ret = besra_init_hardware(dev);
developerb11a5392022-03-31 00:34:47 +08001067 if (ret)
1068 return ret;
1069
developer7800b8d2022-06-23 22:15:56 +08001070 besra_init_wiphy(hw);
developerb11a5392022-03-31 00:34:47 +08001071
1072#ifdef CONFIG_NL80211_TESTMODE
developer7800b8d2022-06-23 22:15:56 +08001073 dev->mt76.test_ops = &besra_testmode_ops;
developerb11a5392022-03-31 00:34:47 +08001074#endif
1075
1076 /* init led callbacks */
1077 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
developer7800b8d2022-06-23 22:15:56 +08001078 dev->mt76.led_cdev.brightness_set = besra_led_set_brightness;
1079 dev->mt76.led_cdev.blink_set = besra_led_set_blink;
developerb11a5392022-03-31 00:34:47 +08001080 }
1081
1082 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1083 ARRAY_SIZE(mt76_rates));
1084 if (ret)
1085 return ret;
1086
developer7800b8d2022-06-23 22:15:56 +08001087 ret = besra_thermal_init(&dev->phy);
developerb11a5392022-03-31 00:34:47 +08001088 if (ret)
1089 return ret;
1090
1091 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1092
developer7800b8d2022-06-23 22:15:56 +08001093 ret = besra_register_ext_phy(dev);
developerb11a5392022-03-31 00:34:47 +08001094 if (ret)
1095 return ret;
1096
developer7800b8d2022-06-23 22:15:56 +08001097 ret = besra_register_tri_phy(dev);
developerb11a5392022-03-31 00:34:47 +08001098 if (ret)
1099 return ret;
1100
developer7800b8d2022-06-23 22:15:56 +08001101 return besra_init_debugfs(&dev->phy);
developerb11a5392022-03-31 00:34:47 +08001102}
1103
developer7800b8d2022-06-23 22:15:56 +08001104void besra_unregister_device(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +08001105{
developer7800b8d2022-06-23 22:15:56 +08001106 besra_unregister_tri_phy(dev);
1107 besra_unregister_ext_phy(dev);
1108 besra_unregister_thermal(&dev->phy);
developerb11a5392022-03-31 00:34:47 +08001109 mt76_unregister_device(&dev->mt76);
developer7800b8d2022-06-23 22:15:56 +08001110 besra_mcu_exit(dev);
1111 besra_tx_token_put(dev);
1112 besra_dma_cleanup(dev);
developerb11a5392022-03-31 00:34:47 +08001113 tasklet_disable(&dev->irq_tasklet);
1114
1115 mt76_free_device(&dev->mt76);
1116}