| developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 1 | /*
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| 2 | * Copyright (c) 2017 MediaTek Inc.
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| 3 | * Author: Chen Zhong <chen.zhong@mediatek.com>
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| 4 | *
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| 5 | * This program is free software; you can redistribute it and/or modify
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| 6 | * it under the terms of the GNU General Public License version 2 as
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| 7 | * published by the Free Software Foundation.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful,
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| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 12 | * GNU General Public License for more details.
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| 13 | */
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| 14 |
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| 15 | #ifndef _DT_BINDINGS_CLK_MT7986_H
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| 16 | #define _DT_BINDINGS_CLK_MT7986_H
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| 17 |
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| 18 | /* INFRACFG */
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| 19 |
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| 20 | #define CK_INFRA_CK_F26M 0
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| 21 | #define CK_INFRA_UART 1
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| 22 | #define CK_INFRA_ISPI0 2
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| 23 | #define CK_INFRA_I2C 3
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| 24 | #define CK_INFRA_ISPI1 4
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| 25 | #define CK_INFRA_PWM 5
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| 26 | #define CK_INFRA_66M_MCK 6
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| 27 | #define CK_INFRA_CK_F32K 7
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| 28 | #define CK_INFRA_PCIE_CK 8
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| 29 | #define CK_INFRA_PWM_BCK 9
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| 30 | #define CK_INFRA_PWM_CK1 10
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| 31 | #define CK_INFRA_PWM_CK2 11
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| 32 | #define CK_INFRA_133M_HCK 12
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| 33 | #define CK_INFRA_EIP_CK 13
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| 34 | #define CK_INFRA_66M_PHCK 14
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| 35 | #define CK_INFRA_FAUD_L_CK 15
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| 36 | #define CK_INFRA_FAUD_AUD_CK 16
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| 37 | #define CK_INFRA_FAUD_EG2_CK 17
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| 38 | #define CK_INFRA_I2CS_CK 18
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| 39 | #define CK_INFRA_MUX_UART0 19
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| 40 | #define CK_INFRA_MUX_UART1 20
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| 41 | #define CK_INFRA_MUX_UART2 21
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| 42 | #define CK_INFRA_NFI_CK 22
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| 43 | #define CK_INFRA_SPINFI_CK 23
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| 44 | #define CK_INFRA_MUX_SPI0 24
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| 45 | #define CK_INFRA_MUX_SPI1 25
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| 46 | #define CK_INFRA_RTC_32K 26
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| 47 | #define CK_INFRA_FMSDC_CK 27
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| 48 | #define CK_INFRA_FMSDC_HCK_CK 28
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| 49 | #define CK_INFRA_PERI_133M 29
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| 50 | #define CK_INFRA_133M_PHCK 30
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| 51 | #define CK_INFRA_USB_SYS_CK 31
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| 52 | #define CK_INFRA_USB_CK 32
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| 53 | #define CK_INFRA_USB_XHCI_CK 33
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| 54 | #define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
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| 55 | #define CK_INFRA_F26M_CK0 35
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| 56 | #define CLK_INFRA_NR_CLK 36
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| 57 |
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| 58 | /* TOPCKGEN */
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| 59 |
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| 60 | #define CK_TOP_CB_CKSQ_40M 0
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| 61 | #define CK_TOP_CB_M_416M 1
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| 62 | #define CK_TOP_CB_M_D2 2
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| 63 | #define CK_TOP_CB_M_D4 3
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| 64 | #define CK_TOP_CB_M_D8 4
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| 65 | #define CK_TOP_M_D8_D2 5
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| 66 | #define CK_TOP_M_D3_D2 6
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| 67 | #define CK_TOP_CB_MM_D2 7
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| 68 | #define CK_TOP_CB_MM_D4 8
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| 69 | #define CK_TOP_CB_MM_D8 9
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| 70 | #define CK_TOP_MM_D8_D2 10
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| 71 | #define CK_TOP_MM_D3_D8 11
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| 72 | #define CK_TOP_CB_U2_PHYD_CK 12
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| 73 | #define CK_TOP_CB_APLL2_196M 13
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| 74 | #define CK_TOP_APLL2_D4 14
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| 75 | #define CK_TOP_CB_NET1_D4 15
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| 76 | #define CK_TOP_CB_NET1_D5 16
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| 77 | #define CK_TOP_NET1_D5_D2 17
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| 78 | #define CK_TOP_NET1_D5_D4 18
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| 79 | #define CK_TOP_NET1_D8_D2 19
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| 80 | #define CK_TOP_NET1_D8_D4 20
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| 81 | #define CK_TOP_CB_NET2_800M 21
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| 82 | #define CK_TOP_CB_NET2_D4 22
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| 83 | #define CK_TOP_NET2_D4_D2 23
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| 84 | #define CK_TOP_NET2_D3_D2 24
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| 85 | #define CK_TOP_CB_WEDMCU_760M 25
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| 86 | #define CK_TOP_WEDMCU_D5_D2 26
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| 87 | #define CK_TOP_CB_SGM_325M 27
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| 88 | #define CK_TOP_CB_CKSQ_40M_D2 28
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| 89 | #define CK_TOP_CB_RTC_32K 29
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| 90 | #define CK_TOP_CB_RTC_32P7K 30
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| 91 | #define CK_TOP_NFI1X 31
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| 92 | #define CK_TOP_USB_EQ_RX250M 32
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| 93 | #define CK_TOP_USB_TX250M 33
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| 94 | #define CK_TOP_USB_LN0_CK 34
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| 95 | #define CK_TOP_USB_CDR_CK 35
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| 96 | #define CK_TOP_SPINFI_BCK 36
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| 97 | #define CK_TOP_I2C_BCK 37
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| 98 | #define CK_TOP_PEXTP_TL 38
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| 99 | #define CK_TOP_EMMC_250M 39
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| 100 | #define CK_TOP_EMMC_416M 40
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| 101 | #define CK_TOP_F_26M_ADC_CK 41
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| 102 | #define CK_TOP_SYSAXI 42
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| 103 | #define CK_TOP_NETSYS_WED_MCU 43
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| 104 | #define CK_TOP_NETSYS_2X 44
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| 105 | #define CK_TOP_SGM_325M 45
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| 106 | #define CK_TOP_A1SYS 46
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| 107 | #define CK_TOP_EIP_B 47
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| 108 | #define CK_TOP_F26M 48
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| 109 | #define CK_TOP_AUD_L 49
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| 110 | #define CK_TOP_A_TUNER 50
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| 111 | #define CK_TOP_U2U3_REF 51
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| 112 | #define CK_TOP_U2U3_SYS 52
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| 113 | #define CK_TOP_U2U3_XHCI 53
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| 114 | #define CK_TOP_AP2CNN_HOST 54
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| 115 | #define CK_TOP_NFI1X_SEL 55
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| 116 | #define CK_TOP_SPINFI_SEL 56
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| 117 | #define CK_TOP_SPI_SEL 57
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| 118 | #define CK_TOP_SPIM_MST_SEL 58
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| 119 | #define CK_TOP_UART_SEL 59
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| 120 | #define CK_TOP_PWM_SEL 60
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| 121 | #define CK_TOP_I2C_SEL 61
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| 122 | #define CK_TOP_PEXTP_TL_SEL 62
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| 123 | #define CK_TOP_EMMC_250M_SEL 63
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| 124 | #define CK_TOP_EMMC_416M_SEL 64
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| 125 | #define CK_TOP_F_26M_ADC_SEL 65
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| 126 | #define CK_TOP_DRAMC_SEL 66
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| 127 | #define CK_TOP_DRAMC_MD32_SEL 67
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| 128 | #define CK_TOP_SYSAXI_SEL 68
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| 129 | #define CK_TOP_SYSAPB_SEL 69
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| 130 | #define CK_TOP_ARM_DB_MAIN_SEL 70
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| 131 | #define CK_TOP_ARM_DB_JTSEL 71
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| 132 | #define CK_TOP_NETSYS_SEL 72
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| 133 | #define CK_TOP_NETSYS_500M_SEL 73
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| 134 | #define CK_TOP_NETSYS_MCU_SEL 74
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| 135 | #define CK_TOP_NETSYS_2X_SEL 75
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| 136 | #define CK_TOP_SGM_325M_SEL 76
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| 137 | #define CK_TOP_SGM_REG_SEL 77
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| 138 | #define CK_TOP_A1SYS_SEL 78
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| 139 | #define CK_TOP_CONN_MCUSYS_SEL 79
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| 140 | #define CK_TOP_EIP_B_SEL 80
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| 141 | #define CK_TOP_PCIE_PHY_SEL 81
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| 142 | #define CK_TOP_USB3_PHY_SEL 82
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| 143 | #define CK_TOP_F26M_SEL 83
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| 144 | #define CK_TOP_AUD_L_SEL 84
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| 145 | #define CK_TOP_A_TUNER_SEL 85
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| 146 | #define CK_TOP_U2U3_SEL 86
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| 147 | #define CK_TOP_U2U3_SYS_SEL 87
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| 148 | #define CK_TOP_U2U3_XHCI_SEL 88
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| 149 | #define CK_TOP_DA_U2_REFSEL 89
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| 150 | #define CK_TOP_DA_U2_CK_1P_SEL 90
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| 151 | #define CK_TOP_AP2CNN_HOST_SEL 91
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| 152 | #define CLK_TOP_NR_CLK 92
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| 153 |
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| 154 | /* INFRACFG_AO */
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| 155 |
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| 156 | #define CK_INFRA_UART0_SEL 0
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| 157 | #define CK_INFRA_UART1_SEL 1
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| 158 | #define CK_INFRA_UART2_SEL 2
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| 159 | #define CK_INFRA_SPI0_SEL 3
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| 160 | #define CK_INFRA_SPI1_SEL 4
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| 161 | #define CK_INFRA_PWM1_SEL 5
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| 162 | #define CK_INFRA_PWM2_SEL 6
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| 163 | #define CK_INFRA_PWM_BSEL 7
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| 164 | #define CK_INFRA_PCIE_SEL 8
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| 165 | #define CK_INFRA_GPT_STA 9
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| 166 | #define CK_INFRA_PWM_HCK 10
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| 167 | #define CK_INFRA_PWM_STA 11
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| 168 | #define CK_INFRA_PWM1_CK 12
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| 169 | #define CK_INFRA_PWM2_CK 13
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| 170 | #define CK_INFRA_CQ_DMA_CK 14
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| 171 | #define CK_INFRA_EIP97_CK 15
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| 172 | #define CK_INFRA_AUD_BUS_CK 16
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| 173 | #define CK_INFRA_AUD_26M_CK 17
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| 174 | #define CK_INFRA_AUD_L_CK 18
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| 175 | #define CK_INFRA_AUD_AUD_CK 19
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| 176 | #define CK_INFRA_AUD_EG2_CK 20
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| 177 | #define CK_INFRA_DRAMC_26M_CK 21
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| 178 | #define CK_INFRA_DBG_CK 22
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| 179 | #define CK_INFRA_AP_DMA_CK 23
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| 180 | #define CK_INFRA_SEJ_CK 24
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| 181 | #define CK_INFRA_SEJ_13M_CK 25
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| 182 | #define CK_INFRA_THERM_CK 26
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| 183 | #define CK_INFRA_I2CO_CK 27
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| 184 | #define CK_INFRA_UART0_CK 28
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| 185 | #define CK_INFRA_UART1_CK 29
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| 186 | #define CK_INFRA_UART2_CK 30
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| 187 | #define CK_INFRA_NFI1_CK 31
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| 188 | #define CK_INFRA_SPINFI1_CK 32
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| 189 | #define CK_INFRA_NFI_HCK_CK 33
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| 190 | #define CK_INFRA_SPI0_CK 34
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| 191 | #define CK_INFRA_SPI1_CK 35
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| 192 | #define CK_INFRA_SPI0_HCK_CK 36
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| 193 | #define CK_INFRA_SPI1_HCK_CK 37
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| 194 | #define CK_INFRA_FRTC_CK 38
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| 195 | #define CK_INFRA_MSDC_CK 39
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| 196 | #define CK_INFRA_MSDC_HCK_CK 40
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| 197 | #define CK_INFRA_MSDC_133M_CK 41
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| 198 | #define CK_INFRA_MSDC_66M_CK 42
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| 199 | #define CK_INFRA_ADC_26M_CK 43
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| 200 | #define CK_INFRA_ADC_FRC_CK 44
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| 201 | #define CK_INFRA_FBIST2FPC_CK 45
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| 202 | #define CK_INFRA_IUSB_133_CK 46
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| 203 | #define CK_INFRA_IUSB_66M_CK 47
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| 204 | #define CK_INFRA_IUSB_SYS_CK 48
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| 205 | #define CK_INFRA_IUSB_CK 49
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| 206 | #define CK_INFRA_IPCIE_CK 50
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| 207 | #define CK_INFRA_IPCIER_CK 51
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| 208 | #define CK_INFRA_IPCIEB_CK 52
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| 209 | #define CLK_INFRA_AO_NR_CLK 53
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| 210 |
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| 211 | /* APMIXEDSYS */
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| 212 |
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| 213 | #define CK_APMIXED_ARMPLL 0
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| 214 | #define CK_APMIXED_NET2PLL 1
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| 215 | #define CK_APMIXED_MMPLL 2
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| 216 | #define CK_APMIXED_SGMPLL 3
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| 217 | #define CK_APMIXED_WEDMCUPLL 4
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| 218 | #define CK_APMIXED_NET1PLL 5
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| 219 | #define CK_APMIXED_MPLL 6
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| 220 | #define CK_APMIXED_APLL2 7
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| 221 | #define CLK_APMIXED_NR_CLK 8
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| 222 |
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| 223 | /* SGMIISYS_0 */
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| 224 |
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| 225 | #define CK_SGM0_TX_EN 0
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| 226 | #define CK_SGM0_RX_EN 1
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| 227 | #define CK_SGM0_CK0_EN 2
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| 228 | #define CK_SGM0_CDR_CK0_EN 3
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| 229 | #define CLK_SGMII0_NR_CLK 4
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| 230 |
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| 231 | /* SGMIISYS_1 */
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| 232 |
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| 233 | #define CK_SGM1_TX_EN 0
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| 234 | #define CK_SGM1_RX_EN 1
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| 235 | #define CK_SGM1_CK1_EN 2
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| 236 | #define CK_SGM1_CDR_CK1_EN 3
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| 237 | #define CLK_SGMII1_NR_CLK 4
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| 238 |
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| 239 | /* ETHSYS */
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| 240 |
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| 241 | #define CK_ETH_FE_EN 0
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| 242 | #define CK_ETH_GP2_EN 1
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| 243 | #define CK_ETH_GP1_EN 2
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| 244 | #define CK_ETH_WOCPU1_EN 3
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| 245 | #define CK_ETH_WOCPU0_EN 4
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| 246 | #define CLK_ETH_NR_CLK 5
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| 247 |
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| 248 | #endif /* _DT_BINDINGS_CLK_MT7986_H */
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| 249 |
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