blob: 9d1ca10f2633a7bfbe197eacb3471cd432110c2f [file] [log] [blame]
developer8cdcb262022-10-27 14:36:15 +08001From 0df9413c8ff0df4ed69b6e1577d7cd5fd2d72e5e Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Tue, 25 Oct 2022 18:25:25 +0800
4Subject: [PATCH 1/3] xHCI: change compliance mode de-emphasis default as gen1
developer2cdaeb12022-10-04 20:25:05 +08005
6Port0 is using Gen2 Phy for 10GHz, and Port0 is running
7on 5GHz actually. hence to change compliance mode de-
8emphasis default as Gen1.
9
10Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
developer8cdcb262022-10-27 14:36:15 +080011Signed-off-by: Sam Shih <sam.shih@mediatek.com>
developer2cdaeb12022-10-04 20:25:05 +080012---
developer8cdcb262022-10-27 14:36:15 +080013 drivers/usb/host/xhci-mtk.c | 18 +++++++++++++++++-
14 drivers/usb/host/xhci-mtk.h | 1 +
15 2 files changed, 18 insertions(+), 1 deletion(-)
developer2cdaeb12022-10-04 20:25:05 +080016
17diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
developer8cdcb262022-10-27 14:36:15 +080018index 5c0eb35cd007..77ddb8c05500 100644
developer2cdaeb12022-10-04 20:25:05 +080019--- a/drivers/usb/host/xhci-mtk.c
20+++ b/drivers/usb/host/xhci-mtk.c
developer8cdcb262022-10-27 14:36:15 +080021@@ -22,6 +22,11 @@
22 #include "xhci.h"
developer2cdaeb12022-10-04 20:25:05 +080023 #include "xhci-mtk.h"
developer2cdaeb12022-10-04 20:25:05 +080024
25+/* COMPLIANCE_CP5_CP7_TXDEEMPH_10G register */
26+#define COMPLIANCE_CP5_CP7_TXDEEMPH_10G 0x2428
27+#define CP5_CP7_TXDEEMPH_10G GENMASK(17, 0)
28+#define CP5_CP7_TXDEEMPH_10G_VAL(val) ((val) & 0x03FFFF)
29+
30 /* ip_pw_ctrl0 register */
31 #define CTRL0_IP_SW_RST BIT(0)
32
developer8cdcb262022-10-27 14:36:15 +080033@@ -413,6 +418,7 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
developer2cdaeb12022-10-04 20:25:05 +080034 {
35 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
36 int ret;
37+ u32 val;
38
39 if (usb_hcd_is_primary_hcd(hcd)) {
40 ret = xhci_mtk_ssusb_config(mtk);
developer8cdcb262022-10-27 14:36:15 +080041@@ -430,6 +436,15 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
developer2cdaeb12022-10-04 20:25:05 +080042 return ret;
43 }
44
45+ /* change COMPLIANCE_CP5_CP7_TXDEEMPH_10G as Gen1 instead Gen2 */
developer8cdcb262022-10-27 14:36:15 +080046+ if (mtk->p0_speed_fixup) {
developer2cdaeb12022-10-04 20:25:05 +080047+ val = readl(mtk->hcd->regs + COMPLIANCE_CP5_CP7_TXDEEMPH_10G);
48+ val &= ~CP5_CP7_TXDEEMPH_10G;
49+ val |= 0x00001;
50+ val = CP5_CP7_TXDEEMPH_10G_VAL(val);
51+ writel(val, mtk->hcd->regs + COMPLIANCE_CP5_CP7_TXDEEMPH_10G);
52+ }
53+
54 return ret;
55 }
56
developer8cdcb262022-10-27 14:36:15 +080057@@ -475,7 +490,8 @@ static int xhci_mtk_probe(struct platform_device *pdev)
58 /* optional property, ignore the error if it does not exist */
59 of_property_read_u32(node, "mediatek,u3p-dis-msk",
60 &mtk->u3p_dis_msk);
61-
62+ mtk->p0_speed_fixup = of_property_read_bool(node,
63+ "mediatek,p0_speed_fixup");
64 ret = usb_wakeup_of_property_parse(mtk, node);
65 if (ret) {
66 dev_err(dev, "failed to parse uwk property\n");
67diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
68index 2f702342de66..8a884e7b481b 100644
69--- a/drivers/usb/host/xhci-mtk.h
70+++ b/drivers/usb/host/xhci-mtk.h
71@@ -156,6 +156,7 @@ struct xhci_hcd_mtk {
72 struct regmap *uwk;
73 u32 uwk_reg_base;
74 u32 uwk_vers;
75+ bool p0_speed_fixup;
76 };
77
78 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
developer2cdaeb12022-10-04 20:25:05 +080079--
802.18.0
81