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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 76c9bcc2e2b084ba51a1dc0b4222e4f6e8813acb / . / target / linux / mediatek / files-5.4 / drivers / pinctrl / mediatek / pinctrl-mt7988.c
blob: 583ba90c4920813e6a484353e2322924c78f5a31 [file] [log] [blame]
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * The MT7988 driver based on Linux generic pinctrl binding.
4 *
5 * Copyright (C) 2020 MediaTek Inc.
6 * Author: Sam Shih <sam.shih@mediatek.com>
7 */
8
9#include "pinctrl-moore.h"
10
11enum MT7988_PINCTRL_REG_PAGE {
12 GPIO_BASE,
13 IOCFG_TR_BASE,
14 IOCFG_BR_BASE,
15 IOCFG_RB_BASE,
16 IOCFG_LB_BASE,
17 IOCFG_TL_BASE,
18};
19
20#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
21
22#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
23 _x_bits) \
24 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
25 _x_bits, 32, 0)
26
27#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
28 _x_bits) \
29 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
30 _x_bits, 32, 1)
31
32static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
33 PIN_FIELD(0, 83, 0x300, 0x10, 0, 4),
34};
35
36static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
37 PIN_FIELD(0, 83, 0x0, 0x10, 0, 1),
38};
39
40static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
41 PIN_FIELD(0, 83, 0x200, 0x10, 0, 1),
42};
43
44static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
45 PIN_FIELD(0, 83, 0x100, 0x10, 0, 1),
46};
47
48static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
49 PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
50 PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
51 PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
52 PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
53 PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
54 PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
55 PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
56
57 PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
58 PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
59 PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
60 PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
61
62 PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
63 PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
64 PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
65 PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
66
67 PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
68 PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
69 PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
70 PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
71
72 PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
73 PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
74
75 PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
76 PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
77 PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
78 PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
79 PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
80 PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
81 PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
82 PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
83 PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
84 PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
85 PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
86 PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
87 PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
88 PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
89 PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
90 PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
91 PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
92 PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
93 PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
94 PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
95 PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
96 PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
97 PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
98 PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
99 PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1),
100 PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1),
101 PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1),
102 PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
103 PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
104 PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
105 PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
106 PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
107 PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
108 PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
109
110 PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
111 PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
112 PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
113 PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
114 PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
115 PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
116 PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
117 PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
118 PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
119 PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
120 PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
121 PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
122 PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
123 PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
124
125 PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
126 PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
127 PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
128 PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
129
130 PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
131 PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
132 PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
133 PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1),
134 PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
135 PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
136 PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
137
138 PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
139 PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
140 PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
141 PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
142};
143
144static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
145 PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
146 PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
147 PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
148 PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
149 PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
150 PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
151 PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
152
153 PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
154 PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
155 PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
156 PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
157
158 PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
159 PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
160 PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
161 PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
162
163 PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
164 PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
165 PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
166 PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
167
168 PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
169 PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
170
171 PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
172 PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
173 PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
174 PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
175 PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
176 PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
177 PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
178 PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
179 PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
180 PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
181 PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
182 PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
183 PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
184 PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
185 PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
186 PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
187 PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
188 PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
189 PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
190 PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
191 PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
192 PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
193 PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
194 PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
195 PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1),
196 PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1),
197 PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1),
198 PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
199 PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
200 PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
201 PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
202 PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
203 PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
204 PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
205
206 PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
207 PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
208 PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
209 PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
210 PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
211 PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
212 PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
213 PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
214 PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
215 PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
216 PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
217 PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
218 PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
219 PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
220
221 PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
222 PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
223 PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
224 PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
225
226 PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
227 PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
228 PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
229 PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1),
230 PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
231 PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
232 PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
233
234 PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
235 PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
236 PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
237 PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
238};
239
240static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
241 PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1),
242 PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
243 PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
244 PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
245
246 PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
247 PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
248 PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
249
250 PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
251 PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
252 PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
253 PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1),
254 PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1),
255};
256
257static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
258 PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1),
259 PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
260 PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
261 PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
262
263 PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
264 PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
265
266 PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
267 PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
268 PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
269 PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
270
271 PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
272 PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
273 PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
274
275 PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
276 PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
277 PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
278 PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1),
279 PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1),
280};
281
282static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
283 PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
284 PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
285 PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
286 PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
287 PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
288 PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
289 PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
290
291 PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
292 PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
293 PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
294 PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
295
296 PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
297 PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
298 PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
299 PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
300
301 PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
302 PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
303
304 PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
305 PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
306 PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
307 PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
308 PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
309 PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
310 PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
311 PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
312 PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
313 PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
314 PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
315 PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
316 PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
317 PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3),
318 PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3),
319 PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3),
320 PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
321 PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
322 PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
323 PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
324 PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
325 PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
326 PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
327 PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
328 PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3),
329 PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3),
330 PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3),
331 PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
332 PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
333 PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
334 PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
335 PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
336 PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
337 PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
338
339 PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
340 PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
341 PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
342 PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
343 PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
344 PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
345 PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
346 PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
347 PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
348 PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
349 PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
350 PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
351 PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
352 PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
353
354 PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
355 PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
356
357 PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
358 PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
359 PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
360 PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3),
361 PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
362 PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
363 PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
364
365 PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
366 PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
367 PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
368 PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
369};
370
371static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
372 PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
373 PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
374 PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
375 PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
376 PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
377 PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
378 PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
379
380 PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
381 PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
382
383 PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
384 PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
385
386 PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
387 PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
388 PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
389 PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
390 PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
391 PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
392 PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
393 PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
394 PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
395 PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
396 PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
397 PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
398 PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
399 PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
400 PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
401 PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
402 PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
403 PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
404 PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
405 PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
406 PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
407 PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
408 PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
409 PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
410 PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1),
411 PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1),
412 PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1),
413 PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
414 PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
415 PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
416 PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
417 PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
418 PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
419 PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
420
421 PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
422 PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
423 PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
424 PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
425 PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
426 PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
427 PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
428 PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
429 PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
430 PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
431 PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
432 PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
433 PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
434
435 PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
436 PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
437
438 PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
439 PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
440
441 PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
442 PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
443 PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
444 PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
445};
446
447static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
448 PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
449 PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
450 PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
451 PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
452 PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
453 PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
454 PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
455
456 PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
457 PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
458
459 PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
460 PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
461
462 PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
463 PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
464 PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
465 PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
466 PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
467 PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
468 PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
469 PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
470 PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
471 PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
472 PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
473 PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
474 PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
475 PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
476 PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
477 PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
478 PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
479 PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
480 PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
481 PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
482 PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
483 PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
484 PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
485 PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
486 PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1),
487 PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1),
488 PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1),
489 PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
490 PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
491 PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
492 PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
493 PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
494 PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
495 PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
496
497 PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
498 PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
499 PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
500 PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
501 PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
502 PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
503 PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
504 PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
505 PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
506 PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
507 PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
508 PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
509 PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
510
511 PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
512 PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
513
514 PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
515 PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
516
517 PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
518 PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
519 PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
520 PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
521};
522
523static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
524 PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
525 PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
526 PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
527 PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
528 PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
529 PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
530 PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
531
532 PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
533 PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
534
535 PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
536 PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
537
538 PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
539 PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
540 PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
541 PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
542 PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
543 PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
544 PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
545 PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
546 PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
547 PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
548 PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
549 PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
550 PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
551 PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
552 PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
553 PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
554 PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
555 PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
556 PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
557 PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
558 PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
559 PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
560 PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
561 PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
562 PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1),
563 PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1),
564 PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1),
565 PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
566 PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
567 PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
568 PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
569 PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
570 PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
571 PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
572
573 PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
574 PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
575 PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
576 PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
577 PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
578 PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
579 PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
580 PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
581 PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
582 PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
583 PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
584 PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
585 PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
586
587 PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
588 PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
589
590 PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
591 PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
592
593 PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
594 PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
595 PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
596 PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
597};
598
599static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
600 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
601 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
602 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
603 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
604 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
605 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
606 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
607 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
608 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
609 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
610 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
611 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
612};
613
614static const struct mtk_pin_desc mt7988_pins[] = {
615 MT7988_PIN(0, "UART2_RXD"),
616 MT7988_PIN(1, "UART2_TXD"),
617 MT7988_PIN(2, "UART2_CTS"),
618 MT7988_PIN(3, "UART2_RTS"),
619 MT7988_PIN(4, "GPIO_A"),
620 MT7988_PIN(5, "SMI_0_MDC"),
621 MT7988_PIN(6, "SMI_0_MDIO"),
622 MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"),
623 MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
624 MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"),
625 MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
626 MT7988_PIN(11, "GPIO_P"),
627 MT7988_PIN(12, "WATCHDOG"),
628 MT7988_PIN(13, "GPIO_RESET"),
629 MT7988_PIN(14, "GPIO_WPS"),
630 MT7988_PIN(15, "PMIC_I2C_SCL"),
631 MT7988_PIN(16, "PMIC_I2C_SDA"),
632 MT7988_PIN(17, "I2C_1_SCL"),
633 MT7988_PIN(18, "I2C_1_SDA"),
634 MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"),
635 MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"),
636 MT7988_PIN(21, "PWMD1"),
637 MT7988_PIN(22, "SPI0_WP"),
638 MT7988_PIN(23, "SPI0_HOLD"),
639 MT7988_PIN(24, "SPI0_CSB"),
640 MT7988_PIN(25, "SPI0_MISO"),
641 MT7988_PIN(26, "SPI0_MOSI"),
642 MT7988_PIN(27, "SPI0_CLK"),
643 MT7988_PIN(28, "SPI1_CSB"),
644 MT7988_PIN(29, "SPI1_MISO"),
645 MT7988_PIN(30, "SPI1_MOSI"),
646 MT7988_PIN(31, "SPI1_CLK"),
647 MT7988_PIN(32, "SPI2_CLK"),
648 MT7988_PIN(33, "SPI2_MOSI"),
649 MT7988_PIN(34, "SPI2_MISO"),
650 MT7988_PIN(35, "SPI2_CSB"),
651 MT7988_PIN(36, "SPI2_HOLD"),
652 MT7988_PIN(37, "SPI2_WP"),
653 MT7988_PIN(38, "EMMC_RSTB"),
654 MT7988_PIN(39, "EMMC_DSL"),
655 MT7988_PIN(40, "EMMC_CK"),
656 MT7988_PIN(41, "EMMC_CMD"),
657 MT7988_PIN(42, "EMMC_DATA_7"),
658 MT7988_PIN(43, "EMMC_DATA_6"),
659 MT7988_PIN(44, "EMMC_DATA_5"),
660 MT7988_PIN(45, "EMMC_DATA_4"),
661 MT7988_PIN(46, "EMMC_DATA_3"),
662 MT7988_PIN(47, "EMMC_DATA_2"),
663 MT7988_PIN(48, "EMMC_DATA_1"),
664 MT7988_PIN(49, "EMMC_DATA_0"),
665 MT7988_PIN(50, "PCM_FS_I2S_LRCK"),
666 MT7988_PIN(51, "PCM_CLK_I2S_BCLK"),
667 MT7988_PIN(52, "PCM_DRX_I2S_DIN"),
668 MT7988_PIN(53, "PCM_DTX_I2S_DOUT"),
669 MT7988_PIN(54, "PCM_MCK_I2S_MCLK"),
670 MT7988_PIN(55, "UART0_RXD"),
671 MT7988_PIN(56, "UART0_TXD"),
672 MT7988_PIN(57, "PWMD0"),
673 MT7988_PIN(58, "JTAG_JTDI"),
674 MT7988_PIN(59, "JTAG_JTDO"),
675 MT7988_PIN(60, "JTAG_JTMS"),
676 MT7988_PIN(61, "JTAG_JTCLK"),
677 MT7988_PIN(62, "JTAG_JTRST_N"),
678 MT7988_PIN(63, "USB_DRV_VBUS_P1"),
679 MT7988_PIN(64, "LED_A"),
680 MT7988_PIN(65, "LED_B"),
681 MT7988_PIN(66, "LED_C"),
682 MT7988_PIN(67, "LED_D"),
683 MT7988_PIN(68, "LED_E"),
684 MT7988_PIN(69, "GPIO_B"),
685 MT7988_PIN(70, "GPIO_C"),
686 MT7988_PIN(71, "I2C_2_SCL"),
687 MT7988_PIN(72, "I2C_2_SDA"),
688 MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"),
689 MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"),
690 MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"),
691 MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
692 MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"),
693 MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
694 MT7988_PIN(79, "USB_DRV_VBUS_P0"),
695 MT7988_PIN(80, "UART1_RXD"),
696 MT7988_PIN(81, "UART1_TXD"),
697 MT7988_PIN(82, "UART1_CTS"),
698 MT7988_PIN(83, "UART1_RTS"),
699};
700
701/* jtag */
702static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
703static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
704
705static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
706static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
707
708static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
709static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
710
711static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
712static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
713
714static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
715static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
716
717static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
718static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
719
720/* int_usxgmii */
721static int mt7988_int_usxgmii_pins[] = { 2, 3 };
722static int mt7988_int_usxgmii_funcs[] = { 3, 3 };
723
724/* pwm */
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]725static int mt7988_pwm0_pins[] = { 57 };
726static int mt7988_pwm0_funcs[] = { 1 };
727
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]728static int mt7988_pwm1_pins[] = { 21 };
729static int mt7988_pwm1_funcs[] = { 1 };
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]730
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]731static int mt7988_pwm2_pins[] = { 80 };
732static int mt7988_pwm2_funcs[] = { 2 };
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]733
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]734static int mt7988_pwm3_pins[] = { 81 };
735static int mt7988_pwm3_funcs[] = { 2 };
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]736
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]737static int mt7988_pwm4_pins[] = { 82 };
738static int mt7988_pwm4_funcs[] = { 2 };
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]739
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]740static int mt7988_pwm5_pins[] = { 83 };
741static int mt7988_pwm5_funcs[] = { 2 };
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]742
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]743static int mt7988_pwm6_pins[] = { 69 };
744static int mt7988_pwm6_funcs[] = { 3 };
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]745
746static int mt7988_pwm7_pins[] = { 70 };
747static int mt7988_pwm7_funcs[] = { 3 };
748
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]749/* dfd */
750static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
751static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
752
753/* i2c */
754static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
755static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
756
757static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
758static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
759
760static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
761static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
762
763static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
764static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
765
766static int mt7988_i2c0_0_pins[] = { 5, 6 };
767static int mt7988_i2c0_0_funcs[] = { 2, 2 };
768
769static int mt7988_i2c1_sfp_pins[] = { 5, 6 };
770static int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
771
772static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
773static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
774
775static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
776static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
777
778static int mt7988_i2c0_1_pins[] = { 15, 16 };
779static int mt7988_i2c0_1_funcs[] = { 1, 1 };
780
781static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
782static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
783
784static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
785static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
786
787static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
788static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
789
790static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
791static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
792
793static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
794static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
795
796static int mt7988_i2c1_0_pins[] = { 17, 18 };
797static int mt7988_i2c1_0_funcs[] = { 1, 1 };
798
799static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
800static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
801
802static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
803static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
804
805static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
806static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
807
808static int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
809static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
810
811static int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
812static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
813
814static int mt7988_i2c1_2_pins[] = { 69, 70 };
815static int mt7988_i2c1_2_funcs[] = { 2, 2 };
816
817static int mt7988_i2c2_0_pins[] = { 69, 70 };
818static int mt7988_i2c2_0_funcs[] = { 4, 4 };
819
820static int mt7988_i2c2_1_pins[] = { 70, 71 };
821static int mt7988_i2c2_1_funcs[] = { 1, 1 };
822
823/* eth */
824static int mt7988_mdc_mdio0_pins[] = { 5, 6 };
825static int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
826
827static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
828static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
829
830static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
831static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
832
833static int mt7988_mdc_mdio1_pins[] = { 69, 70 };
834static int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
835
836/* pcie */
837static int mt7988_pcie_wake_n0_0_pins[] = { 7 };
838static int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
839
840static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
841static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
842
843static int mt7988_pcie_wake_n3_0_pins[] = { 9 };
844static int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
845
846static int mt7988_pcie_clk_req_n3_pins[] = { 10 };
847static int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
848
849static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
850static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
851
852static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
853static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
854
855static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
856static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
857
858static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
859static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
860
861static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
862static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
863
864static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
865static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
866
867static int mt7988_pcie_wake_n0_1_pins[] = { 13 };
868static int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
869
870static int mt7988_pcie_wake_n3_1_pins[] = { 14 };
871static int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
872
873static int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
874static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
875
876static int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
877static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
878
879static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
880static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
881
882static int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
883static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
884
885static int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
886static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
887
888static int mt7988_pcie_wake_n1_0_pins[] = { 75 };
889static int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
890
891static int mt7988_pcie_clk_req_n1_pins[] = { 76 };
892static int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
893
894static int mt7988_pcie_wake_n2_0_pins[] = { 77 };
895static int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
896
897static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
898static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
899
900static int mt7988_pcie_wake_n2_1_pins[] = { 79 };
901static int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
902
903/* pmic */
904static int mt7988_pmic_pins[] = { 11 };
905static int mt7988_pmic_funcs[] = { 1 };
906
907/* watchdog */
908static int mt7988_watchdog_pins[] = { 12 };
909static int mt7988_watchdog_funcs[] = { 1 };
910
911/* spi */
912static int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
913static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
914
915static int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
916static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
917
918static int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
919static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
920
921static int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
922static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
923
924static int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
925static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
926
927/* flash */
928static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
929static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
930
931static int mt7988_emmc_45_pins[] = {
932 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
933};
934static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
935
developer7d52c342022-11-03 11:46:34 +0800[diff] [blame]936static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 };
937static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 };
938
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]939static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43,
940 44, 45, 46, 47, 48, 49 };
941static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
942
943/* uart */
944static int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
945static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
946
947static int mt7988_tops_uart0_0_pins[] = { 22, 23 };
948static int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
949
950static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
951static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
952
953static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
954static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
955
956static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
957static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
958
959static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
960static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
961
962static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
963static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
964
965static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
966static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
967
968static int mt7988_tops_uart1_0_pins[] = { 28, 29 };
969static int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
970
971static int mt7988_tops_uart0_1_pins[] = { 30, 31 };
972static int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
973
974static int mt7988_tops_uart1_1_pins[] = { 36, 37 };
975static int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
976
977static int mt7988_uart0_pins[] = { 55, 56 };
978static int mt7988_uart0_funcs[] = { 1, 1 };
979
980static int mt7988_tops_uart0_2_pins[] = { 55, 56 };
981static int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
982
983static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
984static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
985
986static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
987static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
988
989static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
990static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
991
992static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
993static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
994
995static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
996static int mt7988_tops_uart1_2_funcs[] = {
997 4,
998 4,
999};
1000
1001static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
1002static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
1003
1004static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
1005static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
1006
1007static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
1008static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
1009
1010/* udi */
1011static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
1012static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
1013
developerd9283a42022-10-24 14:30:14 +0800[diff] [blame]1014/* i2s */
1015static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
1016static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
1017
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1018/* pcm */
developerd9283a42022-10-24 14:30:14 +0800[diff] [blame]1019static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
1020static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1021
1022/* led */
1023static int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
1024static int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 };
1025
1026static int mt7988_2p5gbe_led1_pins[] = { 62 };
1027static int mt7988_2p5gbe_led1_funcs[] = { 6 };
1028
1029static int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 };
1030static int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 };
1031
1032static int mt7988_2p5gbe_led0_pins[] = { 68 };
1033static int mt7988_2p5gbe_led0_funcs[] = { 1 };
1034
1035/* usb */
1036static int mt7988_drv_vbus_p1_pins[] = { 63 };
1037static int mt7988_drv_vbus_p1_funcs[] = { 1 };
1038
1039static int mt7988_drv_vbus_pins[] = { 79 };
1040static int mt7988_drv_vbus_funcs[] = { 1 };
1041
1042static const struct group_desc mt7988_groups[] = {
1043 /* @GPIO(0,1,2,3): uart2 */
1044 PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
1045 /* @GPIO(0,1,2,3,4): tops_jtag0_0 */
1046 PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
1047 /* @GPIO(2,3): int_usxgmii */
1048 PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1049 /* @GPIO(0,1,2,3,4): dfd */
1050 PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
1051 /* @GPIO(0,1): xfi_phy0_i2c0 */
1052 PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
1053 /* @GPIO(0,1): xfi_phy1_i2c0 */
1054 PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
1055 /* @GPIO(3,4): xfi_phy_pll_i2c0 */
1056 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
1057 /* @GPIO(3,4): xfi_phy_pll_i2c1 */
1058 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
1059 /* @GPIO(5,6) i2c0_0 */
1060 PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
1061 /* @GPIO(5,6) i2c1_sfp */
1062 PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
1063 /* @GPIO(5,6) xfi_pextp_phy0_i2c */
1064 PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
1065 /* @GPIO(5,6) xfi_pextp_phy1_i2c */
1066 PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
1067 /* @GPIO(5,6) mdc_mdio0 */
1068 PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
1069 /* @GPIO(7): pcie_wake_n0_0 */
1070 PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
1071 /* @GPIO(8): pcie_clk_req_n0_0 */
1072 PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
1073 /* @GPIO(9): pcie_wake_n3_0 */
1074 PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
1075 /* @GPIO(10): pcie_clk_req_n3 */
1076 PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
1077 /* @GPIO(10): pcie_clk_req_n0_1 */
1078 PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
1079 /* @GPIO(7,8) pcie_p0_phy_i2c */
1080 PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
1081 /* @GPIO(7,8) pcie_p1_phy_i2c */
1082 PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
1083 /* @GPIO(7,8) pcie_p2_phy_i2c */
1084 PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
1085 /* @GPIO(9,10) pcie_p3_phy_i2c */
1086 PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
1087 /* @GPIO(9,10) ckm_phy_i2c */
1088 PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
1089 /* @GPIO(11): pmic */
1090 PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
1091 /* @GPIO(12): watchdog */
1092 PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
1093 /* @GPIO(13): pcie_wake_n0_1 */
1094 PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
1095 /* @GPIO(14): pcie_wake_n3_1 */
1096 PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
1097 /* @GPIO(15,16) i2c0_1 */
1098 PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
1099 /* @GPIO(15,16) u30_phy_i2c0 */
1100 PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
1101 /* @GPIO(15,16) u32_phy_i2c0 */
1102 PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
1103 /* @GPIO(15,16) xfi_phy0_i2c1 */
1104 PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
1105 /* @GPIO(15,16) xfi_phy1_i2c1 */
1106 PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
1107 /* @GPIO(15,16) xfi_phy_pll_i2c2 */
1108 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
1109 /* @GPIO(17,18) i2c1_0 */
1110 PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
1111 /* @GPIO(17,18) u30_phy_i2c1 */
1112 PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
1113 /* @GPIO(17,18) u32_phy_i2c1 */
1114 PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
1115 /* @GPIO(17,18) xfi_phy_pll_i2c3 */
1116 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
1117 /* @GPIO(17,18) sgmii0_i2c */
1118 PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
1119 /* @GPIO(17,18) sgmii1_i2c */
1120 PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
1121 /* @GPIO(19): pcie_2l_0_pereset */
1122 PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
1123 /* @GPIO(20): pcie_1l_1_pereset */
1124 PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
1125 /* @GPIO(21): pwm1 */
1126 PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
1127 /* @GPIO(22,23) spi0_wp_hold */
1128 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
1129 /* @GPIO(24,25,26,27) spi0 */
1130 PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
1131 /* @GPIO(28,29,30,31) spi1 */
1132 PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
1133 /* @GPIO(32,33,34,35) spi2 */
1134 PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
1135 /* @GPIO(36,37) spi2_wp_hold */
1136 PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
1137 /* @GPIO(22,23,24,25,26,27) snfi */
1138 PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
1139 /* @GPIO(22,23) tops_uart0_0 */
1140 PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
1141 /* @GPIO(28,29,30,31) uart2_0 */
1142 PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
1143 /* @GPIO(32,33,34,35) uart1_0 */
1144 PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
1145 /* @GPIO(32,33,34,35) uart2_1 */
1146 PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
1147 /* @GPIO(28) net_wo0_uart_txd_0 */
1148 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
1149 /* @GPIO(29) net_wo1_uart_txd_0 */
1150 PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
1151 /* @GPIO(30) net_wo2_uart_txd_0 */
1152 PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
1153 /* @GPIO(28,29) tops_uart1_0 */
1154 PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
1155 /* @GPIO(30,31) tops_uart0_1 */
1156 PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
1157 /* @GPIO(36,37) tops_uart1_1 */
1158 PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
1159 /* @GPIO(32,33,34,35,36) udi */
1160 PINCTRL_PIN_GROUP("udi", mt7988_udi),
1161 /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */
1162 PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
developer7d52c342022-11-03 11:46:34 +0800[diff] [blame]1163 /* @GPIO(32,33,34,35,36,37) sdcard */
1164 PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1165 /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */
1166 PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
1167 /* @GPIO(28,29) 2p5g_ext_mdio */
1168 PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
1169 /* @GPIO(30,31) gbe_ext_mdio */
1170 PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
developerd9283a42022-10-24 14:30:14 +0800[diff] [blame]1171 /* @GPIO(50,51,52,53,54) i2s */
1172 PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
1173 /* @GPIO(50,51,52,53) pcm */
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1174 PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
1175 /* @GPIO(55,56) uart0 */
1176 PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
1177 /* @GPIO(55,56) tops_uart0_2 */
1178 PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
1179 /* @GPIO(50,51,52,53) uart2_2 */
1180 PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
1181 /* @GPIO(50,51,52,53,54) wo0_jtag */
1182 PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
1183 /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */
1184 PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
1185 /* @GPIO(50,51,52,53,54) wo2_jtag */
1186 PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
1187 /* @GPIO(57) pwm0 */
1188 PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
1189 /* @GPIO(58,59,60,61,62) jtag */
1190 PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
1191 /* @GPIO(58,59,60,61,62) tops_jtag0_1 */
1192 PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
1193 /* @GPIO(58,59,60,61) uart2_3 */
1194 PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
1195 /* @GPIO(58,59,60,61) uart1_1 */
1196 PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1197 /* @GPIO(58,59,60,61) gbe_led1 */
1198 PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1),
1199 /* @GPIO(62) 2p5gbe_led1 */
1200 PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
1201 /* @GPIO(64,65,66,67) gbe_led0 */
1202 PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0),
1203 /* @GPIO(68) 2p5gbe_led0 */
1204 PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
1205 /* @GPIO(63) drv_vbus_p1 */
1206 PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
1207 /* @GPIO(63) pcie_clk_req_n2_1 */
1208 PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
1209 /* @GPIO(69, 70) mdc_mdio1 */
1210 PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
1211 /* @GPIO(69, 70) i2c1_2 */
1212 PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]1213 /* @GPIO(69) pwm6 */
1214 PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1215 /* @GPIO(70) pwm7 */
1216 PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
1217 /* @GPIO(69,70) i2c2_0 */
1218 PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
1219 /* @GPIO(71,72) i2c2_1 */
1220 PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
1221 /* @GPIO(73) pcie_2l_1_pereset */
1222 PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
1223 /* @GPIO(74) pcie_1l_0_pereset */
1224 PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
1225 /* @GPIO(75) pcie_wake_n1_0 */
1226 PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
1227 /* @GPIO(76) pcie_clk_req_n1 */
1228 PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
1229 /* @GPIO(77) pcie_wake_n2_0 */
1230 PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
1231 /* @GPIO(78) pcie_clk_req_n2_0 */
1232 PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
1233 /* @GPIO(79) drv_vbus */
1234 PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
1235 /* @GPIO(79) pcie_wake_n2_1 */
1236 PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
1237 /* @GPIO(80,81,82,83) uart1_2 */
1238 PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]1239 /* @GPIO(80) pwm2 */
1240 PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
1241 /* @GPIO(81) pwm3 */
1242 PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
1243 /* @GPIO(82) pwm4 */
1244 PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
1245 /* @GPIO(83) pwm5 */
1246 PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1247 /* @GPIO(80) net_wo0_uart_txd_0 */
1248 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
1249 /* @GPIO(81) net_wo1_uart_txd_0 */
1250 PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
1251 /* @GPIO(82) net_wo2_uart_txd_0 */
1252 PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
1253 /* @GPIO(80,81) tops_uart1_2 */
1254 PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
1255 /* @GPIO(80) net_wo0_uart_txd_1 */
1256 PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
1257 /* @GPIO(81) net_wo1_uart_txd_1 */
1258 PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
1259 /* @GPIO(82) net_wo2_uart_txd_1 */
1260 PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
1261};
1262
1263/* Joint those groups owning the same capability in user point of view which
1264 * allows that people tend to use through the device tree.
1265 */
1266static const char * const mt7988_jtag_groups[] = {
1267 "tops_jtag0_0", "wo0_jtag", "wo1_jtag",
1268 "wo2_jtag", "jtag", "tops_jtag0_1",
1269};
1270static const char * const mt7988_int_usxgmii_groups[] = {
1271 "int_usxgmii",
1272};
1273static const char * const mt7988_pwm_groups[] = {
developerbce0da02022-10-28 11:07:02 +0800[diff] [blame]1274 "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7"
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1275};
1276static const char * const mt7988_dfd_groups[] = {
1277 "dfd",
1278};
1279static const char * const mt7988_i2c_groups[] = {
1280 "xfi_phy0_i2c0",
1281 "xfi_phy1_i2c0",
1282 "xfi_phy_pll_i2c0",
1283 "xfi_phy_pll_i2c1",
1284 "i2c0_0",
1285 "i2c1_sfp",
1286 "xfi_pextp_phy0_i2c",
1287 "xfi_pextp_phy1_i2c",
1288 "i2c0_1",
1289 "u30_phy_i2c0",
1290 "u32_phy_i2c0",
1291 "xfi_phy0_i2c1",
1292 "xfi_phy1_i2c1",
1293 "xfi_phy_pll_i2c2",
1294 "i2c1_0",
1295 "u30_phy_i2c1",
1296 "u32_phy_i2c1",
1297 "xfi_phy_pll_i2c3",
1298 "sgmii0_i2c",
1299 "sgmii1_i2c",
1300 "i2c1_2",
1301 "i2c2_0",
1302 "i2c2_1",
1303};
1304static const char * const mt7988_ethernet_groups[] = {
1305 "mdc_mdio0",
1306 "2p5g_ext_mdio",
1307 "gbe_ext_mdio",
1308 "mdc_mdio1",
1309};
1310static const char * const mt7988_pcie_groups[] = {
1311 "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0",
1312 "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c",
1313 "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c",
1314 "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset",
1315 "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset",
1316 "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1",
1317 "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1",
1318 "pcie_clk_req_n0_1"
1319};
1320static const char * const mt7988_pmic_groups[] = {
1321 "pmic",
1322};
1323static const char * const mt7988_wdt_groups[] = {
1324 "watchdog",
1325};
1326static const char * const mt7988_spi_groups[] = {
1327 "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
1328};
developer7d52c342022-11-03 11:46:34 +0800[diff] [blame]1329static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1330 "emmc_51" };
1331static const char * const mt7988_uart_groups[] = {
1332 "uart2",
1333 "tops_uart0_0",
1334 "uart2_0",
1335 "uart1_0",
1336 "uart2_1",
1337 "net_wo0_uart_txd_0",
1338 "net_wo1_uart_txd_0",
1339 "net_wo2_uart_txd_0",
1340 "tops_uart1_0",
1341 "ops_uart0_1",
1342 "ops_uart1_1",
1343 "uart0",
1344 "tops_uart0_2",
1345 "uart1_1",
1346 "uart2_3",
1347 "uart1_2",
1348 "tops_uart1_2",
1349 "net_wo0_uart_txd_1",
1350 "net_wo1_uart_txd_1",
1351 "net_wo2_uart_txd_1",
1352};
1353static const char * const mt7988_udi_groups[] = {
1354 "udi",
1355};
developerd9283a42022-10-24 14:30:14 +0800[diff] [blame]1356static const char * const mt7988_audio_groups[] = {
1357 "i2s", "pcm",
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1358};
1359static const char * const mt7988_led_groups[] = {
1360 "gbe_led1", "2p5gbe_led1", "gbe_led0",
1361 "2p5gbe_led0", "wf5g_led0", "wf5g_led1",
1362};
1363static const char * const mt7988_usb_groups[] = {
1364 "drv_vbus",
1365 "drv_vbus_p1",
1366};
1367
1368static const struct function_desc mt7988_functions[] = {
developerd9283a42022-10-24 14:30:14 +0800[diff] [blame]1369 { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1370 { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
1371 { "int_usxgmii", mt7988_int_usxgmii_groups,
1372 ARRAY_SIZE(mt7988_int_usxgmii_groups) },
1373 { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) },
1374 { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) },
1375 { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) },
1376 { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
1377 { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
1378 { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
1379 { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
1380 { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) },
1381 { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
1382 { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
1383 { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1384 { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
1385 { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
1386};
1387
1388static const struct mtk_eint_hw mt7988_eint_hw = {
1389 .port_mask = 7,
1390 .ports = 7,
1391 .ap_num = ARRAY_SIZE(mt7988_pins),
1392 .db_cnt = 16,
1393};
1394
1395static const char * const mt7988_pinctrl_register_base_names[] = {
1396 "gpio_base", "iocfg_tr_base", "iocfg_br_base",
1397 "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
1398};
1399
1400static struct mtk_pin_soc mt7988_data = {
1401 .reg_cal = mt7988_reg_cals,
1402 .pins = mt7988_pins,
1403 .npins = ARRAY_SIZE(mt7988_pins),
1404 .grps = mt7988_groups,
1405 .ngrps = ARRAY_SIZE(mt7988_groups),
1406 .funcs = mt7988_functions,
1407 .nfuncs = ARRAY_SIZE(mt7988_functions),
1408 .eint_hw = &mt7988_eint_hw,
1409 .gpio_m = 0,
1410 .ies_present = false,
1411 .base_names = mt7988_pinctrl_register_base_names,
1412 .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
1413 .bias_disable_set = mtk_pinconf_bias_disable_set,
1414 .bias_disable_get = mtk_pinconf_bias_disable_get,
1415 .bias_set = mtk_pinconf_bias_set,
1416 .bias_get = mtk_pinconf_bias_get,
1417 .drive_set = mtk_pinconf_drive_set_rev1,
1418 .drive_get = mtk_pinconf_drive_get_rev1,
1419 .adv_pull_get = mtk_pinconf_adv_pull_get,
1420 .adv_pull_set = mtk_pinconf_adv_pull_set,
1421};
1422
1423static const struct of_device_id mt7988_pinctrl_of_match[] = {
1424 {
1425 .compatible = "mediatek,mt7988-pinctrl",
1426 },
1427 {}
1428};
1429
1430static int mt7988_pinctrl_probe(struct platform_device *pdev)
1431{
1432 return mtk_moore_pinctrl_probe(pdev, &mt7988_data);
1433}
1434
1435static struct platform_driver mt7988_pinctrl_driver = {
1436 .driver = {
1437 .name = "mt7988-pinctrl",
1438 .of_match_table = mt7988_pinctrl_of_match,
1439 },
1440 .probe = mt7988_pinctrl_probe,
1441};
1442
1443static int __init mt7988_pinctrl_init(void)
1444{
1445 return platform_driver_register(&mt7988_pinctrl_driver);
1446}
1447arch_initcall(mt7988_pinctrl_init);