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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 76c9bcc2e2b084ba51a1dc0b4222e4f6e8813acb / . / target / linux / mediatek / files-5.4 / drivers / clk / mediatek / clk-mt7981.c
blob: 471fef35f68699ed0c0697f0c7ce02e1029882f1 [file] [log] [blame]
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]1/*
2 * Copyright (c) 2021 MediaTek Inc.
3 * Author: Wenzhen Yu<Yenzhen.Yu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/slab.h>
20#include <linux/mfd/syscon.h>
21
22#include "clk-mtk.h"
23#include "clk-gate.h"
24#include "clk-mux.h"
25
26#include <dt-bindings/clock/mt7981-clk.h>
27
28static DEFINE_SPINLOCK(mt7981_clk_lock);
29
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]30static const struct mtk_fixed_factor infra_divs[] __initconst = {
31 FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", "csw_f26m_sel", 1, 1),
32 FACTOR(CK_INFRA_UART, "infra_uart", "uart_sel", 1, 1),
33 FACTOR(CK_INFRA_ISPI0, "infra_ispi0", "spi_sel", 1, 1),
34 FACTOR(CK_INFRA_I2C, "infra_i2c", "i2c_sel", 1, 1),
35 FACTOR(CK_INFRA_ISPI1, "infra_ispi1", "spim_mst_sel", 1, 1),
36 FACTOR(CK_INFRA_PWM, "infra_pwm", "pwm_sel", 1, 1),
37 FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
38 FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", "cb_rtc_32p7k", 1, 1),
39 FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", "pextp_tl_ck_sel", 1, 1),
40 FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", "infra_pwm_bsel", 1, 1),
41 FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", "infra_pwm1_sel", 1, 1),
42 FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", "infra_pwm2_sel", 1, 1),
43 FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", "sysaxi", 1, 1),
44 FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", "infra_133m_hck", 1, 1),
45 FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", "aud_l", 1, 1),
46 FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", "a1sys", 1, 1),
47 FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", "a_tuner", 1, 1),
48 FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", "i2c_bck", 1, 1),
49 FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", "infra_uart0_sel", 1, 1),
50 FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", "infra_uart1_sel", 1, 1),
51 FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", "infra_uart2_sel", 1, 1),
52 FACTOR(CK_INFRA_NFI_CK, "infra_nfi", "nfi1x", 1, 1),
53 FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", "spinfi_bck", 1, 1),
54 FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", "infra_spi0_sel", 1, 1),
55 FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", "infra_spi1_sel", 1, 1),
56 FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", "infra_spi2_sel", 1, 1),
57 FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", "cb_rtc_32k", 1, 1),
58 FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", "emmc_400m", 1, 1),
59 FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", "emmc_208m", 1, 1),
60 FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", "sysaxi", 1, 1),
61 FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", "sysaxi", 1, 1),
62 FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", "u2u3_sys", 1, 1),
63 FACTOR(CK_INFRA_USB_CK, "infra_usb", "u2u3_ref", 1, 1),
64 FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", "u2u3_xhci", 1, 1),
65 FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", "pextp_tl", 1, 1),
66 FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", "csw_f26m", 1, 1),
67 FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", "sysaxi", 1, 1),
68};
69
70static const struct mtk_fixed_factor top_divs[] __initconst = {
71 FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
72 FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
73 FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
74 FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
75 FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
76 FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
77 FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
78 FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
79 FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
80 FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
81 FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
82 FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
83 FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
84 FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
85 FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
86 FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
87 FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
88 FACTOR(CK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
89 FACTOR(CK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
90 FACTOR(CK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
91 FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
92 FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
93 FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
94 FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
95 FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
96 FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
97 FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
98 FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
99 FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
100 FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
101 FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
102 FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
103 FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
104 FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
105 FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
106 FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
107 FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
108 FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
109 FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
developer705fe872022-01-10 15:59:07 +0800[diff] [blame]110 FACTOR(CK_TOP_FAUD, "faud", "aud_sel", 1, 1),
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]111 FACTOR(CK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
112 FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
113 FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
114 FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
115 FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
116 FACTOR(CK_TOP_SPI, "spi", "spi_sel", 1, 1),
117 FACTOR(CK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
118 FACTOR(CK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
119 FACTOR(CK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
120 FACTOR(CK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
121 FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
122 FACTOR(CK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
123 FACTOR(CK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
124 FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
125 FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
126 FACTOR(CK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
127 FACTOR(CK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
128 FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
129 FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
130 FACTOR(CK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
131 FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
132 FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
133 FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
134 FACTOR(CK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
135 FACTOR(CK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
136 FACTOR(CK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
137 FACTOR(CK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
138 FACTOR(CK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
139 FACTOR(CK_TOP_AUD, "aud", "faud", 1, 1),
140 FACTOR(CK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
141 FACTOR(CK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
142 FACTOR(CK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
143 FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
144 FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
145 FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
146 FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
147};
148
149static const char * const nfi1x_parents[] __initconst = {
150 "cb_cksq_40m",
151 "cb_mm_d4",
152 "net1_d8_d2",
153 "cb_net2_d6",
154 "cb_m_d4",
155 "cb_mm_d8",
156 "net1_d8_d4",
157 "cb_m_d8"
158};
159
160static const char * const spinfi_parents[] __initconst = {
161 "cksq_40m_d2",
162 "cb_cksq_40m",
163 "net1_d5_d4",
164 "cb_m_d4",
165 "cb_mm_d8",
166 "net1_d8_d4",
167 "mm_d6_d2",
168 "cb_m_d8"
169};
170
171static const char * const spi_parents[] __initconst = {
172 "cb_cksq_40m",
173 "cb_m_d2",
174 "cb_mm_d4",
175 "net1_d8_d2",
176 "cb_net2_d6",
177 "net1_d5_d4",
178 "cb_m_d4",
179 "net1_d8_d4"
180};
181
182static const char * const uart_parents[] __initconst = {
183 "cb_cksq_40m",
184 "cb_m_d8",
185 "m_d8_d2"
186};
187
188static const char * const pwm_parents[] __initconst = {
189 "cb_cksq_40m",
190 "net1_d8_d2",
191 "net1_d5_d4",
192 "cb_m_d4",
193 "m_d8_d2",
194 "cb_rtc_32k"
195};
196
197static const char * const i2c_parents[] __initconst = {
198 "cb_cksq_40m",
199 "net1_d5_d4",
200 "cb_m_d4",
201 "net1_d8_d4"
202};
203
204static const char * const pextp_tl_ck_parents[] __initconst = {
205 "cb_cksq_40m",
206 "net1_d5_d4",
207 "cb_m_d4",
208 "cb_rtc_32k"
209};
210
211static const char * const emmc_208m_parents[] __initconst = {
212 "cb_cksq_40m",
213 "cb_m_d2",
214 "cb_net2_d4",
215 "cb_apll2_196m",
216 "cb_mm_d4",
217 "net1_d8_d2",
218 "cb_mm_d6"
219};
220
221static const char * const emmc_400m_parents[] __initconst = {
222 "cb_cksq_40m",
223 "cb_net2_d2",
224 "cb_mm_d2",
225 "cb_net2_d2"
226};
227
228static const char * const csw_f26m_parents[] __initconst = {
229 "cksq_40m_d2",
230 "m_d8_d2"
231};
232
233static const char * const dramc_md32_parents[] __initconst = {
234 "cb_cksq_40m",
235 "cb_m_d2",
236 "cb_wedmcu_208m"
237};
238
239static const char * const sysaxi_parents[] __initconst = {
240 "cb_cksq_40m",
241 "net1_d8_d2"
242};
243
244static const char * const sysapb_parents[] __initconst = {
245 "cb_cksq_40m",
246 "m_d3_d2"
247};
248
249static const char * const arm_db_main_parents[] __initconst = {
250 "cb_cksq_40m",
251 "cb_net2_d6"
252};
253
254static const char * const ap2cnn_host_parents[] __initconst = {
255 "cb_cksq_40m",
256 "net1_d8_d4"
257};
258
259static const char * const netsys_parents[] __initconst = {
260 "cb_cksq_40m",
261 "cb_mm_d2"
262};
263
264static const char * const netsys_500m_parents[] __initconst = {
265 "cb_cksq_40m",
266 "cb_net1_d5"
267};
268
269static const char * const netsys_mcu_parents[] __initconst = {
270 "cb_cksq_40m",
271 "cb_mm_720m",
272 "cb_net1_d4",
273 "cb_net1_d5",
274 "cb_m_416m"
275};
276
277static const char * const netsys_2x_parents[] __initconst = {
278 "cb_cksq_40m",
279 "cb_net2_800m",
280 "cb_mm_720m"
281};
282
283static const char * const sgm_325m_parents[] __initconst = {
284 "cb_cksq_40m",
285 "cb_sgm_325m"
286};
287
288static const char * const sgm_reg_parents[] __initconst = {
289 "cb_cksq_40m",
290 "cb_net2_d4"
291};
292
293static const char * const eip97b_parents[] __initconst = {
294 "cb_cksq_40m",
295 "cb_net1_d5",
296 "cb_m_416m",
297 "cb_mm_d2",
298 "net1_d5_d2"
299};
300
301static const char * const aud_parents[] __initconst = {
302 "cb_cksq_40m",
303 "cb_apll2_196m"
304};
305
306static const char * const a1sys_parents[] __initconst = {
307 "cb_cksq_40m",
308 "apll2_d4"
309};
310
311static const char * const aud_l_parents[] __initconst = {
312 "cb_cksq_40m",
313 "cb_apll2_196m",
314 "m_d8_d2"
315};
316
317static const char * const a_tuner_parents[] __initconst = {
318 "cb_cksq_40m",
319 "apll2_d4",
320 "m_d8_d2"
321};
322
323static const char * const u2u3_parents[] __initconst = {
324 "cb_cksq_40m",
325 "m_d8_d2"
326};
327
328static const char * const u2u3_sys_parents[] __initconst = {
329 "cb_cksq_40m",
330 "net1_d5_d4"
331};
332
333static const char * const usb_frmcnt_parents[] __initconst = {
334 "cb_cksq_40m",
335 "cb_mm_d3_d5"
336};
337
338static const struct mtk_mux top_muxes[] = {
339 /* CLK_CFG_0 */
340 MUX_GATE_CLR_SET_UPD(CK_TOP_NFI1X_SEL, "nfi1x_sel",
341 nfi1x_parents, 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
342 MUX_GATE_CLR_SET_UPD(CK_TOP_SPINFI_SEL, "spinfi_sel",
343 spinfi_parents, 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
344 MUX_GATE_CLR_SET_UPD(CK_TOP_SPI_SEL, "spi_sel",
345 spi_parents, 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
346 MUX_GATE_CLR_SET_UPD(CK_TOP_SPIM_MST_SEL, "spim_mst_sel",
347 spi_parents, 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
348 /* CLK_CFG_1 */
349 MUX_GATE_CLR_SET_UPD(CK_TOP_UART_SEL, "uart_sel",
350 uart_parents, 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
351 MUX_GATE_CLR_SET_UPD(CK_TOP_PWM_SEL, "pwm_sel",
352 pwm_parents, 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
353 MUX_GATE_CLR_SET_UPD(CK_TOP_I2C_SEL, "i2c_sel",
354 i2c_parents, 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
355 MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
356 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
357 /* CLK_CFG_2 */
358 MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
359 emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x1C0, 8),
360 MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
361 emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x1C0, 9),
362 MUX_GATE_CLR_SET_UPD(CK_TOP_F26M_SEL, "csw_f26m_sel",
363 csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, 0x1C0, 10),
364 MUX_GATE_CLR_SET_UPD(CK_TOP_DRAMC_SEL, "dramc_sel",
365 csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
366 /* CLK_CFG_3 */
367 MUX_GATE_CLR_SET_UPD(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
368 dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, 7, 0x1C0, 12),
369 MUX_GATE_CLR_SET_UPD(CK_TOP_SYSAXI_SEL, "sysaxi_sel",
370 sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, 0x1C0, 13),
371 MUX_GATE_CLR_SET_UPD(CK_TOP_SYSAPB_SEL, "sysapb_sel",
372 sysapb_parents, 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14),
373 MUX_GATE_CLR_SET_UPD(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
374 arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
375 /* CLK_CFG_4 */
376 MUX_GATE_CLR_SET_UPD(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
377 ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
378 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_SEL, "netsys_sel",
379 netsys_parents, 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
380 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
381 netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
382 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
383 netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
384 /* CLK_CFG_5 */
385 MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
386 netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 0x1C0, 20),
387 MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_325M_SEL, "sgm_325m_sel",
388 sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 0x1C0, 21),
389 MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_REG_SEL, "sgm_reg_sel",
390 sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
391 MUX_GATE_CLR_SET_UPD(CK_TOP_EIP97B_SEL, "eip97b_sel",
392 eip97b_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
393 /* CLK_CFG_6 */
394 MUX_GATE_CLR_SET_UPD(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
395 csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
396 MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_SEL, "aud_sel",
397 aud_parents, 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
398 MUX_GATE_CLR_SET_UPD(CK_TOP_A1SYS_SEL, "a1sys_sel",
399 a1sys_parents, 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
400 MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_L_SEL, "aud_l_sel",
401 aud_l_parents, 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
402 /* CLK_CFG_7 */
403 MUX_GATE_CLR_SET_UPD(CK_TOP_A_TUNER_SEL, "a_tuner_sel",
404 a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, 0x1C0, 28),
405 MUX_GATE_CLR_SET_UPD(CK_TOP_U2U3_SEL, "u2u3_sel",
406 u2u3_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
407 MUX_GATE_CLR_SET_UPD(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
408 u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30),
409 MUX_GATE_CLR_SET_UPD(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
410 u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
411 /* CLK_CFG_8 */
412 MUX_GATE_CLR_SET_UPD(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
413 usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1),
414};
415
416static const char * const infra_uart0_parents[] __initconst = {
417 "infra_ck_f26m",
418 "infra_uart"
419};
420
421static const char * const infra_spi0_parents[] __initconst = {
developer51e91772021-12-13 15:35:41 +0800[diff] [blame]422 "infra_i2c",
423 "infra_ispi0"
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]424};
425
426static const char * const infra_spi1_parents[] __initconst = {
developer51e91772021-12-13 15:35:41 +0800[diff] [blame]427 "infra_i2c",
428 "infra_ispi1"
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]429};
430
431static const char * const infra_pwm1_parents[] __initconst = {
developerba7333b2021-12-01 13:49:36 +0800[diff] [blame]432 "infra_pwm"
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]433};
434
435static const char * const infra_pwm_bsel_parents[] __initconst = {
436 "infra_ck_f32k",
437 "infra_ck_f26m",
438 "infra_66m_mck",
439 "infra_pwm"
440};
441
442static const char * const infra_pcie_parents[] __initconst = {
developer51e91772021-12-13 15:35:41 +0800[diff] [blame]443 "infra_ck_f32k",
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]444 "infra_ck_f26m",
developer51e91772021-12-13 15:35:41 +0800[diff] [blame]445 "cb_cksq_40m",
446 "infra_pcie"
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]447};
448
449static const struct mtk_mux infra_muxes[] = {
450 /* MODULE_CLK_SEL_0 */
451 MUX_GATE_CLR_SET_UPD(CK_INFRA_UART0_SEL, "infra_uart0_sel",
452 infra_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
453 MUX_GATE_CLR_SET_UPD(CK_INFRA_UART1_SEL, "infra_uart1_sel",
454 infra_uart0_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
455 MUX_GATE_CLR_SET_UPD(CK_INFRA_UART2_SEL, "infra_uart2_sel",
456 infra_uart0_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
457 MUX_GATE_CLR_SET_UPD(CK_INFRA_SPI0_SEL, "infra_spi0_sel",
458 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
459 MUX_GATE_CLR_SET_UPD(CK_INFRA_SPI1_SEL, "infra_spi1_sel",
460 infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
461 MUX_GATE_CLR_SET_UPD(CK_INFRA_SPI2_SEL, "infra_spi2_sel",
462 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
463 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM1_SEL, "infra_pwm1_sel",
developerba7333b2021-12-01 13:49:36 +0800[diff] [blame]464 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, -1, -1, -1),
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]465 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM2_SEL, "infra_pwm2_sel",
developerba7333b2021-12-01 13:49:36 +0800[diff] [blame]466 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, -1, -1, -1),
467 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM3_SEL, "infra_pwm3_sel",
468 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, -1, -1, -1),
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]469 MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_BSEL, "infra_pwm_bsel",
470 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, 2, -1, -1, -1),
471 /* MODULE_CLK_SEL_1 */
472 MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_SEL, "infra_pcie_sel",
473 infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, -1, -1),
474};
475
developer705fe872022-01-10 15:59:07 +0800[diff] [blame]476static struct mtk_composite top_aud_divs[] = {
477 DIV_GATE(CK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
478 0x0420, 0, 0x0420, 8, 8),
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]479};
480
481static const struct mtk_gate_regs infra0_cg_regs = {
482 .set_ofs = 0x40,
483 .clr_ofs = 0x44,
484 .sta_ofs = 0x48,
485};
486
487static const struct mtk_gate_regs infra1_cg_regs = {
488 .set_ofs = 0x50,
489 .clr_ofs = 0x54,
490 .sta_ofs = 0x58,
491};
492
493static const struct mtk_gate_regs infra2_cg_regs = {
494 .set_ofs = 0x60,
495 .clr_ofs = 0x64,
496 .sta_ofs = 0x68,
497};
498
499#define GATE_INFRA0(_id, _name, _parent, _shift) { \
500 .id = _id, \
501 .name = _name, \
502 .parent_name = _parent, \
503 .regs = &infra0_cg_regs, \
504 .shift = _shift, \
505 .ops = &mtk_clk_gate_ops_setclr, \
506 }
507
508#define GATE_INFRA1(_id, _name, _parent, _shift) { \
509 .id = _id, \
510 .name = _name, \
511 .parent_name = _parent, \
512 .regs = &infra1_cg_regs, \
513 .shift = _shift, \
514 .ops = &mtk_clk_gate_ops_setclr, \
515 }
516
517#define GATE_INFRA2(_id, _name, _parent, _shift) { \
518 .id = _id, \
519 .name = _name, \
520 .parent_name = _parent, \
521 .regs = &infra2_cg_regs, \
522 .shift = _shift, \
523 .ops = &mtk_clk_gate_ops_setclr, \
524 }
525
526static const struct mtk_gate infra_clks[] __initconst = {
527 /* INFRA0 */
528 GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
529 GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
530 GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bck", 2),
531 GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm_ck1", 3),
532 GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm_ck2", 4),
533 GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", "infra_133m_hck", 6),
534 GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", "infra_66m_phck", 8),
535 GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", "infra_ck_f26m", 9),
536 GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", "infra_faud_l", 10),
537 GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", "infra_faud_aud", 11),
538 GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "infra_faud_eg2", 13),
539 GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "infra_ck_f26m", 14),
540 GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
541 GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
542 GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
543 GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", "infra_ck_f26m", 25),
developerba7333b2021-12-01 13:49:36 +0800[diff] [blame]544 GATE_INFRA0(CK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]545 /* INFRA1 */
546 GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", "infra_ck_f26m", 0),
547 GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", "infra_i2cs", 1),
548 GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", "infra_mux_uart0", 2),
549 GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", "infra_mux_uart1", 3),
550 GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", "infra_mux_uart2", 4),
551 GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", "infra_mux_spi2", 6),
552 GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
553 GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", "infra_nfi", 8),
554 GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", "infra_spinfi", 9),
555 GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
556 GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", "infra_mux_spi0", 11),
557 GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", "infra_mux_spi1", 12),
558 GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", 13),
559 GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", 14),
560 GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", "infra_rtc_32k", 15),
561 GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", "infra_fmsdc", 16),
562 GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "infra_fmsdc_hck", 17),
563 GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "infra_peri_133m", 18),
564 GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_66m_phck", 19),
565 GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m", 20),
566 GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
567 GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "infra_nfi", 23),
568 GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "infra_133m_mck", 25),
569 GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
570 /* INFRA2 */
571 GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", "infra_133m_phck", 0),
572 GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_66m_phck", 1),
573 GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "infra_usb_sys", 2),
574 GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", "infra_usb", 3),
575 GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", "infra_pcie_mux", 12),
developere87be172021-12-06 11:31:16 +0800[diff] [blame]576 GATE_INFRA2(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", 13),
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]577 GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", "infra_f26m_ck0", 14),
578 GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", "infra_133m_phck", 15),
579};
580
581static const struct mtk_gate_regs sgmii0_cg_regs = {
582 .set_ofs = 0xE4,
583 .clr_ofs = 0xE4,
584 .sta_ofs = 0xE4,
585};
586
587#define GATE_SGMII0(_id, _name, _parent, _shift) { \
588 .id = _id, \
589 .name = _name, \
590 .parent_name = _parent, \
591 .regs = &sgmii0_cg_regs, \
592 .shift = _shift, \
593 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
594 }
595
596static const struct mtk_gate sgmii0_clks[] __initconst = {
597 GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
598 GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
599 GATE_SGMII0(CK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
600 GATE_SGMII0(CK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
601};
602
603static const struct mtk_gate_regs sgmii1_cg_regs = {
604 .set_ofs = 0xE4,
605 .clr_ofs = 0xE4,
606 .sta_ofs = 0xE4,
607};
608
609#define GATE_SGMII1(_id, _name, _parent, _shift) { \
610 .id = _id, \
611 .name = _name, \
612 .parent_name = _parent, \
613 .regs = &sgmii1_cg_regs, \
614 .shift = _shift, \
615 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
616 }
617
618static const struct mtk_gate sgmii1_clks[] __initconst = {
619 GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
620 GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
621 GATE_SGMII1(CK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
622 GATE_SGMII1(CK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
623};
624
625static const struct mtk_gate_regs eth_cg_regs = {
626 .set_ofs = 0x30,
627 .clr_ofs = 0x30,
628 .sta_ofs = 0x30,
629};
630
631#define GATE_ETH(_id, _name, _parent, _shift) { \
632 .id = _id, \
633 .name = _name, \
634 .parent_name = _parent, \
635 .regs = &eth_cg_regs, \
636 .shift = _shift, \
637 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
638 }
639
640static const struct mtk_gate eth_clks[] __initconst = {
641 GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
642 GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
643 GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
644 GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
645};
646
647#define MT7981_PLL_FMAX (2500UL * MHZ)
648
649#define CON0_MT7981_RST_BAR BIT(27)
650
651#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
652 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
653 _pcw_shift, _div_table, _parent_name) { \
654 .id = _id, \
655 .name = _name, \
656 .reg = _reg, \
657 .pwr_reg = _pwr_reg, \
658 .en_mask = _en_mask, \
659 .flags = _flags, \
660 .rst_bar_mask = CON0_MT7981_RST_BAR, \
661 .fmax = MT7981_PLL_FMAX, \
662 .pcwbits = _pcwbits, \
663 .pd_reg = _pd_reg, \
664 .pd_shift = _pd_shift, \
665 .tuner_reg = _tuner_reg, \
666 .pcw_reg = _pcw_reg, \
667 .pcw_shift = _pcw_shift, \
668 .div_table = _div_table, \
669 .parent_name = _parent_name, \
670 }
671
672#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
673 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
674 _pcw_shift, _parent_name) \
675 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
676 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
677 NULL, _parent_name)
678
679static const struct mtk_pll_data plls[] = {
680 PLL(CK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
681 0, 32, 0x0200, 4, 0, 0x0204, 0, "clkxtal"),
682 PLL(CK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001,
683 0, 32, 0x0210, 4, 0, 0x0214, 0, "clkxtal"),
684 PLL(CK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001,
685 0, 32, 0x0220, 4, 0, 0x0224, 0, "clkxtal"),
686 PLL(CK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001,
687 0, 32, 0x0230, 4, 0, 0x0234, 0, "clkxtal"),
688 PLL(CK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001,
689 0, 32, 0x0240, 4, 0, 0x0244, 0, "clkxtal"),
690 PLL(CK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001,
691 0, 32, 0x0250, 4, 0, 0x0254, 0, "clkxtal"),
692 PLL(CK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001,
693 0, 32, 0x0260, 4, 0, 0x0264, 0, "clkxtal"),
694 PLL(CK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001,
695 0, 32, 0x0278, 4, 0, 0x027C, 0, "clkxtal"),
696};
697
698static struct clk_onecell_data *mt7981_top_clk_data __initdata;
699static struct clk_onecell_data *mt7981_pll_clk_data __initdata;
700
701static void __init mtk_clk_enable_critical(void)
702{
703 if (!mt7981_top_clk_data || !mt7981_pll_clk_data)
704 return;
705
706 clk_prepare_enable(mt7981_pll_clk_data->clks[CK_APMIXED_ARMPLL]);
707 clk_prepare_enable(mt7981_top_clk_data->clks[CK_TOP_SYSAXI_SEL]);
708 clk_prepare_enable(mt7981_top_clk_data->clks[CK_TOP_SYSAPB_SEL]);
709 clk_prepare_enable(mt7981_top_clk_data->clks[CK_TOP_DRAMC_SEL]);
710 clk_prepare_enable(mt7981_top_clk_data->clks[CK_TOP_DRAMC_MD32_SEL]);
711 clk_prepare_enable(mt7981_top_clk_data->clks[CK_TOP_F26M_SEL]);
712}
713
714static void __init mtk_infracfg_init(struct device_node *node)
715{
716 int r;
717
718
719 mt7981_top_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
720
721 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), mt7981_top_clk_data);
722
723 r = of_clk_add_provider(node, of_clk_src_onecell_get, mt7981_top_clk_data);
724
725 if (r)
726 pr_err("%s(): could not register clock provider: %d\n",
727 __func__, r);
728
729 mtk_clk_enable_critical();
730}
731CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt7981-infracfg", mtk_infracfg_init);
732
733static void __init mtk_topckgen_init(struct device_node *node)
734{
735 int r;
736 void __iomem *base;
737
738 base = of_iomap(node, 0);
739 if (!base) {
740 pr_err("%s(): ioremap failed\n", __func__);
741 return;
742 }
743
744 mt7981_top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
745
746 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), mt7981_top_clk_data);
developer0fd9b1c2021-11-05 13:44:44 +0800[diff] [blame]747 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, &mt7981_clk_lock, mt7981_top_clk_data);
developer705fe872022-01-10 15:59:07 +0800[diff] [blame]748 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
749 base, &mt7981_clk_lock, mt7981_top_clk_data);
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]750
751 r = of_clk_add_provider(node, of_clk_src_onecell_get, mt7981_top_clk_data);
752
753 if (r)
754 pr_err("%s(): could not register clock provider: %d\n",
755 __func__, r);
756
757 mtk_clk_enable_critical();
758}
759CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7981-topckgen", mtk_topckgen_init);
760
761static void __init mtk_infracfg_ao_init(struct device_node *node)
762{
763 struct clk_onecell_data *clk_data;
764 int r;
765 void __iomem *base;
766
767 base = of_iomap(node, 0);
768 if (!base) {
769 pr_err("%s(): ioremap failed\n", __func__);
770 return;
771 }
772
developerba7333b2021-12-01 13:49:36 +0800[diff] [blame]773 clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]774
developer0fd9b1c2021-11-05 13:44:44 +0800[diff] [blame]775 mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, &mt7981_clk_lock, clk_data);
developer6ec21762021-09-30 17:15:17 +0800[diff] [blame]776 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data);
777
778 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
779
780 if (r)
781 pr_err("%s(): could not register clock provider: %d\n",
782 __func__, r);
783}
784CLK_OF_DECLARE(mtk_infracfg_ao, "mediatek,mt7981-infracfg_ao", mtk_infracfg_ao_init);
785
786static void __init mtk_apmixedsys_init(struct device_node *node)
787{
788 int r;
789
790 mt7981_pll_clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
791
792 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), mt7981_pll_clk_data);
793
794 r = of_clk_add_provider(node, of_clk_src_onecell_get, mt7981_pll_clk_data);
795
796 if (r)
797 pr_err("%s(): could not register clock provider: %d\n",
798 __func__, r);
799
800 mtk_clk_enable_critical();
801}
802CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7981-apmixedsys", mtk_apmixedsys_init);
803
804static void __init mtk_sgmiisys_0_init(struct device_node *node)
805{
806 struct clk_onecell_data *clk_data;
807 int r;
808
809 clk_data = mtk_alloc_clk_data(CLK_SGMII0_NR_CLK);
810
811 mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), clk_data);
812
813 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
814
815 if (r)
816 pr_err("%s(): could not register clock provider: %d\n",
817 __func__, r);
818}
819CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0", mtk_sgmiisys_0_init);
820
821static void __init mtk_sgmiisys_1_init(struct device_node *node)
822{
823 struct clk_onecell_data *clk_data;
824 int r;
825
826 clk_data = mtk_alloc_clk_data(CLK_SGMII1_NR_CLK);
827
828 mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), clk_data);
829
830 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
831
832 if (r)
833 pr_err("%s(): could not register clock provider: %d\n",
834 __func__, r);
835}
836CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1", mtk_sgmiisys_1_init);
837
838static void __init mtk_ethsys_init(struct device_node *node)
839{
840 struct clk_onecell_data *clk_data;
841 int r;
842
843 clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
844
845 mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
846
847 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
848
849 if (r)
850 pr_err("%s(): could not register clock provider: %d\n",
851 __func__, r);
852}
853CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init);
854