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developer3abe1ad2022-01-24 11:13:32 +08001/* Copyright (C) 2021-2022 Mediatek Inc. */
2#ifndef __ATENL_H
3#define __ATENL_H
4
5#include <arpa/inet.h>
6#include <errno.h>
7#include <fcntl.h>
8#include <limits.h>
9#include <linux/nl80211.h>
10#include <net/if.h>
11#include <stdbool.h>
12#include <stdio.h>
13#include <stdlib.h>
14#include <unistd.h>
15
16#include "nl.h"
17#include "util.h"
18
19/* #define CONFIG_ATENL_DEBUG 1 */
20/* #define CONFIG_ATENL_DEBUG_VERBOSE 1 */
21#define BRIDGE_NAME "br-lan"
22#define ETH_P_RACFG 0x2880
23#define RACFG_PKT_MAX_SIZE 1600
24#define RACFG_HLEN 12
25#define RACFG_MAGIC_NO 0x18142880
26
27#define RACFG_CMD_TYPE_MASK GENMASK(14, 0)
28#define RACFG_CMD_TYPE_ETHREQ BIT(3)
29#define RACFG_CMD_TYPE_PLATFORM_MODULE GENMASK(4, 3)
30
31#define atenl_info(fmt, ...) printf(fmt, __VA_ARGS__)
32#define atenl_err(fmt, ...) fprintf(stderr, fmt, __VA_ARGS__)
33#ifdef CONFIG_ATENL_DEBUG
34#define atenl_dbg(fmt, ...) atenl_info(fmt, __VA_ARGS__)
35#else
36#define atenl_dbg(fmt, ...)
37#endif
38
39#define set_band_val(_an, _band, _field, _val) \
40 _an->anb[_band]._field = (_val)
41#define get_band_val(_an, _band, _field) \
42 (_an->anb[_band]._field)
43
44enum atenl_rf_mode {
45 ATENL_RF_MODE_NORMAL,
46 ATENL_RF_MODE_TEST,
47 ATENL_RF_MODE_ICAP,
48 ATENL_RF_MODE_ICAP_OVERLAP,
49
50 __ATENL_RF_MODE_MAX,
51};
52
53struct atenl_rx_stat {
54 u64 total;
55 u64 ok_cnt;
56 u64 err_cnt;
57 u64 len_mismatch;
58};
59
60struct atenl_band {
61 bool valid;
62 u8 phy_idx;
63 u8 cap;
64 u8 chainmask;
65
66 enum mt76_testmode_state cur_state;
67 s8 tx_power;
68 enum atenl_rf_mode rf_mode;
69
70 bool use_tx_time;
71
72 bool reset_tx_cnt;
73 bool reset_rx_cnt;
74
75 /* history */
76 struct atenl_rx_stat rx_stat;
77};
78
79#define MAX_BAND_NUM 4
80
81struct atenl {
82 struct atenl_band anb[MAX_BAND_NUM];
83 u16 chip_id;
84
85 u8 cur_band;
86
87 u8 mac_addr[ETH_ALEN];
88 bool unicast;
89 int sock_eth;
90 int pipefd[2];
91 int child_pid;
92
93 const char *mtd_part;
94 u32 mtd_offset;
95 u8 *eeprom_data;
96 int eeprom_fd;
97 u16 eeprom_size;
developer3abe1ad2022-01-24 11:13:32 +080098
99 bool cmd_mode;
100};
101
102struct atenl_cmd_hdr {
103 __be32 magic_no;
104 __be16 cmd_type;
105 __be16 cmd_id;
106 __be16 len;
107 __be16 seq;
108 u8 data[2048];
109} __attribute__((packed));
110
111enum atenl_cmd {
112 HQA_CMD_UNKNOWN,
113 HQA_CMD_LEGACY, /* legacy or deprecated */
114
115 HQA_CMD_OPEN_ADAPTER,
116 HQA_CMD_CLOSE_ADAPTER,
117 HQA_CMD_GET_CHIP_ID,
118 HQA_CMD_GET_SUB_CHIP_ID,
119 HQA_CMD_SET_TX_BW,
120 HQA_CMD_SET_TX_PKT_BW,
121 HQA_CMD_SET_TX_PRI_BW,
122 HQA_CMD_GET_TX_INFO,
123 HQA_CMD_SET_TX_PATH,
124 HQA_CMD_SET_TX_POWER,
125 HQA_CMD_SET_TX_POWER_MANUAL,
126 HQA_CMD_SET_RF_MODE,
127 HQA_CMD_SET_RX_PATH,
128 HQA_CMD_SET_RX_PKT_LEN,
129 HQA_CMD_SET_FREQ_OFFSET,
130 HQA_CMD_SET_TSSI,
131 HQA_CMD_SET_CFG,
132 HQA_CMD_SET_RU,
133 HQA_CMD_SET_BAND,
134 HQA_CMD_READ_MAC_BBP_REG,
135 HQA_CMD_READ_RF_REG,
136 HQA_CMD_READ_EEPROM_BULK,
137 HQA_CMD_READ_TEMPERATURE,
138 HQA_CMD_WRITE_MAC_BBP_REG,
139 HQA_CMD_WRITE_RF_REG,
140 HQA_CMD_WRITE_EEPROM_BULK,
141 HQA_CMD_WRITE_BUFFER_DONE,
142 HQA_CMD_GET_BAND,
143 HQA_CMD_GET_CFG,
144 HQA_CMD_GET_TX_POWER,
145 HQA_CMD_GET_TX_TONE_POWER,
146 HQA_CMD_GET_EFUSE_FREE_BLOCK,
147 HQA_CMD_GET_FREQ_OFFSET,
148 HQA_CMD_GET_FW_INFO,
149 HQA_CMD_GET_RX_INFO,
150 HQA_CMD_GET_RF_CAP,
151 HQA_CMD_CHECK_EFUSE_MODE,
152 HQA_CMD_CHECK_EFUSE_MODE_TYPE,
153 HQA_CMD_CHECK_EFUSE_MODE_NATIVE,
154 HQA_CMD_ANT_SWAP_CAP,
155 HQA_CMD_RESET_TX_RX_COUNTER,
156 HQA_CMD_CONTINUOUS_TX,
157
158 HQA_CMD_EXT,
159 HQA_CMD_ERR,
160
161 __HQA_CMD_MAX_NUM,
162};
163
164enum atenl_ext_cmd {
165 HQA_EXT_CMD_UNSPEC,
166
167 HQA_EXT_CMD_SET_CHANNEL,
168 HQA_EXT_CMD_SET_TX,
169 HQA_EXT_CMD_START_TX,
170 HQA_EXT_CMD_START_RX,
171 HQA_EXT_CMD_STOP_TX,
172 HQA_EXT_CMD_STOP_RX,
173 HQA_EXT_CMD_SET_TX_TIME_OPT,
174
175 HQA_EXT_CMD_OFF_CH_SCAN,
176
177 HQA_EXT_CMD_IBF_SET_VAL,
178 HQA_EXT_CMD_IBF_GET_STATUS,
179 HQA_EXT_CMD_IBF_PROF_UPDATE_ALL,
180
181 HQA_EXT_CMD_ERR,
182
183 __HQA_EXT_CMD_MAX_NUM,
184};
185
186struct atenl_data {
187 u8 buf[RACFG_PKT_MAX_SIZE];
188 int len;
189 enum atenl_cmd cmd;
190 u32 ext_id;
191 enum atenl_ext_cmd ext_cmd;
192};
193
194struct atenl_cmd_ops {
195 u16 resp_len;
196 int (*ops)(struct atenl *an, struct atenl_data *data);
197};
198
199static inline struct atenl_cmd_hdr * atenl_hdr(struct atenl_data *data)
200{
201 u8 *hqa_data = (u8 *)data->buf + ETH_HLEN;
202
203 return (struct atenl_cmd_hdr *)hqa_data;
204}
205
206static inline void
207atenl_dbg_print_data(struct atenl_data *data, const char *func_name, u32 len)
208{
209#ifdef CONFIG_ATENL_DEBUG_VERBOSE
210 u32 *tmp = (u32 *)data->buf;
211 int i;
212
213 for (i = 0; i < DIV_ROUND_UP(len, 4); i++)
214 atenl_dbg("%s: [%d] = 0x%08x\n", func_name, i, tmp[i]);
215#endif
216}
217
218enum atenl_phy_type {
219 ATENL_PHY_TYPE_CCK,
220 ATENL_PHY_TYPE_OFDM,
221 ATENL_PHY_TYPE_HT,
222 ATENL_PHY_TYPE_HT_GF,
223 ATENL_PHY_TYPE_VHT,
224 ATENL_PHY_TYPE_HE_SU = 8,
225 ATENL_PHY_TYPE_HE_EXT_SU,
226 ATENL_PHY_TYPE_HE_TB,
227 ATENL_PHY_TYPE_HE_MU,
228};
229
230enum atenl_e2p_mode {
231 E2P_EFUSE_MODE = 1,
232 E2P_FLASH_MODE,
233 E2P_EEPROM_MODE,
234 E2P_BIN_MODE,
235};
236
237enum atenl_band_type {
238 BAND_TYPE_UNUSE,
239 BAND_TYPE_2G,
240 BAND_TYPE_5G,
241 BAND_TYPE_2G_5G,
242 BAND_TYPE_6G,
243 BAND_TYPE_2G_6G,
244 BAND_TYPE_5G_6G,
245 BAND_TYPE_2G_5G_6G,
246};
247
248enum atenl_ch_band {
249 CH_BAND_2GHZ,
250 CH_BAND_5GHZ,
251 CH_BAND_6GHZ,
252};
253
254/* for mt7915 */
255enum {
256 MT_EE_BAND_SEL_DEFAULT,
257 MT_EE_BAND_SEL_5GHZ,
258 MT_EE_BAND_SEL_2GHZ,
259 MT_EE_BAND_SEL_DUAL,
260};
261
262/* for mt7916/mt7986 */
263enum {
264 MT_EE_BAND_SEL_2G,
265 MT_EE_BAND_SEL_5G,
266 MT_EE_BAND_SEL_6G,
267 MT_EE_BAND_SEL_5G_6G,
268};
269
270#define MT_EE_WIFI_CONF 0x190
271#define MT_EE_WIFI_CONF0_BAND_SEL GENMASK(7, 6)
272
273enum {
274 MT7976_ONE_ADIE_DBDC = 0x7,
275 MT7975_ONE_ADIE_SINGLE_BAND = 0x8, /* AX7800 */
276 MT7976_ONE_ADIE_SINGLE_BAND = 0xa, /* AX7800 */
277 MT7975_DUAL_ADIE_DBDC = 0xd, /* AX6000 */
278 MT7976_DUAL_ADIE_DBDC = 0xf, /* AX6000 */
279};
280
281enum {
282 TEST_CBW_20MHZ,
283 TEST_CBW_40MHZ,
284 TEST_CBW_80MHZ,
285 TEST_CBW_10MHZ,
286 TEST_CBW_5MHZ,
287 TEST_CBW_160MHZ,
288 TEST_CBW_8080MHZ,
289
290 TEST_CBW_MAX = TEST_CBW_8080MHZ - 1,
291};
292
293struct atenl_rx_info_hdr {
294 __be32 type;
295 __be32 ver;
296 __be32 val;
297 __be32 len;
298} __attribute__((packed));
299
300struct atenl_rx_info_band {
301 __be32 mac_rx_fcs_err_cnt;
302 __be32 mac_rx_mdrdy_cnt;
303 __be32 mac_rx_len_mismatch;
304 __be32 mac_rx_fcs_ok_cnt;
305 __be32 phy_rx_fcs_err_cnt_cck;
306 __be32 phy_rx_fcs_err_cnt_ofdm;
307 __be32 phy_rx_pd_cck;
308 __be32 phy_rx_pd_ofdm;
309 __be32 phy_rx_sig_err_cck;
310 __be32 phy_rx_sfd_err_cck;
311 __be32 phy_rx_sig_err_ofdm;
312 __be32 phy_rx_tag_err_ofdm;
313 __be32 phy_rx_mdrdy_cnt_cck;
314 __be32 phy_rx_mdrdy_cnt_ofdm;
315} __attribute__((packed));
316
317struct atenl_rx_info_path {
318 __be32 rcpi;
319 __be32 rssi;
320 __be32 fagc_ib_rssi;
321 __be32 fagc_wb_rssi;
322 __be32 inst_ib_rssi;
323 __be32 inst_wb_rssi;
324} __attribute__((packed));
325
326struct atenl_rx_info_user {
327 __be32 freq_offset;
328 __be32 snr;
329 __be32 fcs_error_cnt;
330} __attribute__((packed));
331
332struct atenl_rx_info_comm {
333 __be32 rx_fifo_full;
334 __be32 aci_hit_low;
335 __be32 aci_hit_high;
336 __be32 mu_pkt_count;
337 __be32 sig_mcs;
338 __be32 sinr;
339 __be32 driver_rx_count;
340} __attribute__((packed));
341
342enum atenl_ibf_action {
343 TXBF_ACT_INIT = 1,
344 TXBF_ACT_CHANNEL,
345 TXBF_ACT_MCS,
346 TXBF_ACT_POWER,
347 TXBF_ACT_TX_ANT,
348 TXBF_ACT_RX_START,
349 TXBF_ACT_RX_ANT,
350 TXBF_ACT_LNA_GAIN,
351 TXBF_ACT_IBF_PHASE_COMP,
352 TXBF_ACT_TX_PKT,
353 TXBF_ACT_IBF_PROF_UPDATE,
354 TXBF_ACT_EBF_PROF_UPDATE,
355 TXBF_ACT_IBF_PHASE_CAL,
356 TXBF_ACT_IBF_PHASE_E2P_UPDATE = 16,
357};
358
359static inline bool is_mt7915(struct atenl *an)
360{
361 return an->chip_id == 0x7915;
362}
363
364static inline bool is_mt7916(struct atenl *an)
365{
366 return (an->chip_id == 0x7916) || (an->chip_id == 0x7906);
367}
368
369static inline bool is_mt7986(struct atenl *an)
370{
371 return an->chip_id == 0x7986;
372}
373
374int atenl_eth_init(struct atenl *an);
375int atenl_eth_recv(struct atenl *an, struct atenl_data *data);
376int atenl_eth_send(struct atenl *an, struct atenl_data *data);
377int atenl_hqa_recv(struct atenl *an, struct atenl_data *data);
378int atenl_hqa_proc_cmd(struct atenl *an, struct atenl_data *data);
379int atenl_nl_process(struct atenl *an, struct atenl_data *data);
380int atenl_nl_process_many(struct atenl *an, struct atenl_data *data);
381int atenl_nl_check_mtd(struct atenl *an);
382int atenl_nl_write_eeprom(struct atenl *an, u32 offset, u8 *val, int len);
383int atenl_nl_write_efuse_all(struct atenl *an, struct atenl_data *data);
384int atenl_nl_update_buffer_mode(struct atenl *an);
385int atenl_nl_set_state(struct atenl *an, u8 band,
386 enum mt76_testmode_state state);
387int atenl_eeprom_init(struct atenl *an, u8 phy_idx);
388void atenl_eeprom_close(struct atenl *an);
389int atenl_eeprom_write_mtd(struct atenl *an);
390int atenl_eeprom_read_from_driver(struct atenl *an, u32 offset, int len);
391void atenl_eeprom_cmd_handler(struct atenl *an, u8 phy_idx, char *cmd);
392u16 atenl_get_center_channel(u8 bw, u8 ch_band, u16 ctrl_ch);
393int atenl_reg_read(struct atenl *an, u32 offset, u32 *res);
394int atenl_reg_write(struct atenl *an, u32 offset, u32 val);
395
396#endif