developer | 0f312e8 | 2022-11-01 12:31:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* Copyright (C) 2022 MediaTek Inc. */ |
| 3 | |
| 4 | #ifndef __MT76_CONNAC2_MAC_H |
| 5 | #define __MT76_CONNAC2_MAC_H |
| 6 | |
| 7 | enum tx_header_format { |
| 8 | MT_HDR_FORMAT_802_3, |
| 9 | MT_HDR_FORMAT_CMD, |
| 10 | MT_HDR_FORMAT_802_11, |
| 11 | MT_HDR_FORMAT_802_11_EXT, |
| 12 | }; |
| 13 | |
| 14 | enum tx_pkt_type { |
| 15 | MT_TX_TYPE_CT, |
| 16 | MT_TX_TYPE_SF, |
| 17 | MT_TX_TYPE_CMD, |
| 18 | MT_TX_TYPE_FW, |
| 19 | }; |
| 20 | |
| 21 | enum { |
| 22 | MT_CTX0, |
| 23 | MT_HIF0 = 0x0, |
| 24 | |
| 25 | MT_LMAC_AC00 = 0x0, |
| 26 | MT_LMAC_AC01, |
| 27 | MT_LMAC_AC02, |
| 28 | MT_LMAC_AC03, |
| 29 | MT_LMAC_ALTX0 = 0x10, |
| 30 | MT_LMAC_BMC0, |
| 31 | MT_LMAC_BCN0, |
| 32 | MT_LMAC_PSMP0, |
| 33 | }; |
| 34 | |
| 35 | #define MT_TXD0_Q_IDX GENMASK(31, 25) |
| 36 | #define MT_TXD0_PKT_FMT GENMASK(24, 23) |
| 37 | #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16) |
| 38 | #define MT_TXD0_TX_BYTES GENMASK(15, 0) |
| 39 | |
| 40 | #define MT_TXD1_LONG_FORMAT BIT(31) |
| 41 | #define MT_TXD1_TGID BIT(30) |
| 42 | #define MT_TXD1_OWN_MAC GENMASK(29, 24) |
| 43 | #define MT_TXD1_AMSDU BIT(23) |
| 44 | #define MT_TXD1_TID GENMASK(22, 20) |
| 45 | #define MT_TXD1_HDR_PAD GENMASK(19, 18) |
| 46 | #define MT_TXD1_HDR_FORMAT GENMASK(17, 16) |
| 47 | #define MT_TXD1_HDR_INFO GENMASK(15, 11) |
| 48 | #define MT_TXD1_ETH_802_3 BIT(15) |
| 49 | #define MT_TXD1_VTA BIT(10) |
| 50 | #define MT_TXD1_WLAN_IDX GENMASK(9, 0) |
| 51 | |
| 52 | #define MT_TXD2_FIX_RATE BIT(31) |
| 53 | #define MT_TXD2_FIXED_RATE BIT(30) |
| 54 | #define MT_TXD2_POWER_OFFSET GENMASK(29, 24) |
| 55 | #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16) |
| 56 | #define MT_TXD2_FRAG GENMASK(15, 14) |
| 57 | #define MT_TXD2_HTC_VLD BIT(13) |
| 58 | #define MT_TXD2_DURATION BIT(12) |
| 59 | #define MT_TXD2_BIP BIT(11) |
| 60 | #define MT_TXD2_MULTICAST BIT(10) |
| 61 | #define MT_TXD2_RTS BIT(9) |
| 62 | #define MT_TXD2_SOUNDING BIT(8) |
| 63 | #define MT_TXD2_NDPA BIT(7) |
| 64 | #define MT_TXD2_NDP BIT(6) |
| 65 | #define MT_TXD2_FRAME_TYPE GENMASK(5, 4) |
| 66 | #define MT_TXD2_SUB_TYPE GENMASK(3, 0) |
| 67 | |
| 68 | #define MT_TXD3_SN_VALID BIT(31) |
| 69 | #define MT_TXD3_PN_VALID BIT(30) |
| 70 | #define MT_TXD3_SW_POWER_MGMT BIT(29) |
| 71 | #define MT_TXD3_BA_DISABLE BIT(28) |
| 72 | #define MT_TXD3_SEQ GENMASK(27, 16) |
| 73 | #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11) |
| 74 | #define MT_TXD3_TX_COUNT GENMASK(10, 6) |
| 75 | #define MT_TXD3_TIMING_MEASURE BIT(5) |
| 76 | #define MT_TXD3_DAS BIT(4) |
| 77 | #define MT_TXD3_EEOSP BIT(3) |
| 78 | #define MT_TXD3_EMRD BIT(2) |
| 79 | #define MT_TXD3_PROTECT_FRAME BIT(1) |
| 80 | #define MT_TXD3_NO_ACK BIT(0) |
| 81 | |
| 82 | #define MT_TXD4_PN_LOW GENMASK(31, 0) |
| 83 | |
| 84 | #define MT_TXD5_PN_HIGH GENMASK(31, 16) |
| 85 | #define MT_TXD5_MD BIT(15) |
| 86 | #define MT_TXD5_ADD_BA BIT(14) |
| 87 | #define MT_TXD5_TX_STATUS_HOST BIT(10) |
| 88 | #define MT_TXD5_TX_STATUS_MCU BIT(9) |
| 89 | #define MT_TXD5_TX_STATUS_FMT BIT(8) |
| 90 | #define MT_TXD5_PID GENMASK(7, 0) |
| 91 | |
| 92 | #define MT_TXD6_TX_IBF BIT(31) |
| 93 | #define MT_TXD6_TX_EBF BIT(30) |
| 94 | #define MT_TXD6_TX_RATE GENMASK(29, 16) |
| 95 | #define MT_TXD6_SGI GENMASK(15, 14) |
| 96 | #define MT_TXD6_HELTF GENMASK(13, 12) |
| 97 | #define MT_TXD6_LDPC BIT(11) |
| 98 | #define MT_TXD6_SPE_ID_IDX BIT(10) |
| 99 | #define MT_TXD6_ANT_ID GENMASK(7, 4) |
| 100 | #define MT_TXD6_DYN_BW BIT(3) |
| 101 | #define MT_TXD6_FIXED_BW BIT(2) |
| 102 | #define MT_TXD6_BW GENMASK(1, 0) |
| 103 | |
| 104 | #define MT_TXD7_TXD_LEN GENMASK(31, 30) |
| 105 | #define MT_TXD7_UDP_TCP_SUM BIT(29) |
| 106 | #define MT_TXD7_IP_SUM BIT(28) |
| 107 | #define MT_TXD7_TYPE GENMASK(21, 20) |
| 108 | #define MT_TXD7_SUB_TYPE GENMASK(19, 16) |
| 109 | |
| 110 | #define MT_TXD7_PSE_FID GENMASK(27, 16) |
| 111 | #define MT_TXD7_SPE_IDX GENMASK(15, 11) |
| 112 | #define MT_TXD7_HW_AMSDU BIT(10) |
| 113 | #define MT_TXD7_TX_TIME GENMASK(9, 0) |
| 114 | |
| 115 | #define MT_TXD8_L_TYPE GENMASK(5, 4) |
| 116 | #define MT_TXD8_L_SUB_TYPE GENMASK(3, 0) |
| 117 | |
| 118 | #define MT_TX_RATE_STBC BIT(13) |
| 119 | #define MT_TX_RATE_NSS GENMASK(12, 10) |
| 120 | #define MT_TX_RATE_MODE GENMASK(9, 6) |
| 121 | #define MT_TX_RATE_SU_EXT_TONE BIT(5) |
| 122 | #define MT_TX_RATE_DCM BIT(4) |
| 123 | /* VHT/HE only use bits 0-3 */ |
| 124 | #define MT_TX_RATE_IDX GENMASK(5, 0) |
| 125 | |
| 126 | #define MT_TXS0_FIXED_RATE BIT(31) |
| 127 | #define MT_TXS0_BW GENMASK(30, 29) |
| 128 | #define MT_TXS0_TID GENMASK(28, 26) |
| 129 | #define MT_TXS0_AMPDU BIT(25) |
| 130 | #define MT_TXS0_TXS_FORMAT GENMASK(24, 23) |
| 131 | #define MT_TXS0_BA_ERROR BIT(22) |
| 132 | #define MT_TXS0_PS_FLAG BIT(21) |
| 133 | #define MT_TXS0_TXOP_TIMEOUT BIT(20) |
| 134 | #define MT_TXS0_BIP_ERROR BIT(19) |
| 135 | |
| 136 | #define MT_TXS0_QUEUE_TIMEOUT BIT(18) |
| 137 | #define MT_TXS0_RTS_TIMEOUT BIT(17) |
| 138 | #define MT_TXS0_ACK_TIMEOUT BIT(16) |
| 139 | #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16) |
| 140 | |
| 141 | #define MT_TXS0_TX_STATUS_HOST BIT(15) |
| 142 | #define MT_TXS0_TX_STATUS_MCU BIT(14) |
| 143 | #define MT_TXS0_TX_RATE GENMASK(13, 0) |
| 144 | |
| 145 | #define MT_TXS1_SEQNO GENMASK(31, 20) |
| 146 | #define MT_TXS1_RESP_RATE GENMASK(19, 16) |
| 147 | #define MT_TXS1_RXV_SEQNO GENMASK(15, 8) |
| 148 | #define MT_TXS1_TX_POWER_DBM GENMASK(7, 0) |
| 149 | |
| 150 | #define MT_TXS2_BF_STATUS GENMASK(31, 30) |
| 151 | #define MT_TXS2_LAST_TX_RATE GENMASK(29, 27) |
| 152 | #define MT_TXS2_SHARED_ANTENNA BIT(26) |
| 153 | #define MT_TXS2_WCID GENMASK(25, 16) |
| 154 | #define MT_TXS2_TX_DELAY GENMASK(15, 0) |
| 155 | |
| 156 | #define MT_TXS3_PID GENMASK(31, 24) |
| 157 | #define MT_TXS3_ANT_ID GENMASK(23, 0) |
| 158 | |
| 159 | #define MT_TXS4_TIMESTAMP GENMASK(31, 0) |
| 160 | |
| 161 | /* PPDU based TXS */ |
| 162 | #define MT_TXS5_MPDU_TX_BYTE GENMASK(22, 0) |
| 163 | #define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23) |
| 164 | |
| 165 | #define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23) |
| 166 | |
| 167 | #define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23) |
| 168 | |
| 169 | /* RXD DW1 */ |
| 170 | #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0) |
| 171 | #define MT_RXD1_NORMAL_GROUP_1 BIT(11) |
| 172 | #define MT_RXD1_NORMAL_GROUP_2 BIT(12) |
| 173 | #define MT_RXD1_NORMAL_GROUP_3 BIT(13) |
| 174 | #define MT_RXD1_NORMAL_GROUP_4 BIT(14) |
| 175 | #define MT_RXD1_NORMAL_GROUP_5 BIT(15) |
| 176 | #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16) |
| 177 | #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21) |
| 178 | #define MT_RXD1_NORMAL_CM BIT(23) |
| 179 | #define MT_RXD1_NORMAL_CLM BIT(24) |
| 180 | #define MT_RXD1_NORMAL_ICV_ERR BIT(25) |
| 181 | #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26) |
| 182 | #define MT_RXD1_NORMAL_FCS_ERR BIT(27) |
| 183 | #define MT_RXD1_NORMAL_BAND_IDX BIT(28) |
| 184 | #define MT_RXD1_NORMAL_SPP_EN BIT(29) |
| 185 | #define MT_RXD1_NORMAL_ADD_OM BIT(30) |
| 186 | #define MT_RXD1_NORMAL_SEC_DONE BIT(31) |
| 187 | |
| 188 | /* RXD DW2 */ |
| 189 | #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0) |
| 190 | #define MT_RXD2_NORMAL_CO_ANT BIT(6) |
| 191 | #define MT_RXD2_NORMAL_BF_CQI BIT(7) |
| 192 | #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8) |
| 193 | #define MT_RXD2_NORMAL_HDR_TRANS BIT(13) |
| 194 | #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14) |
| 195 | #define MT_RXD2_NORMAL_TID GENMASK(19, 16) |
| 196 | #define MT_RXD2_NORMAL_MU_BAR BIT(21) |
| 197 | #define MT_RXD2_NORMAL_SW_BIT BIT(22) |
| 198 | #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23) |
| 199 | #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24) |
| 200 | #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25) |
| 201 | #define MT_RXD2_NORMAL_INT_FRAME BIT(26) |
| 202 | #define MT_RXD2_NORMAL_FRAG BIT(27) |
| 203 | #define MT_RXD2_NORMAL_NULL_FRAME BIT(28) |
| 204 | #define MT_RXD2_NORMAL_NDATA BIT(29) |
| 205 | #define MT_RXD2_NORMAL_NON_AMPDU BIT(30) |
| 206 | #define MT_RXD2_NORMAL_BF_REPORT BIT(31) |
| 207 | |
| 208 | /* RXD DW4 */ |
| 209 | #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0) |
| 210 | #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0) |
| 211 | #define MT_RXD4_MID_AMSDU_FRAME BIT(1) |
| 212 | #define MT_RXD4_LAST_AMSDU_FRAME BIT(0) |
| 213 | #define MT_RXD4_NORMAL_PATTERN_DROP BIT(9) |
| 214 | #define MT_RXD4_NORMAL_CLS BIT(10) |
| 215 | #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11) |
| 216 | #define MT_RXD4_NORMAL_MAGIC_PKT BIT(13) |
| 217 | #define MT_RXD4_NORMAL_WOL GENMASK(18, 14) |
| 218 | #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19) |
| 219 | #define MT_RXD3_NORMAL_PF_MODE BIT(29) |
| 220 | #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30) |
| 221 | |
| 222 | #define MT_RXV_HDR_BAND_IDX BIT(24) |
| 223 | |
| 224 | /* RXD DW3 */ |
| 225 | #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0) |
| 226 | #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8) |
| 227 | #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16) |
| 228 | #define MT_RXD3_NORMAL_U2M BIT(0) |
| 229 | #define MT_RXD3_NORMAL_HTC_VLD BIT(0) |
| 230 | #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19) |
| 231 | #define MT_RXD3_NORMAL_BEACON_MC BIT(20) |
| 232 | #define MT_RXD3_NORMAL_BEACON_UC BIT(21) |
| 233 | #define MT_RXD3_NORMAL_AMSDU BIT(22) |
| 234 | #define MT_RXD3_NORMAL_MESH BIT(23) |
| 235 | #define MT_RXD3_NORMAL_MHCP BIT(24) |
| 236 | #define MT_RXD3_NORMAL_NO_INFO_WB BIT(25) |
| 237 | #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26) |
| 238 | #define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27) |
| 239 | #define MT_RXD3_NORMAL_MORE BIT(28) |
| 240 | #define MT_RXD3_NORMAL_UNWANT BIT(29) |
| 241 | #define MT_RXD3_NORMAL_RX_DROP BIT(30) |
| 242 | #define MT_RXD3_NORMAL_VLAN2ETH BIT(31) |
| 243 | |
| 244 | /* RXD GROUP4 */ |
| 245 | #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0) |
| 246 | #define MT_RXD6_TA_LO GENMASK(31, 16) |
| 247 | |
| 248 | #define MT_RXD7_TA_HI GENMASK(31, 0) |
| 249 | |
| 250 | #define MT_RXD8_SEQ_CTRL GENMASK(15, 0) |
| 251 | #define MT_RXD8_QOS_CTL GENMASK(31, 16) |
| 252 | |
| 253 | #define MT_RXD9_HT_CONTROL GENMASK(31, 0) |
| 254 | |
| 255 | /* P-RXV DW0 */ |
| 256 | #define MT_PRXV_TX_RATE GENMASK(6, 0) |
| 257 | #define MT_PRXV_TX_DCM BIT(4) |
| 258 | #define MT_PRXV_TX_ER_SU_106T BIT(5) |
| 259 | #define MT_PRXV_NSTS GENMASK(9, 7) |
| 260 | #define MT_PRXV_TXBF BIT(10) |
| 261 | #define MT_PRXV_HT_AD_CODE BIT(11) |
| 262 | #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28) |
| 263 | |
| 264 | #define MT_PRXV_FRAME_MODE GENMASK(14, 12) |
| 265 | #define MT_PRXV_HT_SGI GENMASK(16, 15) |
| 266 | #define MT_PRXV_HT_STBC GENMASK(23, 22) |
| 267 | #define MT_PRXV_TX_MODE GENMASK(27, 24) |
| 268 | #define MT_PRXV_DCM BIT(17) |
| 269 | #define MT_PRXV_NUM_RX BIT(20, 18) |
| 270 | |
| 271 | /* P-RXV DW1 */ |
| 272 | #define MT_PRXV_RCPI3 GENMASK(31, 24) |
| 273 | #define MT_PRXV_RCPI2 GENMASK(23, 16) |
| 274 | #define MT_PRXV_RCPI1 GENMASK(15, 8) |
| 275 | #define MT_PRXV_RCPI0 GENMASK(7, 0) |
| 276 | #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0) |
| 277 | |
| 278 | /* C-RXV */ |
| 279 | #define MT_CRXV_HT_STBC GENMASK(1, 0) |
| 280 | #define MT_CRXV_TX_MODE GENMASK(7, 4) |
| 281 | #define MT_CRXV_FRAME_MODE GENMASK(10, 8) |
| 282 | #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13) |
| 283 | #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17) |
| 284 | #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20) |
| 285 | #define MT_CRXV_HE_PE_DISAMBIG BIT(23) |
| 286 | #define MT_CRXV_HE_NUM_USER GENMASK(30, 24) |
| 287 | #define MT_CRXV_HE_UPLINK BIT(31) |
| 288 | |
| 289 | #define MT_CRXV_HE_RU0 GENMASK(7, 0) |
| 290 | #define MT_CRXV_HE_RU1 GENMASK(15, 8) |
| 291 | #define MT_CRXV_HE_RU2 GENMASK(23, 16) |
| 292 | #define MT_CRXV_HE_RU3 GENMASK(31, 24) |
| 293 | |
| 294 | #define MT_CRXV_HE_MU_AID GENMASK(30, 20) |
| 295 | |
| 296 | #define MT_CRXV_HE_SR_MASK GENMASK(11, 8) |
| 297 | #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12) |
| 298 | #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17) |
| 299 | #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21) |
| 300 | |
| 301 | #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0) |
| 302 | #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6) |
| 303 | #define MT_CRXV_HE_BEAM_CHNG BIT(13) |
| 304 | #define MT_CRXV_HE_DOPPLER BIT(16) |
| 305 | |
| 306 | #define MT_CRXV_SNR GENMASK(18, 13) |
| 307 | #define MT_CRXV_FOE_LO GENMASK(31, 19) |
| 308 | #define MT_CRXV_FOE_HI GENMASK(6, 0) |
| 309 | #define MT_CRXV_FOE_SHIFT 13 |
| 310 | |
| 311 | #define MT_CT_INFO_APPLY_TXD BIT(0) |
| 312 | #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1) |
| 313 | #define MT_CT_INFO_MGMT_FRAME BIT(2) |
| 314 | #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3) |
| 315 | #define MT_CT_INFO_HSR2_TX BIT(4) |
| 316 | #define MT_CT_INFO_FROM_HOST BIT(7) |
| 317 | |
| 318 | enum tx_mcu_port_q_idx { |
| 319 | MT_TX_MCU_PORT_RX_Q0 = 0x20, |
| 320 | MT_TX_MCU_PORT_RX_Q1, |
| 321 | MT_TX_MCU_PORT_RX_Q2, |
| 322 | MT_TX_MCU_PORT_RX_Q3, |
| 323 | MT_TX_MCU_PORT_RX_FWDL = 0x3e |
| 324 | }; |
| 325 | |
| 326 | enum tx_port_idx { |
| 327 | MT_TX_PORT_IDX_LMAC, |
| 328 | MT_TX_PORT_IDX_MCU |
| 329 | }; |
| 330 | |
| 331 | #endif /* __MT76_CONNAC2_MAC_H */ |