developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (c) 2015 MediaTek Inc. |
| 4 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> |
| 5 | * Sascha Hauer <s.hauer@pengutronix.de> |
| 6 | * Dawei Chien <dawei.chien@mediatek.com> |
| 7 | * Louis Yu <louis.yu@mediatek.com> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/nvmem-consumer.h> |
| 16 | #include <linux/of.h> |
| 17 | #include <linux/of_address.h> |
| 18 | #include <linux/of_device.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/thermal.h> |
| 23 | #include <linux/reset.h> |
| 24 | #include <linux/types.h> |
| 25 | |
| 26 | /* AUXADC Registers */ |
| 27 | #define AUXADC_CON1_SET_V 0x008 |
| 28 | #define AUXADC_CON1_CLR_V 0x00c |
| 29 | #define AUXADC_CON2_V 0x010 |
| 30 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) |
| 31 | |
| 32 | #define APMIXED_SYS_TS_CON1 0x604 |
| 33 | |
| 34 | /* Thermal Controller Registers */ |
| 35 | #define TEMP_MONCTL0 0x000 |
| 36 | #define TEMP_MONCTL1 0x004 |
| 37 | #define TEMP_MONCTL2 0x008 |
| 38 | #define TEMP_MONIDET0 0x014 |
| 39 | #define TEMP_MONIDET1 0x018 |
| 40 | #define TEMP_MSRCTL0 0x038 |
| 41 | #define TEMP_MSRCTL1 0x03c |
| 42 | #define TEMP_AHBPOLL 0x040 |
| 43 | #define TEMP_AHBTO 0x044 |
| 44 | #define TEMP_ADCPNP0 0x048 |
| 45 | #define TEMP_ADCPNP1 0x04c |
| 46 | #define TEMP_ADCPNP2 0x050 |
| 47 | #define TEMP_ADCPNP3 0x0b4 |
| 48 | |
| 49 | #define TEMP_ADCMUX 0x054 |
| 50 | #define TEMP_ADCEN 0x060 |
| 51 | #define TEMP_PNPMUXADDR 0x064 |
| 52 | #define TEMP_ADCMUXADDR 0x068 |
| 53 | #define TEMP_ADCENADDR 0x074 |
| 54 | #define TEMP_ADCVALIDADDR 0x078 |
| 55 | #define TEMP_ADCVOLTADDR 0x07c |
| 56 | #define TEMP_RDCTRL 0x080 |
| 57 | #define TEMP_ADCVALIDMASK 0x084 |
| 58 | #define TEMP_ADCVOLTAGESHIFT 0x088 |
| 59 | #define TEMP_ADCWRITECTRL 0x08c |
| 60 | #define TEMP_MSR0 0x090 |
| 61 | #define TEMP_MSR1 0x094 |
| 62 | #define TEMP_MSR2 0x098 |
| 63 | #define TEMP_MSR3 0x0B8 |
| 64 | |
| 65 | #define TEMP_SPARE0 0x0f0 |
| 66 | |
| 67 | #define TEMP_ADCPNP0_1 0x148 |
| 68 | #define TEMP_ADCPNP1_1 0x14c |
| 69 | #define TEMP_ADCPNP2_1 0x150 |
| 70 | #define TEMP_MSR0_1 0x190 |
| 71 | #define TEMP_MSR1_1 0x194 |
| 72 | #define TEMP_MSR2_1 0x198 |
| 73 | #define TEMP_ADCPNP3_1 0x1b4 |
| 74 | #define TEMP_MSR3_1 0x1B8 |
| 75 | |
| 76 | #define PTPCORESEL 0x400 |
| 77 | |
| 78 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) |
| 79 | |
| 80 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
| 81 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
| 82 | |
| 83 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) |
| 84 | |
| 85 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) |
| 86 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) |
| 87 | |
| 88 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) |
| 89 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) |
| 90 | |
| 91 | /* MT8173 thermal sensors */ |
| 92 | #define MT8173_TS1 0 |
| 93 | #define MT8173_TS2 1 |
| 94 | #define MT8173_TS3 2 |
| 95 | #define MT8173_TS4 3 |
| 96 | #define MT8173_TSABB 4 |
| 97 | |
| 98 | /* AUXADC channel 11 is used for the temperature sensors */ |
| 99 | #define MT8173_TEMP_AUXADC_CHANNEL 11 |
| 100 | |
| 101 | /* The total number of temperature sensors in the MT8173 */ |
| 102 | #define MT8173_NUM_SENSORS 5 |
| 103 | |
| 104 | /* The number of banks in the MT8173 */ |
| 105 | #define MT8173_NUM_ZONES 4 |
| 106 | |
| 107 | /* The number of sensing points per bank */ |
| 108 | #define MT8173_NUM_SENSORS_PER_ZONE 4 |
| 109 | |
| 110 | /* The number of controller in the MT8173 */ |
| 111 | #define MT8173_NUM_CONTROLLER 1 |
| 112 | |
| 113 | /* The calibration coefficient of sensor */ |
| 114 | #define MT8173_CALIBRATION 165 |
| 115 | |
| 116 | /* |
| 117 | * Layout of the fuses providing the calibration data |
| 118 | * These macros could be used for MT8183, MT8173, MT2701, and MT2712. |
| 119 | * MT8183 has 6 sensors and needs 6 VTS calibration data. |
| 120 | * MT8173 has 5 sensors and needs 5 VTS calibration data. |
| 121 | * MT2701 has 3 sensors and needs 3 VTS calibration data. |
| 122 | * MT2712 has 4 sensors and needs 4 VTS calibration data. |
| 123 | */ |
| 124 | #define CALIB_BUF0_VALID_V1 BIT(0) |
| 125 | #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) |
| 126 | #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) |
| 127 | #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) |
| 128 | #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) |
| 129 | #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) |
| 130 | #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) |
| 131 | #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) |
| 132 | #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) |
| 133 | #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) |
| 134 | #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) |
| 135 | #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) |
| 136 | |
| 137 | /* |
| 138 | * Layout of the fuses providing the calibration data |
| 139 | * These macros could be used for MT7622. |
| 140 | */ |
| 141 | #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) |
| 142 | #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) |
| 143 | #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) |
| 144 | #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) |
| 145 | #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) |
| 146 | #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) |
| 147 | #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) |
| 148 | #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) |
| 149 | #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) |
| 150 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 151 | /* |
| 152 | * Layout of the fuses providing the calibration data |
developer | 1f80b45 | 2021-12-17 14:26:01 +0800 | [diff] [blame] | 153 | * These macros could be used for MT7981 and MT7986. |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 154 | */ |
| 155 | #define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) |
| 156 | #define CALIB_BUF0_ADC_OE_V3(x) (((x) >> 10) & 0x3ff) |
| 157 | #define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) |
| 158 | #define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) |
| 159 | #define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) |
| 160 | #define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) |
| 161 | #define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) |
| 162 | #define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) |
| 163 | #define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) |
| 164 | #define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) |
| 165 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 166 | enum { |
| 167 | VTS1, |
| 168 | VTS2, |
| 169 | VTS3, |
| 170 | VTS4, |
| 171 | VTS5, |
| 172 | VTSABB, |
| 173 | MAX_NUM_VTS, |
| 174 | }; |
| 175 | |
| 176 | enum mtk_thermal_version { |
| 177 | MTK_THERMAL_V1 = 1, |
| 178 | MTK_THERMAL_V2, |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 179 | MTK_THERMAL_V3, |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 180 | }; |
| 181 | |
| 182 | /* MT2701 thermal sensors */ |
| 183 | #define MT2701_TS1 0 |
| 184 | #define MT2701_TS2 1 |
| 185 | #define MT2701_TSABB 2 |
| 186 | |
| 187 | /* AUXADC channel 11 is used for the temperature sensors */ |
| 188 | #define MT2701_TEMP_AUXADC_CHANNEL 11 |
| 189 | |
| 190 | /* The total number of temperature sensors in the MT2701 */ |
| 191 | #define MT2701_NUM_SENSORS 3 |
| 192 | |
| 193 | /* The number of sensing points per bank */ |
| 194 | #define MT2701_NUM_SENSORS_PER_ZONE 3 |
| 195 | |
| 196 | /* The number of controller in the MT2701 */ |
| 197 | #define MT2701_NUM_CONTROLLER 1 |
| 198 | |
| 199 | /* The calibration coefficient of sensor */ |
| 200 | #define MT2701_CALIBRATION 165 |
| 201 | |
| 202 | /* MT2712 thermal sensors */ |
| 203 | #define MT2712_TS1 0 |
| 204 | #define MT2712_TS2 1 |
| 205 | #define MT2712_TS3 2 |
| 206 | #define MT2712_TS4 3 |
| 207 | |
| 208 | /* AUXADC channel 11 is used for the temperature sensors */ |
| 209 | #define MT2712_TEMP_AUXADC_CHANNEL 11 |
| 210 | |
| 211 | /* The total number of temperature sensors in the MT2712 */ |
| 212 | #define MT2712_NUM_SENSORS 4 |
| 213 | |
| 214 | /* The number of sensing points per bank */ |
| 215 | #define MT2712_NUM_SENSORS_PER_ZONE 4 |
| 216 | |
| 217 | /* The number of controller in the MT2712 */ |
| 218 | #define MT2712_NUM_CONTROLLER 1 |
| 219 | |
| 220 | /* The calibration coefficient of sensor */ |
| 221 | #define MT2712_CALIBRATION 165 |
| 222 | |
| 223 | #define MT7622_TEMP_AUXADC_CHANNEL 11 |
| 224 | #define MT7622_NUM_SENSORS 1 |
| 225 | #define MT7622_NUM_ZONES 1 |
| 226 | #define MT7622_NUM_SENSORS_PER_ZONE 1 |
| 227 | #define MT7622_TS1 0 |
| 228 | #define MT7622_NUM_CONTROLLER 1 |
| 229 | |
| 230 | /* The maximum number of banks */ |
| 231 | #define MAX_NUM_ZONES 8 |
| 232 | |
| 233 | /* The calibration coefficient of sensor */ |
| 234 | #define MT7622_CALIBRATION 165 |
| 235 | |
| 236 | /* MT8183 thermal sensors */ |
| 237 | #define MT8183_TS1 0 |
| 238 | #define MT8183_TS2 1 |
| 239 | #define MT8183_TS3 2 |
| 240 | #define MT8183_TS4 3 |
| 241 | #define MT8183_TS5 4 |
| 242 | #define MT8183_TSABB 5 |
| 243 | |
| 244 | /* AUXADC channel is used for the temperature sensors */ |
| 245 | #define MT8183_TEMP_AUXADC_CHANNEL 11 |
| 246 | |
| 247 | /* The total number of temperature sensors in the MT8183 */ |
| 248 | #define MT8183_NUM_SENSORS 6 |
| 249 | |
| 250 | /* The number of banks in the MT8183 */ |
| 251 | #define MT8183_NUM_ZONES 1 |
| 252 | |
| 253 | /* The number of sensing points per bank */ |
| 254 | #define MT8183_NUM_SENSORS_PER_ZONE 6 |
| 255 | |
| 256 | /* The number of controller in the MT8183 */ |
| 257 | #define MT8183_NUM_CONTROLLER 2 |
| 258 | |
| 259 | /* The calibration coefficient of sensor */ |
| 260 | #define MT8183_CALIBRATION 153 |
| 261 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 262 | /* AUXADC channel 11 is used for the temperature sensors */ |
developer | 1f80b45 | 2021-12-17 14:26:01 +0800 | [diff] [blame] | 263 | #define MT7981_TEMP_AUXADC_CHANNEL 11 |
| 264 | |
| 265 | /* The total number of temperature sensors in the MT7981 */ |
| 266 | #define MT7981_NUM_SENSORS 1 |
| 267 | |
| 268 | /* The number of banks in the MT7981 */ |
| 269 | #define MT7981_NUM_ZONES 1 |
| 270 | |
| 271 | /* The number of sensing points per bank */ |
| 272 | #define MT7981_NUM_SENSORS_PER_ZONE 1 |
| 273 | |
| 274 | /* MT7981 thermal sensors */ |
| 275 | #define MT7981_TS1 0 |
| 276 | |
| 277 | /* The number of controller in the MT7981 */ |
| 278 | #define MT7981_NUM_CONTROLLER 1 |
| 279 | |
| 280 | /* The calibration coefficient of sensor */ |
| 281 | #define MT7981_CALIBRATION 165 |
| 282 | |
| 283 | /* AUXADC channel 11 is used for the temperature sensors */ |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 284 | #define MT7986_TEMP_AUXADC_CHANNEL 11 |
| 285 | |
| 286 | /* The total number of temperature sensors in the MT7986 */ |
| 287 | #define MT7986_NUM_SENSORS 1 |
| 288 | |
| 289 | /* The number of banks in the MT7986 */ |
| 290 | #define MT7986_NUM_ZONES 1 |
| 291 | |
| 292 | /* The number of sensing points per bank */ |
| 293 | #define MT7986_NUM_SENSORS_PER_ZONE 1 |
| 294 | |
| 295 | /* MT7986 thermal sensors */ |
| 296 | #define MT7986_TS1 0 |
| 297 | |
| 298 | /* The number of controller in the MT7986 */ |
| 299 | #define MT7986_NUM_CONTROLLER 1 |
| 300 | |
| 301 | /* The calibration coefficient of sensor */ |
| 302 | #define MT7986_CALIBRATION 165 |
| 303 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 304 | struct mtk_thermal; |
| 305 | |
| 306 | struct thermal_bank_cfg { |
| 307 | unsigned int num_sensors; |
| 308 | const int *sensors; |
| 309 | }; |
| 310 | |
| 311 | struct mtk_thermal_bank { |
| 312 | struct mtk_thermal *mt; |
| 313 | int id; |
| 314 | }; |
| 315 | |
| 316 | struct mtk_thermal_data { |
| 317 | s32 num_banks; |
| 318 | s32 num_sensors; |
| 319 | s32 auxadc_channel; |
| 320 | const int *vts_index; |
| 321 | const int *sensor_mux_values; |
| 322 | const int *msr; |
| 323 | const int *adcpnp; |
| 324 | const int cali_val; |
| 325 | const int num_controller; |
| 326 | const int *controller_offset; |
| 327 | bool need_switch_bank; |
| 328 | struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; |
| 329 | enum mtk_thermal_version version; |
| 330 | }; |
| 331 | |
| 332 | struct mtk_thermal { |
| 333 | struct device *dev; |
| 334 | void __iomem *thermal_base; |
| 335 | |
| 336 | struct clk *clk_peri_therm; |
| 337 | struct clk *clk_auxadc; |
developer | df32d11 | 2021-08-29 11:58:01 +0800 | [diff] [blame] | 338 | struct clk *clk_adc_32k; |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 339 | /* lock: for getting and putting banks */ |
| 340 | struct mutex lock; |
| 341 | |
| 342 | /* Calibration values */ |
| 343 | s32 adc_ge; |
| 344 | s32 adc_oe; |
| 345 | s32 degc_cali; |
| 346 | s32 o_slope; |
| 347 | s32 o_slope_sign; |
| 348 | s32 vts[MAX_NUM_VTS]; |
| 349 | |
| 350 | const struct mtk_thermal_data *conf; |
| 351 | struct mtk_thermal_bank banks[MAX_NUM_ZONES]; |
| 352 | }; |
| 353 | |
| 354 | /* MT8183 thermal sensor data */ |
| 355 | static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { |
| 356 | MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB |
| 357 | }; |
| 358 | |
| 359 | static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { |
| 360 | TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 |
| 361 | }; |
| 362 | |
| 363 | static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { |
| 364 | TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, |
| 365 | TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 |
| 366 | }; |
| 367 | |
| 368 | static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; |
| 369 | static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; |
| 370 | |
| 371 | static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { |
| 372 | VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB |
| 373 | }; |
| 374 | |
| 375 | /* MT8173 thermal sensor data */ |
| 376 | static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
| 377 | { MT8173_TS2, MT8173_TS3 }, |
| 378 | { MT8173_TS2, MT8173_TS4 }, |
| 379 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, |
| 380 | { MT8173_TS2 }, |
| 381 | }; |
| 382 | |
| 383 | static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
| 384 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
| 385 | }; |
| 386 | |
| 387 | static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
| 388 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
| 389 | }; |
| 390 | |
| 391 | static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; |
| 392 | static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; |
| 393 | |
| 394 | static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { |
| 395 | VTS1, VTS2, VTS3, VTS4, VTSABB |
| 396 | }; |
| 397 | |
| 398 | /* MT2701 thermal sensor data */ |
| 399 | static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { |
| 400 | MT2701_TS1, MT2701_TS2, MT2701_TSABB |
| 401 | }; |
| 402 | |
| 403 | static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { |
| 404 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
| 405 | }; |
| 406 | |
| 407 | static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { |
| 408 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
| 409 | }; |
| 410 | |
| 411 | static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; |
| 412 | static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; |
| 413 | |
| 414 | static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { |
| 415 | VTS1, VTS2, VTS3 |
| 416 | }; |
| 417 | |
| 418 | /* MT2712 thermal sensor data */ |
| 419 | static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { |
| 420 | MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 |
| 421 | }; |
| 422 | |
| 423 | static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { |
| 424 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
| 425 | }; |
| 426 | |
| 427 | static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { |
| 428 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
| 429 | }; |
| 430 | |
| 431 | static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; |
| 432 | static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; |
| 433 | |
| 434 | static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { |
| 435 | VTS1, VTS2, VTS3, VTS4 |
| 436 | }; |
| 437 | |
| 438 | /* MT7622 thermal sensor data */ |
| 439 | static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; |
| 440 | static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; |
| 441 | static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; |
| 442 | static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; |
| 443 | static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; |
| 444 | static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; |
| 445 | |
developer | 1f80b45 | 2021-12-17 14:26:01 +0800 | [diff] [blame] | 446 | /* MT7981 thermal sensor data */ |
| 447 | static const int mt7981_bank_data[MT7981_NUM_SENSORS] = { MT7981_TS1, }; |
| 448 | static const int mt7981_msr[MT7981_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; |
| 449 | static const int mt7981_adcpnp[MT7981_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; |
| 450 | static const int mt7981_mux_values[MT7981_NUM_SENSORS] = { 0, }; |
| 451 | static const int mt7981_vts_index[MT7981_NUM_SENSORS] = { VTS1 }; |
| 452 | static const int mt7981_tc_offset[MT7981_NUM_CONTROLLER] = { 0x0, }; |
| 453 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 454 | /* MT7986 thermal sensor data */ |
| 455 | static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; |
| 456 | static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; |
| 457 | static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; |
| 458 | static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; |
| 459 | static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; |
| 460 | static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; |
| 461 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 462 | /* |
| 463 | * The MT8173 thermal controller has four banks. Each bank can read up to |
| 464 | * four temperature sensors simultaneously. The MT8173 has a total of 5 |
| 465 | * temperature sensors. We use each bank to measure a certain area of the |
| 466 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple |
| 467 | * areas, hence is used in different banks. |
| 468 | * |
| 469 | * The thermal core only gets the maximum temperature of all banks, so |
| 470 | * the bank concept wouldn't be necessary here. However, the SVS (Smart |
| 471 | * Voltage Scaling) unit makes its decisions based on the same bank |
| 472 | * data, and this indeed needs the temperatures of the individual banks |
| 473 | * for making better decisions. |
| 474 | */ |
| 475 | static const struct mtk_thermal_data mt8173_thermal_data = { |
| 476 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, |
| 477 | .num_banks = MT8173_NUM_ZONES, |
| 478 | .num_sensors = MT8173_NUM_SENSORS, |
| 479 | .vts_index = mt8173_vts_index, |
| 480 | .cali_val = MT8173_CALIBRATION, |
| 481 | .num_controller = MT8173_NUM_CONTROLLER, |
| 482 | .controller_offset = mt8173_tc_offset, |
| 483 | .need_switch_bank = true, |
| 484 | .bank_data = { |
| 485 | { |
| 486 | .num_sensors = 2, |
| 487 | .sensors = mt8173_bank_data[0], |
| 488 | }, { |
| 489 | .num_sensors = 2, |
| 490 | .sensors = mt8173_bank_data[1], |
| 491 | }, { |
| 492 | .num_sensors = 3, |
| 493 | .sensors = mt8173_bank_data[2], |
| 494 | }, { |
| 495 | .num_sensors = 1, |
| 496 | .sensors = mt8173_bank_data[3], |
| 497 | }, |
| 498 | }, |
| 499 | .msr = mt8173_msr, |
| 500 | .adcpnp = mt8173_adcpnp, |
| 501 | .sensor_mux_values = mt8173_mux_values, |
| 502 | .version = MTK_THERMAL_V1, |
| 503 | }; |
| 504 | |
| 505 | /* |
| 506 | * The MT2701 thermal controller has one bank, which can read up to |
| 507 | * three temperature sensors simultaneously. The MT2701 has a total of 3 |
| 508 | * temperature sensors. |
| 509 | * |
| 510 | * The thermal core only gets the maximum temperature of this one bank, |
| 511 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
| 512 | * Voltage Scaling) unit makes its decisions based on the same bank |
| 513 | * data. |
| 514 | */ |
| 515 | static const struct mtk_thermal_data mt2701_thermal_data = { |
| 516 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, |
| 517 | .num_banks = 1, |
| 518 | .num_sensors = MT2701_NUM_SENSORS, |
| 519 | .vts_index = mt2701_vts_index, |
| 520 | .cali_val = MT2701_CALIBRATION, |
| 521 | .num_controller = MT2701_NUM_CONTROLLER, |
| 522 | .controller_offset = mt2701_tc_offset, |
| 523 | .need_switch_bank = true, |
| 524 | .bank_data = { |
| 525 | { |
| 526 | .num_sensors = 3, |
| 527 | .sensors = mt2701_bank_data, |
| 528 | }, |
| 529 | }, |
| 530 | .msr = mt2701_msr, |
| 531 | .adcpnp = mt2701_adcpnp, |
| 532 | .sensor_mux_values = mt2701_mux_values, |
| 533 | .version = MTK_THERMAL_V1, |
| 534 | }; |
| 535 | |
| 536 | /* |
| 537 | * The MT2712 thermal controller has one bank, which can read up to |
| 538 | * four temperature sensors simultaneously. The MT2712 has a total of 4 |
| 539 | * temperature sensors. |
| 540 | * |
| 541 | * The thermal core only gets the maximum temperature of this one bank, |
| 542 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
| 543 | * Voltage Scaling) unit makes its decisions based on the same bank |
| 544 | * data. |
| 545 | */ |
| 546 | static const struct mtk_thermal_data mt2712_thermal_data = { |
| 547 | .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, |
| 548 | .num_banks = 1, |
| 549 | .num_sensors = MT2712_NUM_SENSORS, |
| 550 | .vts_index = mt2712_vts_index, |
| 551 | .cali_val = MT2712_CALIBRATION, |
| 552 | .num_controller = MT2712_NUM_CONTROLLER, |
| 553 | .controller_offset = mt2712_tc_offset, |
| 554 | .need_switch_bank = true, |
| 555 | .bank_data = { |
| 556 | { |
| 557 | .num_sensors = 4, |
| 558 | .sensors = mt2712_bank_data, |
| 559 | }, |
| 560 | }, |
| 561 | .msr = mt2712_msr, |
| 562 | .adcpnp = mt2712_adcpnp, |
| 563 | .sensor_mux_values = mt2712_mux_values, |
| 564 | .version = MTK_THERMAL_V1, |
| 565 | }; |
| 566 | |
| 567 | /* |
| 568 | * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data |
| 569 | * access. |
| 570 | */ |
| 571 | static const struct mtk_thermal_data mt7622_thermal_data = { |
| 572 | .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, |
| 573 | .num_banks = MT7622_NUM_ZONES, |
| 574 | .num_sensors = MT7622_NUM_SENSORS, |
| 575 | .vts_index = mt7622_vts_index, |
| 576 | .cali_val = MT7622_CALIBRATION, |
| 577 | .num_controller = MT7622_NUM_CONTROLLER, |
| 578 | .controller_offset = mt7622_tc_offset, |
| 579 | .need_switch_bank = true, |
| 580 | .bank_data = { |
| 581 | { |
| 582 | .num_sensors = 1, |
| 583 | .sensors = mt7622_bank_data, |
| 584 | }, |
| 585 | }, |
| 586 | .msr = mt7622_msr, |
| 587 | .adcpnp = mt7622_adcpnp, |
| 588 | .sensor_mux_values = mt7622_mux_values, |
| 589 | .version = MTK_THERMAL_V2, |
| 590 | }; |
| 591 | |
| 592 | /* |
| 593 | * The MT8183 thermal controller has one bank for the current SW framework. |
| 594 | * The MT8183 has a total of 6 temperature sensors. |
| 595 | * There are two thermal controller to control the six sensor. |
| 596 | * The first one bind 2 sensor, and the other bind 4 sensors. |
| 597 | * The thermal core only gets the maximum temperature of all sensor, so |
| 598 | * the bank concept wouldn't be necessary here. However, the SVS (Smart |
| 599 | * Voltage Scaling) unit makes its decisions based on the same bank |
| 600 | * data, and this indeed needs the temperatures of the individual banks |
| 601 | * for making better decisions. |
| 602 | */ |
| 603 | static const struct mtk_thermal_data mt8183_thermal_data = { |
| 604 | .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, |
| 605 | .num_banks = MT8183_NUM_ZONES, |
| 606 | .num_sensors = MT8183_NUM_SENSORS, |
| 607 | .vts_index = mt8183_vts_index, |
| 608 | .cali_val = MT8183_CALIBRATION, |
| 609 | .num_controller = MT8183_NUM_CONTROLLER, |
| 610 | .controller_offset = mt8183_tc_offset, |
| 611 | .need_switch_bank = false, |
| 612 | .bank_data = { |
| 613 | { |
| 614 | .num_sensors = 6, |
| 615 | .sensors = mt8183_bank_data, |
| 616 | }, |
| 617 | }, |
| 618 | |
| 619 | .msr = mt8183_msr, |
| 620 | .adcpnp = mt8183_adcpnp, |
| 621 | .sensor_mux_values = mt8183_mux_values, |
| 622 | .version = MTK_THERMAL_V1, |
| 623 | }; |
| 624 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 625 | /* |
developer | 1f80b45 | 2021-12-17 14:26:01 +0800 | [diff] [blame] | 626 | * MT7981 uses AUXADC Channel 11 for raw data access. |
| 627 | */ |
| 628 | static const struct mtk_thermal_data mt7981_thermal_data = { |
| 629 | .auxadc_channel = MT7981_TEMP_AUXADC_CHANNEL, |
| 630 | .num_banks = MT7981_NUM_ZONES, |
| 631 | .num_sensors = MT7981_NUM_SENSORS, |
| 632 | .vts_index = mt7981_vts_index, |
| 633 | .cali_val = MT7981_CALIBRATION, |
| 634 | .num_controller = MT7981_NUM_CONTROLLER, |
| 635 | .controller_offset = mt7981_tc_offset, |
| 636 | .need_switch_bank = true, |
| 637 | .bank_data = { |
| 638 | { |
| 639 | .num_sensors = 1, |
| 640 | .sensors = mt7981_bank_data, |
| 641 | }, |
| 642 | }, |
| 643 | .msr = mt7981_msr, |
| 644 | .adcpnp = mt7981_adcpnp, |
| 645 | .sensor_mux_values = mt7981_mux_values, |
| 646 | .version = MTK_THERMAL_V3, |
| 647 | }; |
| 648 | |
| 649 | /* |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 650 | * MT7986 uses AUXADC Channel 11 for raw data access. |
| 651 | */ |
| 652 | static const struct mtk_thermal_data mt7986_thermal_data = { |
| 653 | .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, |
| 654 | .num_banks = MT7986_NUM_ZONES, |
| 655 | .num_sensors = MT7986_NUM_SENSORS, |
| 656 | .vts_index = mt7986_vts_index, |
| 657 | .cali_val = MT7986_CALIBRATION, |
| 658 | .num_controller = MT7986_NUM_CONTROLLER, |
| 659 | .controller_offset = mt7986_tc_offset, |
| 660 | .need_switch_bank = true, |
| 661 | .bank_data = { |
| 662 | { |
| 663 | .num_sensors = 1, |
| 664 | .sensors = mt7986_bank_data, |
| 665 | }, |
| 666 | }, |
| 667 | .msr = mt7986_msr, |
| 668 | .adcpnp = mt7986_adcpnp, |
| 669 | .sensor_mux_values = mt7986_mux_values, |
| 670 | .version = MTK_THERMAL_V3, |
| 671 | }; |
| 672 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 673 | /** |
| 674 | * raw_to_mcelsius - convert a raw ADC value to mcelsius |
| 675 | * @mt: The thermal controller |
| 676 | * @sensno: sensor number |
| 677 | * @raw: raw ADC value |
| 678 | * |
| 679 | * This converts the raw ADC value to mcelsius using the SoC specific |
| 680 | * calibration constants |
| 681 | */ |
| 682 | static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) |
| 683 | { |
| 684 | s32 tmp; |
| 685 | |
| 686 | raw &= 0xfff; |
| 687 | |
| 688 | tmp = 203450520 << 3; |
| 689 | tmp /= mt->conf->cali_val + mt->o_slope; |
| 690 | tmp /= 10000 + mt->adc_ge; |
| 691 | tmp *= raw - mt->vts[sensno] - 3350; |
| 692 | tmp >>= 3; |
| 693 | |
| 694 | return mt->degc_cali * 500 - tmp; |
| 695 | } |
| 696 | |
| 697 | static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) |
| 698 | { |
| 699 | s32 format_1; |
| 700 | s32 format_2; |
| 701 | s32 g_oe; |
| 702 | s32 g_gain; |
| 703 | s32 g_x_roomt; |
| 704 | s32 tmp; |
| 705 | |
| 706 | if (raw == 0) |
| 707 | return 0; |
| 708 | |
| 709 | raw &= 0xfff; |
| 710 | g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); |
| 711 | g_oe = mt->adc_oe - 512; |
| 712 | format_1 = mt->vts[VTS2] + 3105 - g_oe; |
| 713 | format_2 = (mt->degc_cali * 10) >> 1; |
| 714 | g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; |
| 715 | |
| 716 | tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; |
| 717 | tmp = tmp * 10 * 100 / 11; |
| 718 | |
| 719 | if (mt->o_slope_sign == 0) |
| 720 | tmp = tmp / (165 - mt->o_slope); |
| 721 | else |
| 722 | tmp = tmp / (165 + mt->o_slope); |
| 723 | |
| 724 | return (format_2 - tmp) * 100; |
| 725 | } |
| 726 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 727 | static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) |
| 728 | { |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 729 | s32 tmp; |
| 730 | |
| 731 | if (raw == 0) |
| 732 | return 0; |
| 733 | |
| 734 | raw &= 0xfff; |
developer | baf36c7 | 2021-07-19 15:44:23 +0800 | [diff] [blame] | 735 | tmp = 100000 * 15 / 16 * 10000; |
| 736 | tmp /= 4096 - 512 + mt->adc_ge; |
| 737 | tmp /= 1490; |
| 738 | tmp *= raw - mt->vts[sensno] - 2900; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 739 | |
developer | baf36c7 | 2021-07-19 15:44:23 +0800 | [diff] [blame] | 740 | return mt->degc_cali * 500 - tmp; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 741 | } |
| 742 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 743 | /** |
| 744 | * mtk_thermal_get_bank - get bank |
| 745 | * @bank: The bank |
| 746 | * |
| 747 | * The bank registers are banked, we have to select a bank in the |
| 748 | * PTPCORESEL register to access it. |
| 749 | */ |
| 750 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) |
| 751 | { |
| 752 | struct mtk_thermal *mt = bank->mt; |
| 753 | u32 val; |
| 754 | |
| 755 | if (mt->conf->need_switch_bank) { |
| 756 | mutex_lock(&mt->lock); |
| 757 | |
| 758 | val = readl(mt->thermal_base + PTPCORESEL); |
| 759 | val &= ~0xf; |
| 760 | val |= bank->id; |
| 761 | writel(val, mt->thermal_base + PTPCORESEL); |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | /** |
| 766 | * mtk_thermal_put_bank - release bank |
| 767 | * @bank: The bank |
| 768 | * |
| 769 | * release a bank previously taken with mtk_thermal_get_bank, |
| 770 | */ |
| 771 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) |
| 772 | { |
| 773 | struct mtk_thermal *mt = bank->mt; |
| 774 | |
| 775 | if (mt->conf->need_switch_bank) |
| 776 | mutex_unlock(&mt->lock); |
| 777 | } |
| 778 | |
| 779 | /** |
| 780 | * mtk_thermal_bank_temperature - get the temperature of a bank |
| 781 | * @bank: The bank |
| 782 | * |
| 783 | * The temperature of a bank is considered the maximum temperature of |
| 784 | * the sensors associated to the bank. |
| 785 | */ |
| 786 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) |
| 787 | { |
| 788 | struct mtk_thermal *mt = bank->mt; |
| 789 | const struct mtk_thermal_data *conf = mt->conf; |
| 790 | int i, temp = INT_MIN, max = INT_MIN; |
| 791 | u32 raw; |
| 792 | |
| 793 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
| 794 | raw = readl(mt->thermal_base + conf->msr[i]); |
| 795 | |
| 796 | if (mt->conf->version == MTK_THERMAL_V1) { |
| 797 | temp = raw_to_mcelsius_v1( |
| 798 | mt, conf->bank_data[bank->id].sensors[i], raw); |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 799 | } else if (mt->conf->version == MTK_THERMAL_V2) { |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 800 | temp = raw_to_mcelsius_v2( |
| 801 | mt, conf->bank_data[bank->id].sensors[i], raw); |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 802 | } else { |
| 803 | temp = raw_to_mcelsius_v3( |
| 804 | mt, conf->bank_data[bank->id].sensors[i], raw); |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 805 | } |
| 806 | |
| 807 | /* |
| 808 | * The first read of a sensor often contains very high bogus |
| 809 | * temperature value. Filter these out so that the system does |
| 810 | * not immediately shut down. |
| 811 | */ |
| 812 | if (temp > 200000) |
| 813 | temp = 0; |
| 814 | |
| 815 | if (temp > max) |
| 816 | max = temp; |
| 817 | } |
| 818 | |
| 819 | return max; |
| 820 | } |
| 821 | |
| 822 | static int mtk_read_temp(void *data, int *temperature) |
| 823 | { |
| 824 | struct mtk_thermal *mt = data; |
| 825 | int i; |
| 826 | int tempmax = INT_MIN; |
| 827 | |
| 828 | for (i = 0; i < mt->conf->num_banks; i++) { |
| 829 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
| 830 | |
| 831 | mtk_thermal_get_bank(bank); |
| 832 | |
| 833 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); |
| 834 | |
| 835 | mtk_thermal_put_bank(bank); |
| 836 | } |
| 837 | |
| 838 | *temperature = tempmax; |
| 839 | |
| 840 | return 0; |
| 841 | } |
| 842 | |
| 843 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { |
| 844 | .get_temp = mtk_read_temp, |
| 845 | }; |
| 846 | |
| 847 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, |
| 848 | u32 apmixed_phys_base, u32 auxadc_phys_base, |
| 849 | int ctrl_id) |
| 850 | { |
| 851 | struct mtk_thermal_bank *bank = &mt->banks[num]; |
| 852 | const struct mtk_thermal_data *conf = mt->conf; |
| 853 | int i; |
| 854 | |
| 855 | int offset = mt->conf->controller_offset[ctrl_id]; |
| 856 | void __iomem *controller_base = mt->thermal_base + offset; |
| 857 | |
| 858 | bank->id = num; |
| 859 | bank->mt = mt; |
| 860 | |
| 861 | mtk_thermal_get_bank(bank); |
| 862 | |
| 863 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ |
| 864 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); |
| 865 | |
| 866 | /* |
| 867 | * filt interval is 1 * 46.540us = 46.54us, |
| 868 | * sen interval is 429 * 46.540us = 19.96ms |
| 869 | */ |
| 870 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | |
| 871 | TEMP_MONCTL2_SENSOR_INTERVAL(429), |
| 872 | controller_base + TEMP_MONCTL2); |
| 873 | |
| 874 | /* poll is set to 10u */ |
| 875 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), |
| 876 | controller_base + TEMP_AHBPOLL); |
| 877 | |
| 878 | /* temperature sampling control, 1 sample */ |
| 879 | writel(0x0, controller_base + TEMP_MSRCTL0); |
| 880 | |
| 881 | /* exceed this polling time, IRQ would be inserted */ |
| 882 | writel(0xffffffff, controller_base + TEMP_AHBTO); |
| 883 | |
| 884 | /* number of interrupts per event, 1 is enough */ |
| 885 | writel(0x0, controller_base + TEMP_MONIDET0); |
| 886 | writel(0x0, controller_base + TEMP_MONIDET1); |
| 887 | |
| 888 | /* |
| 889 | * The MT8173 thermal controller does not have its own ADC. Instead it |
| 890 | * uses AHB bus accesses to control the AUXADC. To do this the thermal |
| 891 | * controller has to be programmed with the physical addresses of the |
| 892 | * AUXADC registers and with the various bit positions in the AUXADC. |
| 893 | * Also the thermal controller controls a mux in the APMIXEDSYS register |
| 894 | * space. |
| 895 | */ |
| 896 | |
| 897 | /* |
| 898 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) |
| 899 | * automatically by hw |
| 900 | */ |
| 901 | writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); |
| 902 | |
| 903 | /* AHB address for auxadc mux selection */ |
| 904 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, |
| 905 | controller_base + TEMP_ADCMUXADDR); |
| 906 | |
| 907 | if (mt->conf->version == MTK_THERMAL_V1) { |
| 908 | /* AHB address for pnp sensor mux selection */ |
| 909 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, |
| 910 | controller_base + TEMP_PNPMUXADDR); |
| 911 | } |
| 912 | |
| 913 | /* AHB value for auxadc enable */ |
| 914 | writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); |
| 915 | |
| 916 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ |
| 917 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, |
| 918 | controller_base + TEMP_ADCENADDR); |
| 919 | |
| 920 | /* AHB address for auxadc valid bit */ |
| 921 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
| 922 | controller_base + TEMP_ADCVALIDADDR); |
| 923 | |
| 924 | /* AHB address for auxadc voltage output */ |
| 925 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
| 926 | controller_base + TEMP_ADCVOLTADDR); |
| 927 | |
| 928 | /* read valid & voltage are at the same register */ |
| 929 | writel(0x0, controller_base + TEMP_RDCTRL); |
| 930 | |
| 931 | /* indicate where the valid bit is */ |
| 932 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), |
| 933 | controller_base + TEMP_ADCVALIDMASK); |
| 934 | |
| 935 | /* no shift */ |
| 936 | writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT); |
| 937 | |
| 938 | /* enable auxadc mux write transaction */ |
| 939 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
| 940 | controller_base + TEMP_ADCWRITECTRL); |
| 941 | |
| 942 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
| 943 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], |
| 944 | mt->thermal_base + conf->adcpnp[i]); |
| 945 | |
| 946 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
| 947 | controller_base + TEMP_MONCTL0); |
| 948 | |
| 949 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
| 950 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
| 951 | controller_base + TEMP_ADCWRITECTRL); |
| 952 | |
| 953 | mtk_thermal_put_bank(bank); |
| 954 | } |
| 955 | |
| 956 | static u64 of_get_phys_base(struct device_node *np) |
| 957 | { |
| 958 | u64 size64; |
| 959 | const __be32 *regaddr_p; |
| 960 | |
| 961 | regaddr_p = of_get_address(np, 0, &size64, NULL); |
| 962 | if (!regaddr_p) |
| 963 | return OF_BAD_ADDR; |
| 964 | |
| 965 | return of_translate_address(np, regaddr_p); |
| 966 | } |
| 967 | |
| 968 | static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) |
| 969 | { |
| 970 | int i; |
| 971 | |
| 972 | if (!(buf[0] & CALIB_BUF0_VALID_V1)) |
| 973 | return -EINVAL; |
| 974 | |
| 975 | mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); |
| 976 | |
| 977 | for (i = 0; i < mt->conf->num_sensors; i++) { |
| 978 | switch (mt->conf->vts_index[i]) { |
| 979 | case VTS1: |
| 980 | mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); |
| 981 | break; |
| 982 | case VTS2: |
| 983 | mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); |
| 984 | break; |
| 985 | case VTS3: |
| 986 | mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); |
| 987 | break; |
| 988 | case VTS4: |
| 989 | mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); |
| 990 | break; |
| 991 | case VTS5: |
| 992 | mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); |
| 993 | break; |
| 994 | case VTSABB: |
| 995 | mt->vts[VTSABB] = |
| 996 | CALIB_BUF2_VTS_TSABB_V1(buf[2]); |
| 997 | break; |
| 998 | default: |
| 999 | break; |
| 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); |
| 1004 | if (CALIB_BUF1_ID_V1(buf[1]) & |
| 1005 | CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) |
| 1006 | mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); |
| 1007 | else |
| 1008 | mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); |
| 1009 | |
| 1010 | return 0; |
| 1011 | } |
| 1012 | |
| 1013 | static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf) |
| 1014 | { |
| 1015 | if (!CALIB_BUF1_VALID_V2(buf[1])) |
| 1016 | return -EINVAL; |
| 1017 | |
| 1018 | mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); |
| 1019 | mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); |
| 1020 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); |
| 1021 | mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); |
| 1022 | mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); |
| 1023 | mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); |
| 1024 | mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); |
| 1025 | mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); |
| 1026 | |
| 1027 | return 0; |
| 1028 | } |
| 1029 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 1030 | static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) |
| 1031 | { |
| 1032 | if (!CALIB_BUF1_VALID_V3(buf[1])) |
| 1033 | return -EINVAL; |
| 1034 | |
| 1035 | mt->adc_oe = CALIB_BUF0_ADC_OE_V3(buf[0]); |
| 1036 | mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); |
| 1037 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); |
| 1038 | mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); |
| 1039 | mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); |
| 1040 | mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); |
| 1041 | mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); |
| 1042 | mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); |
| 1043 | |
| 1044 | if (CALIB_BUF1_ID_V3(buf[1]) == 0) |
| 1045 | mt->o_slope = 0; |
| 1046 | |
| 1047 | return 0; |
| 1048 | } |
| 1049 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1050 | static int mtk_thermal_get_calibration_data(struct device *dev, |
| 1051 | struct mtk_thermal *mt) |
| 1052 | { |
| 1053 | struct nvmem_cell *cell; |
| 1054 | u32 *buf; |
| 1055 | size_t len; |
| 1056 | int i, ret = 0; |
| 1057 | |
| 1058 | /* Start with default values */ |
| 1059 | mt->adc_ge = 512; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 1060 | mt->adc_oe = 512; |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1061 | for (i = 0; i < mt->conf->num_sensors; i++) |
| 1062 | mt->vts[i] = 260; |
| 1063 | mt->degc_cali = 40; |
| 1064 | mt->o_slope = 0; |
| 1065 | |
| 1066 | cell = nvmem_cell_get(dev, "calibration-data"); |
| 1067 | if (IS_ERR(cell)) { |
| 1068 | if (PTR_ERR(cell) == -EPROBE_DEFER) |
| 1069 | return PTR_ERR(cell); |
| 1070 | return 0; |
| 1071 | } |
| 1072 | |
| 1073 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 1074 | |
| 1075 | nvmem_cell_put(cell); |
| 1076 | |
| 1077 | if (IS_ERR(buf)) |
| 1078 | return PTR_ERR(buf); |
| 1079 | |
| 1080 | if (len < 3 * sizeof(u32)) { |
| 1081 | dev_warn(dev, "invalid calibration data\n"); |
| 1082 | ret = -EINVAL; |
| 1083 | goto out; |
| 1084 | } |
| 1085 | |
| 1086 | if (mt->conf->version == MTK_THERMAL_V1) |
| 1087 | ret = mtk_thermal_extract_efuse_v1(mt, buf); |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 1088 | else if (mt->conf->version == MTK_THERMAL_V2) |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1089 | ret = mtk_thermal_extract_efuse_v2(mt, buf); |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 1090 | else |
| 1091 | ret = mtk_thermal_extract_efuse_v3(mt, buf); |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1092 | |
| 1093 | if (ret) { |
| 1094 | dev_info(dev, "Device not calibrated, using default calibration values\n"); |
| 1095 | ret = 0; |
| 1096 | } |
| 1097 | |
| 1098 | out: |
| 1099 | kfree(buf); |
| 1100 | |
| 1101 | return ret; |
| 1102 | } |
| 1103 | |
| 1104 | static const struct of_device_id mtk_thermal_of_match[] = { |
| 1105 | { |
| 1106 | .compatible = "mediatek,mt8173-thermal", |
| 1107 | .data = (void *)&mt8173_thermal_data, |
| 1108 | }, |
| 1109 | { |
| 1110 | .compatible = "mediatek,mt2701-thermal", |
| 1111 | .data = (void *)&mt2701_thermal_data, |
| 1112 | }, |
| 1113 | { |
| 1114 | .compatible = "mediatek,mt2712-thermal", |
| 1115 | .data = (void *)&mt2712_thermal_data, |
| 1116 | }, |
| 1117 | { |
| 1118 | .compatible = "mediatek,mt7622-thermal", |
| 1119 | .data = (void *)&mt7622_thermal_data, |
| 1120 | }, |
| 1121 | { |
| 1122 | .compatible = "mediatek,mt8183-thermal", |
| 1123 | .data = (void *)&mt8183_thermal_data, |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 1124 | }, |
| 1125 | { |
developer | 1f80b45 | 2021-12-17 14:26:01 +0800 | [diff] [blame] | 1126 | .compatible = "mediatek,mt7981-thermal", |
| 1127 | .data = (void *)&mt7981_thermal_data, |
| 1128 | }, |
| 1129 | { |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 1130 | .compatible = "mediatek,mt7986-thermal", |
| 1131 | .data = (void *)&mt7986_thermal_data, |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1132 | }, { |
| 1133 | }, |
| 1134 | }; |
| 1135 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); |
| 1136 | |
| 1137 | static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) |
| 1138 | { |
| 1139 | int tmp; |
| 1140 | |
| 1141 | tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); |
| 1142 | tmp &= ~(0x37); |
| 1143 | tmp |= 0x1; |
| 1144 | writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); |
| 1145 | udelay(200); |
| 1146 | } |
| 1147 | |
| 1148 | static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, |
| 1149 | void __iomem *auxadc_base) |
| 1150 | { |
| 1151 | int tmp; |
| 1152 | |
| 1153 | writel(0x800, auxadc_base + AUXADC_CON1_SET_V); |
| 1154 | writel(0x1, mt->thermal_base + TEMP_MONCTL0); |
| 1155 | tmp = readl(mt->thermal_base + TEMP_MSRCTL1); |
| 1156 | writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); |
| 1157 | } |
| 1158 | |
| 1159 | static int mtk_thermal_probe(struct platform_device *pdev) |
| 1160 | { |
| 1161 | int ret, i, ctrl_id; |
| 1162 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; |
| 1163 | struct mtk_thermal *mt; |
| 1164 | struct resource *res; |
| 1165 | u64 auxadc_phys_base, apmixed_phys_base; |
| 1166 | struct thermal_zone_device *tzdev; |
| 1167 | void __iomem *apmixed_base, *auxadc_base; |
| 1168 | |
| 1169 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); |
| 1170 | if (!mt) |
| 1171 | return -ENOMEM; |
| 1172 | |
| 1173 | mt->conf = of_device_get_match_data(&pdev->dev); |
| 1174 | |
| 1175 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
| 1176 | if (IS_ERR(mt->clk_peri_therm)) |
| 1177 | return PTR_ERR(mt->clk_peri_therm); |
| 1178 | |
| 1179 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); |
| 1180 | if (IS_ERR(mt->clk_auxadc)) |
| 1181 | return PTR_ERR(mt->clk_auxadc); |
| 1182 | |
developer | df32d11 | 2021-08-29 11:58:01 +0800 | [diff] [blame] | 1183 | if (mt->conf->version == MTK_THERMAL_V3) { |
| 1184 | mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k"); |
| 1185 | if (IS_ERR(mt->clk_adc_32k)) |
| 1186 | return PTR_ERR(mt->clk_adc_32k); |
| 1187 | } |
| 1188 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1189 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1190 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); |
| 1191 | if (IS_ERR(mt->thermal_base)) |
| 1192 | return PTR_ERR(mt->thermal_base); |
| 1193 | |
| 1194 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); |
| 1195 | if (ret) |
| 1196 | return ret; |
| 1197 | |
| 1198 | mutex_init(&mt->lock); |
| 1199 | |
| 1200 | mt->dev = &pdev->dev; |
| 1201 | |
| 1202 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); |
| 1203 | if (!auxadc) { |
| 1204 | dev_err(&pdev->dev, "missing auxadc node\n"); |
| 1205 | return -ENODEV; |
| 1206 | } |
| 1207 | |
| 1208 | auxadc_base = of_iomap(auxadc, 0); |
| 1209 | auxadc_phys_base = of_get_phys_base(auxadc); |
| 1210 | |
| 1211 | of_node_put(auxadc); |
| 1212 | |
| 1213 | if (auxadc_phys_base == OF_BAD_ADDR) { |
| 1214 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); |
| 1215 | return -EINVAL; |
| 1216 | } |
| 1217 | |
| 1218 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); |
| 1219 | if (!apmixedsys) { |
| 1220 | dev_err(&pdev->dev, "missing apmixedsys node\n"); |
| 1221 | return -ENODEV; |
| 1222 | } |
| 1223 | |
| 1224 | apmixed_base = of_iomap(apmixedsys, 0); |
| 1225 | apmixed_phys_base = of_get_phys_base(apmixedsys); |
| 1226 | |
| 1227 | of_node_put(apmixedsys); |
| 1228 | |
| 1229 | if (apmixed_phys_base == OF_BAD_ADDR) { |
| 1230 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); |
| 1231 | return -EINVAL; |
| 1232 | } |
| 1233 | |
| 1234 | ret = device_reset_optional(&pdev->dev); |
| 1235 | if (ret) |
| 1236 | return ret; |
| 1237 | |
developer | df32d11 | 2021-08-29 11:58:01 +0800 | [diff] [blame] | 1238 | if (mt->conf->version == MTK_THERMAL_V3) { |
| 1239 | ret = clk_prepare_enable(mt->clk_adc_32k); |
| 1240 | if (ret) { |
| 1241 | dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret); |
| 1242 | return ret; |
| 1243 | } |
| 1244 | } |
| 1245 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1246 | ret = clk_prepare_enable(mt->clk_auxadc); |
| 1247 | if (ret) { |
| 1248 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); |
developer | df32d11 | 2021-08-29 11:58:01 +0800 | [diff] [blame] | 1249 | goto err_disable_clk_adc_32k; |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1250 | } |
| 1251 | |
| 1252 | ret = clk_prepare_enable(mt->clk_peri_therm); |
| 1253 | if (ret) { |
| 1254 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); |
| 1255 | goto err_disable_clk_auxadc; |
| 1256 | } |
| 1257 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 1258 | if (mt->conf->version == MTK_THERMAL_V2 || |
| 1259 | mt->conf->version == MTK_THERMAL_V3) { |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1260 | mtk_thermal_turn_on_buffer(apmixed_base); |
| 1261 | mtk_thermal_release_periodic_ts(mt, auxadc_base); |
| 1262 | } |
| 1263 | |
| 1264 | for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) |
| 1265 | for (i = 0; i < mt->conf->num_banks; i++) |
| 1266 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, |
| 1267 | auxadc_phys_base, ctrl_id); |
| 1268 | |
| 1269 | platform_set_drvdata(pdev, mt); |
| 1270 | |
| 1271 | tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, |
| 1272 | &mtk_thermal_ops); |
| 1273 | if (IS_ERR(tzdev)) { |
| 1274 | ret = PTR_ERR(tzdev); |
| 1275 | goto err_disable_clk_peri_therm; |
| 1276 | } |
| 1277 | |
| 1278 | return 0; |
| 1279 | |
| 1280 | err_disable_clk_peri_therm: |
| 1281 | clk_disable_unprepare(mt->clk_peri_therm); |
| 1282 | err_disable_clk_auxadc: |
| 1283 | clk_disable_unprepare(mt->clk_auxadc); |
developer | df32d11 | 2021-08-29 11:58:01 +0800 | [diff] [blame] | 1284 | err_disable_clk_adc_32k: |
| 1285 | if (mt->conf->version == MTK_THERMAL_V3) |
| 1286 | clk_disable_unprepare(mt->clk_adc_32k); |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1287 | |
| 1288 | return ret; |
| 1289 | } |
| 1290 | |
| 1291 | static int mtk_thermal_remove(struct platform_device *pdev) |
| 1292 | { |
| 1293 | struct mtk_thermal *mt = platform_get_drvdata(pdev); |
| 1294 | |
| 1295 | clk_disable_unprepare(mt->clk_peri_therm); |
| 1296 | clk_disable_unprepare(mt->clk_auxadc); |
| 1297 | |
developer | df32d11 | 2021-08-29 11:58:01 +0800 | [diff] [blame] | 1298 | if (mt->conf->version == MTK_THERMAL_V3) |
| 1299 | clk_disable_unprepare(mt->clk_adc_32k); |
| 1300 | |
developer | aedf420 | 2021-06-12 11:52:43 +0800 | [diff] [blame] | 1301 | return 0; |
| 1302 | } |
| 1303 | |
| 1304 | static struct platform_driver mtk_thermal_driver = { |
| 1305 | .probe = mtk_thermal_probe, |
| 1306 | .remove = mtk_thermal_remove, |
| 1307 | .driver = { |
| 1308 | .name = "mtk-thermal", |
| 1309 | .of_match_table = mtk_thermal_of_match, |
| 1310 | }, |
| 1311 | }; |
| 1312 | |
| 1313 | module_platform_driver(mtk_thermal_driver); |
| 1314 | |
| 1315 | MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>"); |
| 1316 | MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>"); |
| 1317 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); |
| 1318 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
| 1319 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
| 1320 | MODULE_DESCRIPTION("Mediatek thermal driver"); |
| 1321 | MODULE_LICENSE("GPL v2"); |