developer | 2908908 | 2023-05-25 12:12:40 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* FILE NAME: en8801sc.c |
| 3 | * PURPOSE: |
| 4 | * EN8801SC phy driver for Linux |
| 5 | * NOTES: |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | /* INCLUDE FILE DECLARATIONS |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/string.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/unistd.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/netdevice.h> |
| 20 | #include <linux/etherdevice.h> |
| 21 | #include <linux/skbuff.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/mm.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/mii.h> |
| 26 | #include <linux/ethtool.h> |
| 27 | #include <linux/phy.h> |
| 28 | #include <linux/delay.h> |
| 29 | |
| 30 | #include <linux/uaccess.h> |
| 31 | #include <linux/version.h> |
| 32 | #if (KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE) |
| 33 | #include <linux/of_gpio.h> |
| 34 | #include <linux/gpio/consumer.h> |
| 35 | #endif |
| 36 | |
| 37 | #include "en8801sc.h" |
| 38 | |
| 39 | MODULE_DESCRIPTION("Airoha EN8801S PHY drivers for MediaTek SoC"); |
| 40 | MODULE_AUTHOR("Airoha"); |
| 41 | MODULE_LICENSE("GPL"); |
| 42 | |
| 43 | #define airoha_mdio_lock(bus) mutex_lock(&((bus)->mdio_lock)) |
| 44 | #define airoha_mdio_unlock(bus) mutex_unlock(&((bus)->mdio_lock)) |
| 45 | |
| 46 | #if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE) |
| 47 | #define phydev_mdio_bus(_dev) (_dev->bus) |
| 48 | #define phydev_phy_addr(_dev) (_dev->addr) |
| 49 | #define phydev_dev(_dev) (&_dev->dev) |
| 50 | #define phydev_pbus_addr(dev) ((dev)->addr + 1) |
| 51 | #else |
| 52 | #define phydev_mdio_bus(_dev) (_dev->mdio.bus) |
| 53 | #define phydev_phy_addr(_dev) (_dev->mdio.addr) |
| 54 | #define phydev_dev(_dev) (&_dev->mdio.dev) |
| 55 | #define phydev_pbus_addr(dev) ((dev)->mdio.addr + 1) |
| 56 | #endif |
| 57 | |
| 58 | enum { |
| 59 | PHY_STATE_DONE = 0, |
| 60 | PHY_STATE_INIT = 1, |
| 61 | PHY_STATE_PROCESS = 2, |
| 62 | PHY_STATE_FAIL = 3, |
| 63 | }; |
| 64 | |
| 65 | struct en8801s_priv { |
| 66 | bool first_init; |
| 67 | u16 count; |
| 68 | #if (KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE) |
| 69 | struct gpio_desc *hw_reset; |
| 70 | #endif |
| 71 | }; |
| 72 | |
| 73 | /* |
| 74 | The following led_cfg example is for reference only. |
| 75 | LED5 1000M/LINK/ACT (GPIO5) <-> BASE_T_LED0, |
| 76 | LED6 10/100M/LINK/ACT (GPIO9) <-> BASE_T_LED1, |
| 77 | LED4 100M/LINK/ACT (GPIO8) <-> BASE_T_LED2, |
| 78 | */ |
| 79 | /* User-defined.B */ |
| 80 | #define AIR_LED_SUPPORT |
| 81 | #ifdef AIR_LED_SUPPORT |
| 82 | static const struct AIR_BASE_T_LED_CFG_S led_cfg[4] = { |
| 83 | /* |
| 84 | * {LED Enable, GPIO, LED Polarity, LED ON, LED Blink} |
| 85 | */ |
| 86 | /* BASE-T LED0 */ |
| 87 | {LED_ENABLE, 5, AIR_ACTIVE_LOW, |
| 88 | BASE_T_LED0_ON_CFG, BASE_T_LED0_BLK_CFG}, |
| 89 | /* BASE-T LED1 */ |
| 90 | {LED_ENABLE, 9, AIR_ACTIVE_LOW, |
| 91 | BASE_T_LED1_ON_CFG, BASE_T_LED1_BLK_CFG}, |
| 92 | /* BASE-T LED2 */ |
| 93 | {LED_ENABLE, 8, AIR_ACTIVE_LOW, |
| 94 | BASE_T_LED2_ON_CFG, BASE_T_LED2_BLK_CFG}, |
| 95 | /* BASE-T LED3 */ |
| 96 | {LED_DISABLE, 1, AIR_ACTIVE_LOW, |
| 97 | BASE_T_LED3_ON_CFG, BASE_T_LED3_BLK_CFG}, |
| 98 | }; |
| 99 | static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M; |
| 100 | #endif |
| 101 | |
| 102 | /* User-defined.E */ |
| 103 | |
| 104 | /************************************************************************ |
| 105 | * F U N C T I O N S |
| 106 | ************************************************************************/ |
| 107 | static unsigned int airoha_cl22_read(struct mii_bus *ebus, int phy_addr, |
| 108 | unsigned int phy_register, unsigned int *read_data) |
| 109 | { |
| 110 | *read_data = mdiobus_read(ebus, phy_addr, phy_register); |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | static int airoha_cl22_write(struct mii_bus *ebus, int phy_addr, |
| 115 | unsigned int phy_register, unsigned int write_data) |
| 116 | { |
| 117 | int ret = 0; |
| 118 | struct device *dev = &ebus->dev; |
| 119 | |
| 120 | ret = mdiobus_write(ebus, phy_addr, phy_register, write_data); |
| 121 | if (ret < 0) { |
| 122 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 123 | return ret; |
| 124 | } |
| 125 | |
| 126 | return ret; |
| 127 | } |
| 128 | |
| 129 | static int __airoha_cl45_write(struct mii_bus *bus, int port, |
| 130 | u32 devad, u32 reg, u16 val) |
| 131 | { |
| 132 | int ret = 0; |
| 133 | struct device *dev = &bus->dev; |
| 134 | |
| 135 | ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad); |
| 136 | if (ret < 0) { |
| 137 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 138 | return ret; |
| 139 | } |
| 140 | ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg); |
| 141 | if (ret < 0) { |
| 142 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 143 | return ret; |
| 144 | } |
| 145 | ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, |
| 146 | MMD_OP_MODE_DATA | devad); |
| 147 | if (ret < 0) { |
| 148 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 149 | return ret; |
| 150 | } |
| 151 | ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, val); |
| 152 | if (ret < 0) { |
| 153 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 154 | return ret; |
| 155 | } |
| 156 | |
| 157 | return ret; |
| 158 | } |
| 159 | |
| 160 | static int __airoha_cl45_read(struct mii_bus *bus, int port, |
| 161 | u32 devad, u32 reg, u16 *read_data) |
| 162 | { |
| 163 | int ret = 0; |
| 164 | struct device *dev = &bus->dev; |
| 165 | |
| 166 | ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad); |
| 167 | if (ret < 0) { |
| 168 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 169 | return ret; |
| 170 | } |
| 171 | ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg); |
| 172 | if (ret < 0) { |
| 173 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 174 | return ret; |
| 175 | } |
| 176 | ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, |
| 177 | MMD_OP_MODE_DATA | devad); |
| 178 | if (ret < 0) { |
| 179 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 180 | return ret; |
| 181 | } |
| 182 | *read_data = __mdiobus_read(bus, port, MII_MMD_ADDR_DATA_REG); |
| 183 | |
| 184 | return ret; |
| 185 | } |
| 186 | |
| 187 | static int airoha_cl45_write(struct mii_bus *bus, int port, |
| 188 | u32 devad, u32 reg, u16 val) |
| 189 | { |
| 190 | int ret = 0; |
| 191 | |
| 192 | airoha_mdio_lock(bus); |
| 193 | ret = __airoha_cl45_write(bus, port, devad, reg, val); |
| 194 | airoha_mdio_unlock(bus); |
| 195 | |
| 196 | return ret; |
| 197 | } |
| 198 | |
| 199 | static int airoha_cl45_read(struct mii_bus *bus, int port, |
| 200 | u32 devad, u32 reg, u16 *read_data) |
| 201 | { |
| 202 | int ret = 0; |
| 203 | |
| 204 | airoha_mdio_lock(bus); |
| 205 | ret = __airoha_cl45_read(bus, port, devad, reg, read_data); |
| 206 | airoha_mdio_unlock(bus); |
| 207 | |
| 208 | return ret; |
| 209 | } |
| 210 | |
| 211 | static int __airoha_pbus_write(struct mii_bus *ebus, int pbus_id, |
| 212 | unsigned long pbus_address, unsigned long pbus_data) |
| 213 | { |
| 214 | int ret = 0; |
| 215 | struct device *dev = &ebus->dev; |
| 216 | |
| 217 | ret = __mdiobus_write(ebus, pbus_id, 0x1F, |
| 218 | (unsigned int)(pbus_address >> 6)); |
| 219 | if (ret < 0) |
| 220 | return ret; |
| 221 | ret = __mdiobus_write(ebus, pbus_id, |
| 222 | (unsigned int)((pbus_address >> 2) & 0xf), |
| 223 | (unsigned int)(pbus_data & 0xFFFF)); |
| 224 | if (ret < 0) |
| 225 | return ret; |
| 226 | ret = __mdiobus_write(ebus, pbus_id, 0x10, |
| 227 | (unsigned int)(pbus_data >> 16)); |
| 228 | if (ret < 0) |
| 229 | return ret; |
| 230 | return ret; |
| 231 | } |
| 232 | |
| 233 | static unsigned long __airoha_pbus_read(struct mii_bus *ebus, int pbus_id, |
| 234 | unsigned long pbus_address) |
| 235 | { |
| 236 | unsigned long pbus_data; |
| 237 | unsigned int pbus_data_low, pbus_data_high; |
| 238 | int ret = 0; |
| 239 | struct device *dev = &ebus->dev; |
| 240 | |
| 241 | ret = __mdiobus_write(ebus, pbus_id, 0x1F, |
| 242 | (unsigned int)(pbus_address >> 6)); |
| 243 | if (ret < 0) { |
| 244 | dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret); |
| 245 | return INVALID_DATA; |
| 246 | } |
| 247 | pbus_data_low = __mdiobus_read(ebus, pbus_id, |
| 248 | (unsigned int)((pbus_address >> 2) & 0xf)); |
| 249 | pbus_data_high = __mdiobus_read(ebus, pbus_id, 0x10); |
| 250 | pbus_data = (pbus_data_high << 16) + pbus_data_low; |
| 251 | return pbus_data; |
| 252 | } |
| 253 | |
| 254 | static int airoha_pbus_write(struct mii_bus *ebus, int pbus_id, |
| 255 | unsigned long pbus_address, unsigned long pbus_data) |
| 256 | { |
| 257 | int ret = 0; |
| 258 | |
| 259 | airoha_mdio_lock(ebus); |
| 260 | ret = __airoha_pbus_write(ebus, pbus_id, pbus_address, pbus_data); |
| 261 | airoha_mdio_unlock(ebus); |
| 262 | |
| 263 | return ret; |
| 264 | } |
| 265 | |
| 266 | static unsigned long airoha_pbus_read(struct mii_bus *ebus, int pbus_id, |
| 267 | unsigned long pbus_address) |
| 268 | { |
| 269 | unsigned long pbus_data; |
| 270 | |
| 271 | airoha_mdio_lock(ebus); |
| 272 | pbus_data = __airoha_pbus_read(ebus, pbus_id, pbus_address); |
| 273 | airoha_mdio_unlock(ebus); |
| 274 | |
| 275 | return pbus_data; |
| 276 | } |
| 277 | |
| 278 | /* Airoha Token Ring Write function */ |
| 279 | static int airoha_tr_reg_write(struct phy_device *phydev, |
| 280 | unsigned long tr_address, unsigned long tr_data) |
| 281 | { |
| 282 | int ret = 0; |
| 283 | int phy_addr = phydev_phy_addr(phydev); |
| 284 | struct mii_bus *ebus = phydev_mdio_bus(phydev); |
| 285 | |
| 286 | airoha_mdio_lock(ebus); |
| 287 | ret = __mdiobus_write(ebus, phy_addr, 0x1F, 0x52b5); /* page select */ |
| 288 | ret = __mdiobus_write(ebus, phy_addr, 0x11, |
| 289 | (unsigned int)(tr_data & 0xffff)); |
| 290 | ret = __mdiobus_write(ebus, phy_addr, 0x12, |
| 291 | (unsigned int)(tr_data >> 16)); |
| 292 | ret = __mdiobus_write(ebus, phy_addr, 0x10, |
| 293 | (unsigned int)(tr_address | TrReg_WR)); |
| 294 | ret = __mdiobus_write(ebus, phy_addr, 0x1F, 0x0); /* page resetore */ |
| 295 | airoha_mdio_unlock(ebus); |
| 296 | |
| 297 | return ret; |
| 298 | } |
| 299 | |
| 300 | #ifdef AIR_LED_SUPPORT |
| 301 | static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity, |
| 302 | int polar, u16 on_evt, u16 blk_evt) |
| 303 | { |
| 304 | int ret = 0; |
| 305 | int phy_addr = phydev_phy_addr(phydev); |
| 306 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 307 | |
| 308 | if (polar == AIR_ACTIVE_HIGH) |
| 309 | on_evt |= LED_ON_POL; |
| 310 | else |
| 311 | on_evt &= ~LED_ON_POL; |
| 312 | |
| 313 | ret = airoha_cl45_write(mbus, phy_addr, 0x1f, |
| 314 | LED_ON_CTRL(entity), on_evt | LED_ON_EN); |
| 315 | if (ret < 0) |
| 316 | return ret; |
| 317 | |
| 318 | ret = airoha_cl45_write(mbus, phy_addr, 0x1f, |
| 319 | LED_BLK_CTRL(entity), blk_evt); |
| 320 | if (ret < 0) |
| 321 | return ret; |
| 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | static int airoha_led_set_mode(struct phy_device *phydev, u8 mode) |
| 327 | { |
| 328 | u16 cl45_data; |
| 329 | int err = 0; |
| 330 | int phy_addr = phydev_phy_addr(phydev); |
| 331 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 332 | |
| 333 | err = airoha_cl45_read(mbus, phy_addr, 0x1f, LED_BCR, &cl45_data); |
| 334 | if (err < 0) |
| 335 | return err; |
| 336 | |
| 337 | switch (mode) { |
| 338 | case AIR_LED_MODE_DISABLE: |
| 339 | cl45_data &= ~LED_BCR_EXT_CTRL; |
| 340 | cl45_data &= ~LED_BCR_MODE_MASK; |
| 341 | cl45_data |= LED_BCR_MODE_DISABLE; |
| 342 | break; |
| 343 | case AIR_LED_MODE_USER_DEFINE: |
| 344 | cl45_data |= LED_BCR_EXT_CTRL; |
| 345 | cl45_data |= LED_BCR_CLK_EN; |
| 346 | break; |
| 347 | default: |
| 348 | return -EINVAL; |
| 349 | } |
| 350 | |
| 351 | err = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_BCR, cl45_data); |
| 352 | if (err < 0) |
| 353 | return err; |
| 354 | return 0; |
| 355 | } |
| 356 | |
| 357 | static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state) |
| 358 | { |
| 359 | u16 cl45_data; |
| 360 | int err; |
| 361 | int phy_addr = phydev_phy_addr(phydev); |
| 362 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 363 | |
| 364 | err = airoha_cl45_read(mbus, phy_addr, 0x1f, |
| 365 | LED_ON_CTRL(entity), &cl45_data); |
| 366 | if (err < 0) |
| 367 | return err; |
| 368 | if (state == LED_ENABLE) |
| 369 | cl45_data |= LED_ON_EN; |
| 370 | else |
| 371 | cl45_data &= ~LED_ON_EN; |
| 372 | |
| 373 | err = airoha_cl45_write(mbus, phy_addr, 0x1f, |
| 374 | LED_ON_CTRL(entity), cl45_data); |
| 375 | if (err < 0) |
| 376 | return err; |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | static int en8801s_led_init(struct phy_device *phydev) |
| 381 | { |
| 382 | |
| 383 | unsigned long led_gpio = 0, reg_value = 0; |
| 384 | int ret = 0, led_id; |
| 385 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 386 | int gpio_led_rg[3] = {0x1870, 0x1874, 0x1878}; |
| 387 | u16 cl45_data = led_dur; |
| 388 | struct device *dev = phydev_dev(phydev); |
| 389 | int phy_addr = phydev_phy_addr(phydev); |
| 390 | int pbus_addr = phydev_pbus_addr(phydev); |
| 391 | |
| 392 | ret = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_BLK_DUR, cl45_data); |
| 393 | if (ret < 0) |
| 394 | return ret; |
| 395 | cl45_data >>= 1; |
| 396 | ret = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_ON_DUR, cl45_data); |
| 397 | if (ret < 0) |
| 398 | return ret; |
| 399 | ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE); |
| 400 | if (ret != 0) { |
| 401 | dev_err(dev, "LED fail to set mode, ret %d !\n", ret); |
| 402 | return ret; |
| 403 | } |
| 404 | for (led_id = 0; led_id < EN8801S_LED_COUNT; led_id++) { |
| 405 | reg_value = 0; |
| 406 | ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en); |
| 407 | if (ret != 0) { |
| 408 | dev_err(dev, "LED fail to set state, ret %d !\n", ret); |
| 409 | return ret; |
| 410 | } |
| 411 | if (led_cfg[led_id].en == LED_ENABLE) { |
| 412 | if ((led_cfg[led_id].gpio < 0) |
| 413 | || led_cfg[led_id].gpio > 9) { |
| 414 | dev_err(dev, "GPIO%d is out of range!! GPIO number is 0~9.\n", |
| 415 | led_cfg[led_id].gpio); |
| 416 | return -EIO; |
| 417 | } |
| 418 | led_gpio |= BIT(led_cfg[led_id].gpio); |
| 419 | reg_value = airoha_pbus_read(mbus, pbus_addr, |
| 420 | gpio_led_rg[led_cfg[led_id].gpio / 4]); |
| 421 | LED_SET_GPIO_SEL(led_cfg[led_id].gpio, |
| 422 | led_id, reg_value); |
| 423 | dev_dbg(dev, "[Airoha] gpio%d, reg_value 0x%lx\n", |
| 424 | led_cfg[led_id].gpio, reg_value); |
| 425 | ret = airoha_pbus_write(mbus, pbus_addr, |
| 426 | gpio_led_rg[led_cfg[led_id].gpio / 4], |
| 427 | reg_value); |
| 428 | if (ret < 0) |
| 429 | return ret; |
| 430 | ret = airoha_led_set_usr_def(phydev, led_id, |
| 431 | led_cfg[led_id].pol, |
| 432 | led_cfg[led_id].on_cfg, |
| 433 | led_cfg[led_id].blk_cfg); |
| 434 | if (ret != 0) { |
| 435 | dev_err(dev, "LED fail to set usr def, ret %d !\n", |
| 436 | ret); |
| 437 | return ret; |
| 438 | } |
| 439 | } |
| 440 | } |
| 441 | reg_value = (airoha_pbus_read(mbus, pbus_addr, 0x1880) & ~led_gpio); |
| 442 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1880, reg_value); |
| 443 | if (ret < 0) |
| 444 | return ret; |
| 445 | ret = airoha_pbus_write(mbus, pbus_addr, 0x186c, led_gpio); |
| 446 | if (ret < 0) |
| 447 | return ret; |
| 448 | dev_info(dev, "LED initialize OK !\n"); |
| 449 | return 0; |
| 450 | } |
| 451 | #endif |
| 452 | static int en8801s_phy_process(struct phy_device *phydev) |
| 453 | { |
| 454 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 455 | unsigned long reg_value = 0; |
| 456 | int ret = 0; |
| 457 | int pbus_addr = phydev_pbus_addr(phydev); |
| 458 | |
| 459 | reg_value = airoha_pbus_read(mbus, pbus_addr, 0x19e0); |
| 460 | reg_value |= BIT(0); |
| 461 | ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, reg_value); |
| 462 | if (ret < 0) |
| 463 | return ret; |
| 464 | reg_value = airoha_pbus_read(mbus, pbus_addr, 0x19e0); |
| 465 | reg_value &= ~BIT(0); |
| 466 | ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, reg_value); |
| 467 | if (ret < 0) |
| 468 | return ret; |
| 469 | return ret; |
| 470 | } |
| 471 | |
| 472 | static int en8801s_phase1_init(struct phy_device *phydev) |
| 473 | { |
| 474 | unsigned long pbus_data; |
| 475 | int pbusAddress = EN8801S_PBUS_DEFAULT_ID; |
| 476 | u16 reg_value; |
| 477 | int retry, ret = 0; |
| 478 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 479 | struct device *dev = phydev_dev(phydev); |
| 480 | struct en8801s_priv *priv = phydev->priv; |
| 481 | |
| 482 | #if (KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE) |
| 483 | /* Deassert the reset signal */ |
| 484 | if (priv->hw_reset) |
| 485 | gpiod_set_value(priv->hw_reset, 0); |
| 486 | #endif |
| 487 | priv->count = 1; |
| 488 | msleep(1000); |
| 489 | |
| 490 | retry = MAX_OUI_CHECK; |
| 491 | while (1) { |
| 492 | pbus_data = airoha_pbus_read(mbus, pbusAddress, |
| 493 | EN8801S_RG_ETHER_PHY_OUI); /* PHY OUI */ |
| 494 | if (pbus_data == EN8801S_PBUS_OUI) { |
| 495 | dev_info(dev, "PBUS addr 0x%x: Start initialized.\n", |
| 496 | pbusAddress); |
| 497 | break; |
| 498 | } |
| 499 | pbusAddress = phydev_pbus_addr(phydev); |
| 500 | if (0 == --retry) { |
| 501 | dev_err(dev, "Probe fail !\n"); |
| 502 | return 0; |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | ret = airoha_pbus_write(mbus, pbusAddress, EN8801S_RG_BUCK_CTL, 0x03); |
| 507 | if (ret < 0) |
| 508 | return ret; |
| 509 | mdelay(10); |
| 510 | pbus_data = (airoha_pbus_read(mbus, pbusAddress, EN8801S_RG_LTR_CTL) |
| 511 | & 0xfffffffc) | BIT(2); |
| 512 | ret = airoha_pbus_write(mbus, pbusAddress, |
| 513 | EN8801S_RG_LTR_CTL, pbus_data); |
| 514 | if (ret < 0) |
| 515 | return ret; |
| 516 | mdelay(500); |
| 517 | pbus_data = (pbus_data & ~BIT(2)) | |
| 518 | EN8801S_RX_POLARITY_NORMAL | |
| 519 | EN8801S_TX_POLARITY_NORMAL; |
| 520 | ret = airoha_pbus_write(mbus, pbusAddress, |
| 521 | EN8801S_RG_LTR_CTL, pbus_data); |
| 522 | if (ret < 0) |
| 523 | return ret; |
| 524 | mdelay(500); |
| 525 | |
| 526 | pbus_data = airoha_pbus_read(mbus, pbusAddress, |
| 527 | EN8801S_RG_SMI_ADDR); /* SMI ADDR */ |
| 528 | pbus_data = (pbus_data & 0xffff0000) | |
| 529 | (unsigned long)(phydev_pbus_addr(phydev) << 8) | |
| 530 | (unsigned long)(phydev_phy_addr(phydev)); |
| 531 | dev_info(phydev_dev(phydev), "SMI_ADDR=%lx (renew)\n", pbus_data); |
| 532 | ret = airoha_pbus_write(mbus, pbusAddress, |
| 533 | EN8801S_RG_SMI_ADDR, pbus_data); |
| 534 | mdelay(10); |
| 535 | |
| 536 | retry = MAX_RETRY; |
| 537 | while (1) { |
| 538 | mdelay(10); |
| 539 | reg_value = phy_read(phydev, MII_PHYSID2); |
| 540 | if (reg_value == EN8801S_PHY_ID2) |
| 541 | break; /* wait GPHY ready */ |
| 542 | |
| 543 | retry--; |
| 544 | if (retry == 0) { |
| 545 | dev_err(dev, "Initialize fail !\n"); |
| 546 | return 0; |
| 547 | } |
| 548 | } |
| 549 | /* Software Reset PHY */ |
| 550 | reg_value = phy_read(phydev, MII_BMCR); |
| 551 | reg_value |= BMCR_RESET; |
| 552 | ret = phy_write(phydev, MII_BMCR, reg_value); |
| 553 | if (ret < 0) |
| 554 | return ret; |
| 555 | retry = MAX_RETRY; |
| 556 | do { |
| 557 | mdelay(10); |
| 558 | reg_value = phy_read(phydev, MII_BMCR); |
| 559 | retry--; |
| 560 | if (retry == 0) { |
| 561 | dev_err(dev, "Reset fail !\n"); |
| 562 | return 0; |
| 563 | } |
| 564 | } while (reg_value & BMCR_RESET); |
| 565 | |
| 566 | phydev->dev_flags = PHY_STATE_INIT; |
| 567 | |
| 568 | dev_info(dev, "Phase1 initialize OK ! (%s)\n", EN8801S_DRIVER_VERSION); |
| 569 | |
| 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | static int en8801s_phase2_init(struct phy_device *phydev) |
| 574 | { |
| 575 | union gephy_all_REG_LpiReg1Ch GPHY_RG_LPI_1C; |
| 576 | union gephy_all_REG_dev1Eh_reg324h GPHY_RG_1E_324; |
| 577 | union gephy_all_REG_dev1Eh_reg012h GPHY_RG_1E_012; |
| 578 | union gephy_all_REG_dev1Eh_reg017h GPHY_RG_1E_017; |
| 579 | unsigned long pbus_data; |
| 580 | int phy_addr = phydev_phy_addr(phydev); |
| 581 | int pbus_addr = phydev_pbus_addr(phydev); |
| 582 | u16 cl45_value; |
| 583 | int retry, ret = 0; |
| 584 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 585 | struct device *dev = phydev_dev(phydev); |
| 586 | struct en8801s_priv *priv = phydev->priv; |
| 587 | |
| 588 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1690); |
| 589 | pbus_data |= BIT(31); |
| 590 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1690, pbus_data); |
| 591 | if (ret < 0) |
| 592 | return ret; |
| 593 | |
| 594 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00); |
| 595 | if (ret < 0) |
| 596 | return ret; |
| 597 | ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD801); |
| 598 | if (ret < 0) |
| 599 | return ret; |
| 600 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0, 0x9140); |
| 601 | if (ret < 0) |
| 602 | return ret; |
| 603 | |
| 604 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0003); |
| 605 | if (ret < 0) |
| 606 | return ret; |
| 607 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00); |
| 608 | if (ret < 0) |
| 609 | return ret; |
| 610 | /* Set FCM control */ |
| 611 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x004b); |
| 612 | if (ret < 0) |
| 613 | return ret; |
| 614 | ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007); |
| 615 | if (ret < 0) |
| 616 | return ret; |
| 617 | |
| 618 | ret = airoha_pbus_write(mbus, pbus_addr, 0x142c, 0x05050505); |
| 619 | if (ret < 0) |
| 620 | return ret; |
| 621 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1440); |
| 622 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1440, pbus_data & ~BIT(11)); |
| 623 | if (ret < 0) |
| 624 | return ret; |
| 625 | |
| 626 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1408); |
| 627 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1408, pbus_data | BIT(5)); |
| 628 | if (ret < 0) |
| 629 | return ret; |
| 630 | |
| 631 | /* Set GPHY Perfomance*/ |
| 632 | /* Token Ring */ |
| 633 | ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_15h, 0x0055A0); |
| 634 | if (ret < 0) |
| 635 | return ret; |
| 636 | ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_17h, 0x07FF3F); |
| 637 | if (ret < 0) |
| 638 | return ret; |
| 639 | ret = airoha_tr_reg_write(phydev, RgAddr_PMA_00h, 0x00001E); |
| 640 | if (ret < 0) |
| 641 | return ret; |
| 642 | ret = airoha_tr_reg_write(phydev, RgAddr_PMA_01h, 0x6FB90A); |
| 643 | if (ret < 0) |
| 644 | return ret; |
| 645 | ret = airoha_tr_reg_write(phydev, RgAddr_PMA_17h, 0x060671); |
| 646 | if (ret < 0) |
| 647 | return ret; |
| 648 | ret = airoha_tr_reg_write(phydev, RgAddr_PMA_18h, 0x0E2F00); |
| 649 | if (ret < 0) |
| 650 | return ret; |
| 651 | ret = airoha_tr_reg_write(phydev, RgAddr_TR_26h, 0x444444); |
| 652 | if (ret < 0) |
| 653 | return ret; |
| 654 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_03h, 0x000000); |
| 655 | if (ret < 0) |
| 656 | return ret; |
| 657 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_06h, 0x2EBAEF); |
| 658 | if (ret < 0) |
| 659 | return ret; |
| 660 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_08h, 0x00000B); |
| 661 | if (ret < 0) |
| 662 | return ret; |
| 663 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Ch, 0x00504D); |
| 664 | if (ret < 0) |
| 665 | return ret; |
| 666 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Dh, 0x02314F); |
| 667 | if (ret < 0) |
| 668 | return ret; |
| 669 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Fh, 0x003028); |
| 670 | if (ret < 0) |
| 671 | return ret; |
| 672 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_10h, 0x005010); |
| 673 | if (ret < 0) |
| 674 | return ret; |
| 675 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_11h, 0x040001); |
| 676 | if (ret < 0) |
| 677 | return ret; |
| 678 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_13h, 0x018670); |
| 679 | if (ret < 0) |
| 680 | return ret; |
| 681 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_14h, 0x00024A); |
| 682 | if (ret < 0) |
| 683 | return ret; |
| 684 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Bh, 0x000072); |
| 685 | if (ret < 0) |
| 686 | return ret; |
| 687 | ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Ch, 0x003210); |
| 688 | if (ret < 0) |
| 689 | return ret; |
| 690 | |
| 691 | /* CL22 & CL45 */ |
| 692 | ret = phy_write(phydev, 0x1f, 0x03); |
| 693 | if (ret < 0) |
| 694 | return ret; |
| 695 | GPHY_RG_LPI_1C.DATA = phy_read(phydev, RgAddr_LPI_1Ch); |
| 696 | GPHY_RG_LPI_1C.DataBitField.smi_deton_th = 0x0C; |
| 697 | ret = phy_write(phydev, RgAddr_LPI_1Ch, GPHY_RG_LPI_1C.DATA); |
| 698 | if (ret < 0) |
| 699 | return ret; |
| 700 | ret = phy_write(phydev, RgAddr_LPI_1Ch, 0xC92); |
| 701 | if (ret < 0) |
| 702 | return ret; |
| 703 | ret = phy_write(phydev, RgAddr_AUXILIARY_1Dh, 0x1); |
| 704 | if (ret < 0) |
| 705 | return ret; |
| 706 | ret = phy_write(phydev, 0x1f, 0x0); |
| 707 | if (ret < 0) |
| 708 | return ret; |
| 709 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x120, 0x8014); |
| 710 | if (ret < 0) |
| 711 | return ret; |
| 712 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x122, 0xffff); |
| 713 | if (ret < 0) |
| 714 | return ret; |
| 715 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x123, 0xffff); |
| 716 | if (ret < 0) |
| 717 | return ret; |
| 718 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x144, 0x0200); |
| 719 | if (ret < 0) |
| 720 | return ret; |
| 721 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x14A, 0xEE20); |
| 722 | if (ret < 0) |
| 723 | return ret; |
| 724 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x189, 0x0110); |
| 725 | if (ret < 0) |
| 726 | return ret; |
| 727 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x19B, 0x0111); |
| 728 | if (ret < 0) |
| 729 | return ret; |
| 730 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x234, 0x0181); |
| 731 | if (ret < 0) |
| 732 | return ret; |
| 733 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x238, 0x0120); |
| 734 | if (ret < 0) |
| 735 | return ret; |
| 736 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x239, 0x0117); |
| 737 | if (ret < 0) |
| 738 | return ret; |
| 739 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x268, 0x07F4); |
| 740 | if (ret < 0) |
| 741 | return ret; |
| 742 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x2D1, 0x0733); |
| 743 | if (ret < 0) |
| 744 | return ret; |
| 745 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x323, 0x0011); |
| 746 | if (ret < 0) |
| 747 | return ret; |
| 748 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324, 0x013F); |
| 749 | if (ret < 0) |
| 750 | return ret; |
| 751 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x326, 0x0037); |
| 752 | if (ret < 0) |
| 753 | return ret; |
| 754 | |
| 755 | ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x324, &cl45_value); |
| 756 | if (ret < 0) |
| 757 | return ret; |
| 758 | GPHY_RG_1E_324.DATA = cl45_value; |
| 759 | GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = 0; |
| 760 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324, |
| 761 | GPHY_RG_1E_324.DATA); |
| 762 | if (ret < 0) |
| 763 | return ret; |
| 764 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x19E, 0xC2); |
| 765 | if (ret < 0) |
| 766 | return ret; |
| 767 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x013, 0x0); |
| 768 | if (ret < 0) |
| 769 | return ret; |
| 770 | |
| 771 | /* EFUSE */ |
| 772 | airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40000040); |
| 773 | retry = MAX_RETRY; |
| 774 | while (retry != 0) { |
| 775 | mdelay(1); |
| 776 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08); |
| 777 | if ((pbus_data & BIT(30)) == 0) |
| 778 | break; |
| 779 | |
| 780 | retry--; |
| 781 | } |
| 782 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C38); /* RAW#2 */ |
| 783 | ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x12, &cl45_value); |
| 784 | if (ret < 0) |
| 785 | return ret; |
| 786 | GPHY_RG_1E_012.DATA = cl45_value; |
| 787 | GPHY_RG_1E_012.DataBitField.da_tx_i2mpb_a_tbt = |
| 788 | (u16)(pbus_data & 0x03f); |
| 789 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x12, |
| 790 | GPHY_RG_1E_012.DATA); |
| 791 | if (ret < 0) |
| 792 | return ret; |
| 793 | ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x17, &cl45_value); |
| 794 | if (ret < 0) |
| 795 | return ret; |
| 796 | GPHY_RG_1E_017.DATA = cl45_value; |
| 797 | GPHY_RG_1E_017.DataBitField.da_tx_i2mpb_b_tbt = |
| 798 | (u16)((pbus_data >> 8) & 0x03f); |
| 799 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x17, |
| 800 | GPHY_RG_1E_017.DATA); |
| 801 | if (ret < 0) |
| 802 | return ret; |
| 803 | |
| 804 | airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40400040); |
| 805 | retry = MAX_RETRY; |
| 806 | while (retry != 0) { |
| 807 | mdelay(1); |
| 808 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08); |
| 809 | if ((pbus_data & BIT(30)) == 0) |
| 810 | break; |
| 811 | |
| 812 | retry--; |
| 813 | } |
| 814 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C30); /* RAW#16 */ |
| 815 | GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = |
| 816 | (u16)((pbus_data >> 12) & 0x01); |
| 817 | ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324, |
| 818 | GPHY_RG_1E_324.DATA); |
| 819 | if (ret < 0) |
| 820 | return ret; |
| 821 | #ifdef AIR_LED_SUPPORT |
| 822 | ret = en8801s_led_init(phydev); |
| 823 | if (ret != 0) |
| 824 | dev_err(dev, "en8801s_led_init fail (ret:%d) !\n", ret); |
| 825 | #endif |
| 826 | |
| 827 | ret = airoha_cl45_read(mbus, phy_addr, MDIO_MMD_AN, |
| 828 | MDIO_AN_EEE_ADV, &cl45_value); |
| 829 | if (ret < 0) |
| 830 | return ret; |
| 831 | if (cl45_value == 0) { |
| 832 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1960); |
| 833 | if (0xA == ((pbus_data & 0x07c00000) >> 22)) { |
| 834 | pbus_data = (pbus_data & 0xf83fffff) | (0xC << 22); |
| 835 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 836 | pbus_data); |
| 837 | if (ret < 0) |
| 838 | return ret; |
| 839 | mdelay(10); |
| 840 | pbus_data = (pbus_data & 0xf83fffff) | (0xE << 22); |
| 841 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 842 | pbus_data); |
| 843 | if (ret < 0) |
| 844 | return ret; |
| 845 | mdelay(10); |
| 846 | } |
| 847 | } else { |
| 848 | pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1960); |
| 849 | if (0xE == ((pbus_data & 0x07c00000) >> 22)) { |
| 850 | pbus_data = (pbus_data & 0xf83fffff) | (0xC << 22); |
| 851 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 852 | pbus_data); |
| 853 | if (ret < 0) |
| 854 | return ret; |
| 855 | mdelay(10); |
| 856 | pbus_data = (pbus_data & 0xf83fffff) | (0xA << 22); |
| 857 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 858 | pbus_data); |
| 859 | if (ret < 0) |
| 860 | return ret; |
| 861 | mdelay(10); |
| 862 | } |
| 863 | } |
| 864 | |
| 865 | priv->first_init = false; |
| 866 | dev_info(phydev_dev(phydev), "Phase2 initialize OK !\n"); |
| 867 | return 0; |
| 868 | } |
| 869 | |
| 870 | static int en8801s_read_status(struct phy_device *phydev) |
| 871 | { |
| 872 | int ret = 0, preSpeed = phydev->speed; |
| 873 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 874 | u32 reg_value; |
| 875 | struct device *dev = phydev_dev(phydev); |
| 876 | int pbus_addr = phydev_pbus_addr(phydev); |
| 877 | struct en8801s_priv *priv = phydev->priv; |
| 878 | |
| 879 | ret = genphy_read_status(phydev); |
| 880 | if (phydev->link == LINK_DOWN) |
| 881 | preSpeed = phydev->speed = 0; |
| 882 | |
| 883 | if (phydev->dev_flags == PHY_STATE_PROCESS) { |
| 884 | en8801s_phy_process(phydev); |
| 885 | phydev->dev_flags = PHY_STATE_DONE; |
| 886 | } |
| 887 | |
| 888 | if (phydev->dev_flags == PHY_STATE_INIT) { |
| 889 | dev_dbg(dev, "phydev->link %d, count %d\n", |
| 890 | phydev->link, priv->count); |
| 891 | if ((phydev->link) || (priv->count == 5)) { |
| 892 | ret = en8801s_phase2_init(phydev); |
| 893 | if (ret != 0) { |
| 894 | dev_info(dev, "en8801_phase2_init failed\n"); |
| 895 | phydev->dev_flags = PHY_STATE_FAIL; |
| 896 | return 0; |
| 897 | } |
| 898 | phydev->dev_flags = PHY_STATE_PROCESS; |
| 899 | } |
| 900 | priv->count++; |
| 901 | } |
| 902 | |
| 903 | if ((preSpeed != phydev->speed) && (phydev->link == LINK_UP)) { |
| 904 | preSpeed = phydev->speed; |
| 905 | |
| 906 | if (preSpeed == SPEED_10) { |
| 907 | reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1694); |
| 908 | reg_value |= BIT(31); |
| 909 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1694, |
| 910 | reg_value); |
| 911 | if (ret < 0) |
| 912 | return ret; |
| 913 | phydev->dev_flags = PHY_STATE_PROCESS; |
| 914 | } else { |
| 915 | reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1694); |
| 916 | reg_value &= ~BIT(31); |
| 917 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1694, |
| 918 | reg_value); |
| 919 | if (ret < 0) |
| 920 | return ret; |
| 921 | phydev->dev_flags = PHY_STATE_PROCESS; |
| 922 | } |
| 923 | |
| 924 | airoha_pbus_write(mbus, pbus_addr, 0x0600, |
| 925 | 0x0c000c00); |
| 926 | if (preSpeed == SPEED_1000) { |
| 927 | ret = airoha_pbus_write(mbus, pbus_addr, 0x10, |
| 928 | 0xD801); |
| 929 | if (ret < 0) |
| 930 | return ret; |
| 931 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0, |
| 932 | 0x9140); |
| 933 | if (ret < 0) |
| 934 | return ret; |
| 935 | |
| 936 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, |
| 937 | 0x0003); |
| 938 | if (ret < 0) |
| 939 | return ret; |
| 940 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, |
| 941 | 0x0c000c00); |
| 942 | if (ret < 0) |
| 943 | return ret; |
| 944 | mdelay(2); /* delay 2 ms */ |
| 945 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, |
| 946 | 0x004b); |
| 947 | if (ret < 0) |
| 948 | return ret; |
| 949 | ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, |
| 950 | 0x0007); |
| 951 | if (ret < 0) |
| 952 | return ret; |
| 953 | } else if (preSpeed == SPEED_100) { |
| 954 | ret = airoha_pbus_write(mbus, pbus_addr, 0x10, |
| 955 | 0xD401); |
| 956 | if (ret < 0) |
| 957 | return ret; |
| 958 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0, |
| 959 | 0x9140); |
| 960 | if (ret < 0) |
| 961 | return ret; |
| 962 | |
| 963 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, |
| 964 | 0x0007); |
| 965 | if (ret < 0) |
| 966 | return ret; |
| 967 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, |
| 968 | 0x0c11); |
| 969 | if (ret < 0) |
| 970 | return ret; |
| 971 | mdelay(2); /* delay 2 ms */ |
| 972 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, |
| 973 | 0x0027); |
| 974 | if (ret < 0) |
| 975 | return ret; |
| 976 | ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, |
| 977 | 0x0007); |
| 978 | if (ret < 0) |
| 979 | return ret; |
| 980 | } else if (preSpeed == SPEED_10) { |
| 981 | ret = airoha_pbus_write(mbus, pbus_addr, 0x10, |
| 982 | 0xD001); |
| 983 | if (ret < 0) |
| 984 | return ret; |
| 985 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0, |
| 986 | 0x9140); |
| 987 | if (ret < 0) |
| 988 | return ret; |
| 989 | |
| 990 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, |
| 991 | 0x000b); |
| 992 | if (ret < 0) |
| 993 | return ret; |
| 994 | ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, |
| 995 | 0x0c11); |
| 996 | if (ret < 0) |
| 997 | return ret; |
| 998 | mdelay(2); /* delay 2 ms */ |
| 999 | ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, |
| 1000 | 0x0027); |
| 1001 | if (ret < 0) |
| 1002 | return ret; |
| 1003 | ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, |
| 1004 | 0x0007); |
| 1005 | if (ret < 0) |
| 1006 | return ret; |
| 1007 | } |
| 1008 | } |
| 1009 | return ret; |
| 1010 | } |
| 1011 | |
| 1012 | static int en8801s_probe(struct phy_device *phydev) |
| 1013 | { |
| 1014 | struct en8801s_priv *priv; |
| 1015 | unsigned long phy_addr = phydev_phy_addr(phydev); |
| 1016 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 1017 | struct device *dev = &mbus->dev; |
| 1018 | #if (KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE) |
| 1019 | struct gpio_desc *en8801s_reset; |
| 1020 | int err = 0; |
| 1021 | #else |
| 1022 | struct mdio_device *mdiodev = &phydev->mdio; |
| 1023 | #endif |
| 1024 | |
| 1025 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 1026 | if (!priv) |
| 1027 | return -ENOMEM; |
| 1028 | |
| 1029 | priv->count = 0; |
| 1030 | priv->first_init = true; |
| 1031 | |
| 1032 | #if (KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE) |
| 1033 | /* Assert the optional reset signal */ |
| 1034 | en8801s_reset = gpiod_get_optional(&phydev->dev, |
| 1035 | "reset", GPIOD_OUT_HIGH); |
| 1036 | err = PTR_ERR_OR_ZERO(en8801s_reset); |
| 1037 | if (err) { |
| 1038 | dev_dbg(phydev_dev(phydev), |
| 1039 | "PHY %lx have no reset pin in device tree.\n", |
| 1040 | phy_addr); |
| 1041 | } else { |
| 1042 | dev_dbg(phydev_dev(phydev), |
| 1043 | "Assert PHY %lx HWRST until config_init\n", |
| 1044 | phy_addr); |
| 1045 | priv->hw_reset = en8801s_reset; |
| 1046 | } |
| 1047 | |
| 1048 | #else |
| 1049 | if (mdiodev->reset_gpio) { |
| 1050 | dev_dbg(phydev_dev(phydev), |
| 1051 | "Assert PHY %lx HWRST until phy_init_hw\n", |
| 1052 | phy_addr); |
| 1053 | phy_device_reset(phydev, 1); |
| 1054 | } |
| 1055 | #endif |
| 1056 | |
| 1057 | phydev->priv = priv; |
| 1058 | |
| 1059 | return 0; |
| 1060 | } |
| 1061 | |
| 1062 | #if (KERNEL_VERSION(4, 5, 0) < LINUX_VERSION_CODE) |
| 1063 | static int airoha_mmd_read(struct phy_device *phydev, |
| 1064 | int devad, u16 reg) |
| 1065 | { |
| 1066 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 1067 | int phy_addr = phydev_phy_addr(phydev); |
| 1068 | int ret = 0; |
| 1069 | u16 cl45_value; |
| 1070 | |
| 1071 | ret = __airoha_cl45_read(mbus, phy_addr, devad, reg, &cl45_value); |
| 1072 | if (ret < 0) |
| 1073 | return ret; |
| 1074 | |
| 1075 | return cl45_value; |
| 1076 | } |
| 1077 | |
| 1078 | static int airoha_mmd_write(struct phy_device *phydev, |
| 1079 | int devad, u16 reg, u16 val) |
| 1080 | { |
| 1081 | struct mii_bus *mbus = phydev_mdio_bus(phydev); |
| 1082 | int phy_addr = phydev_phy_addr(phydev); |
| 1083 | int pbus_addr = phydev_pbus_addr(phydev); |
| 1084 | unsigned long pbus_data; |
| 1085 | int ret = 0; |
| 1086 | |
| 1087 | if (MDIO_MMD_AN == devad && MDIO_AN_EEE_ADV == reg) { |
| 1088 | if (val == 0) { |
| 1089 | pbus_data = __airoha_pbus_read(mbus, pbus_addr, 0x1960); |
| 1090 | if (0xA == ((pbus_data & 0x07c00000) >> 22)) { |
| 1091 | pbus_data = (pbus_data & 0xf83fffff) | |
| 1092 | (0xC << 22); |
| 1093 | __airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 1094 | pbus_data); |
| 1095 | mdelay(10); |
| 1096 | pbus_data = (pbus_data & 0xf83fffff) | |
| 1097 | (0xE << 22); |
| 1098 | __airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 1099 | pbus_data); |
| 1100 | mdelay(10); |
| 1101 | } |
| 1102 | } else { |
| 1103 | pbus_data = __airoha_pbus_read(mbus, pbus_addr, 0x1960); |
| 1104 | if (0xE == ((pbus_data & 0x07c00000) >> 22)) { |
| 1105 | pbus_data = (pbus_data & 0xf83fffff) | |
| 1106 | (0xC << 22); |
| 1107 | __airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 1108 | pbus_data); |
| 1109 | mdelay(10); |
| 1110 | pbus_data = (pbus_data & 0xf83fffff) | |
| 1111 | (0xA << 22); |
| 1112 | __airoha_pbus_write(mbus, pbus_addr, 0x1960, |
| 1113 | pbus_data); |
| 1114 | mdelay(10); |
| 1115 | } |
| 1116 | } |
| 1117 | } |
| 1118 | |
| 1119 | ret = __airoha_cl45_write(mbus, phy_addr, devad, reg, val); |
| 1120 | if (ret < 0) |
| 1121 | return ret; |
| 1122 | |
| 1123 | return 0; |
| 1124 | } |
| 1125 | #endif |
| 1126 | |
| 1127 | static struct phy_driver Airoha_driver[] = { |
| 1128 | { |
| 1129 | .phy_id = EN8801SC_PHY_ID, |
| 1130 | .name = "Airoha EN8801SC", |
| 1131 | .phy_id_mask = 0x0ffffff0, |
| 1132 | .features = PHY_GBIT_FEATURES, |
| 1133 | .probe = en8801s_probe, |
| 1134 | .config_init = en8801s_phase1_init, |
| 1135 | .config_aneg = genphy_config_aneg, |
| 1136 | .read_status = en8801s_read_status, |
| 1137 | .suspend = genphy_suspend, |
| 1138 | .resume = genphy_resume, |
| 1139 | #if (KERNEL_VERSION(4, 5, 0) < LINUX_VERSION_CODE) |
| 1140 | .read_mmd = airoha_mmd_read, |
| 1141 | .write_mmd = airoha_mmd_write, |
| 1142 | #endif |
| 1143 | } |
| 1144 | }; |
| 1145 | |
| 1146 | module_phy_driver(Airoha_driver); |
| 1147 | |
| 1148 | static struct mdio_device_id __maybe_unused Airoha_tbl[] = { |
| 1149 | { EN8801SC_PHY_ID, 0x0ffffff0 }, |
| 1150 | { } |
| 1151 | }; |
| 1152 | |
| 1153 | MODULE_DEVICE_TABLE(mdio, Airoha_tbl); |