| developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7981-fpga.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7981 FPGA"; |
| 5 | compatible = "mediatek,mt7981-fpga-emmc"; |
| 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000 \ |
| developer | dd4f717 | 2023-03-15 10:45:06 +0800 | [diff] [blame] | 9 | root=PARTLABEL=rootfs rootwait \ |
| 10 | rootfstype=squashfs,f2fs"; |
| developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 11 | }; |
| 12 | |
| 13 | memory { |
| 14 | // fpga ddr2: 128MB*2 |
| 15 | reg = <0 0x40000000 0 0x10000000>; |
| 16 | }; |
| 17 | |
| 18 | wsys_adie: wsys_adie@0 { |
| 19 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 20 | compatible = "mediatek,rebb-mt7981-adie"; |
| 21 | adie_id = <7976>; |
| 22 | sku_type = <3000>; |
| 23 | }; |
| 24 | |
| 25 | reg_3p3v: regulator-3p3v { |
| 26 | compatible = "regulator-fixed"; |
| 27 | regulator-name = "fixed-3.3V"; |
| 28 | regulator-min-microvolt = <3300000>; |
| 29 | regulator-max-microvolt = <3300000>; |
| 30 | regulator-boot-on; |
| 31 | regulator-always-on; |
| 32 | }; |
| 33 | }; |
| 34 | |
| 35 | &uart0 { |
| 36 | status = "okay"; |
| 37 | }; |
| 38 | |
| 39 | &spi1 { |
| 40 | pinctrl-names = "default"; |
| 41 | /* pin shared with snfi */ |
| 42 | pinctrl-0 = <&spic_pins>; |
| 43 | status = "disabled"; |
| 44 | }; |
| 45 | |
| 46 | &pcie { |
| 47 | pinctrl-names = "default"; |
| 48 | pinctrl-0 = <&pcie_pins>; |
| 49 | status = "okay"; |
| 50 | }; |
| 51 | |
| 52 | &pio { |
| 53 | pcie_pins: pcie-pins { |
| 54 | mux { |
| 55 | function = "pcie"; |
| 56 | groups = "pcie_pereset", "pcie_clk", "pcie_wake"; |
| 57 | }; |
| 58 | }; |
| 59 | |
| 60 | spic_pins: spi1-pins { |
| 61 | mux { |
| 62 | function = "spi"; |
| 63 | groups = "spi1_1"; |
| 64 | }; |
| 65 | }; |
| 66 | |
| 67 | mmc0_pins_default: mmc0-pins-default { |
| 68 | mux { |
| 69 | function = "flash"; |
| 70 | groups = "emmc_45"; |
| 71 | }; |
| 72 | }; |
| 73 | |
| 74 | mmc0_pins_uhs: mmc0-pins-uhs { |
| 75 | mux { |
| 76 | function = "flash"; |
| 77 | groups = "emmc_45"; |
| 78 | }; |
| 79 | }; |
| 80 | }; |
| 81 | |
| 82 | &watchdog { |
| 83 | status = "disabled"; |
| 84 | }; |
| 85 | |
| 86 | &mmc0 { |
| 87 | pinctrl-names = "default", "state_uhs"; |
| 88 | pinctrl-0 = <&mmc0_pins_default>; |
| 89 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 90 | bus-width = <8>; |
| 91 | max-frequency = <3000000>; |
| 92 | cap-mmc-highspeed; |
| 93 | vmmc-supply = <®_3p3v>; |
| 94 | non-removable; |
| 95 | status = "okay"; |
| 96 | }; |
| 97 | |
| 98 | ð { |
| 99 | status = "okay"; |
| 100 | |
| 101 | gmac0: mac@0 { |
| 102 | compatible = "mediatek,eth-mac"; |
| 103 | reg = <0>; |
| 104 | phy-mode = "rgmii"; |
| 105 | |
| 106 | fixed-link { |
| 107 | speed = <100>; |
| 108 | full-duplex; |
| 109 | pause; |
| 110 | }; |
| 111 | }; |
| 112 | |
| 113 | gmac1: mac@1 { |
| 114 | compatible = "mediatek,eth-mac"; |
| 115 | reg = <1>; |
| 116 | phy-mode = "rgmii"; |
| 117 | |
| 118 | fixed-link { |
| 119 | speed = <100>; |
| 120 | full-duplex; |
| 121 | pause; |
| 122 | }; |
| 123 | }; |
| 124 | |
| 125 | mdio: mdio-bus { |
| 126 | #address-cells = <1>; |
| 127 | #size-cells = <0>; |
| 128 | }; |
| 129 | }; |
| 130 | |
| 131 | &hnat { |
| 132 | mtketh-wan = "eth1"; |
| 133 | mtketh-lan = "eth0"; |
| 134 | mtketh-max-gmac = <2>; |
| 135 | status = "okay"; |
| 136 | }; |