blob: 3c801b38f1bf0f733d0712bd86efcd1d71a0f164 [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
5 compatible = "mediatek,mt7981-emmc-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000 \
developerdd4f7172023-03-15 10:45:06 +08009 root=PARTLABEL=rootfs rootwait \
10 rootfstype=squashfs,f2fs";
developer24455dd2021-10-28 10:55:41 +080011 };
12
13 memory {
14 // fpga ddr2: 128MB*2
15 reg = <0 0x40000000 0 0x10000000>;
16 };
17
18 reg_3p3v: regulator-3p3v {
19 compatible = "regulator-fixed";
20 regulator-name = "fixed-3.3V";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 regulator-boot-on;
24 regulator-always-on;
25 };
26};
27
28&uart0 {
29 status = "okay";
30};
31
32&watchdog {
33 status = "okay";
34};
35
36&mmc0 {
37 pinctrl-names = "default", "state_uhs";
38 pinctrl-0 = <&mmc0_pins_default>;
39 pinctrl-1 = <&mmc0_pins_uhs>;
40 bus-width = <8>;
41 max-frequency = <52000000>;
42 cap-mmc-highspeed;
43 vmmc-supply = <&reg_3p3v>;
44 non-removable;
45 status = "okay";
46};
47
48&eth {
49 status = "okay";
50
51 gmac0: mac@0 {
52 compatible = "mediatek,eth-mac";
53 reg = <0>;
54 phy-mode = "2500base-x";
55
56 fixed-link {
57 speed = <2500>;
58 full-duplex;
59 pause;
60 };
61 };
62
63 gmac1: mac@1 {
64 compatible = "mediatek,eth-mac";
65 reg = <1>;
66 phy-mode = "gmii";
67 phy-handle = <&phy0>;
68 };
69
70 mdio: mdio-bus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 phy0: ethernet-phy@0 {
developera7de8be2021-11-15 21:14:31 +080075 compatible = "ethernet-phy-id03a2.9461";
developer24455dd2021-10-28 10:55:41 +080076 reg = <0>;
developera7de8be2021-11-15 21:14:31 +080077 phy-mode = "gmii";
developera7de8be2021-11-15 21:14:31 +080078 nvmem-cells = <&phy_calibration>;
79 nvmem-cell-names = "phy-cal-data";
developer24455dd2021-10-28 10:55:41 +080080 };
81
82 switch@0 {
83 compatible = "mediatek,mt7531";
84 reg = <31>;
85 reset-gpios = <&pio 39 0>;
86
87 ports {
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 port@0 {
92 reg = <0>;
93 label = "lan1";
94 };
95
96 port@1 {
97 reg = <1>;
98 label = "lan2";
99 };
100
101 port@2 {
102 reg = <2>;
103 label = "lan3";
104 };
105
106 port@3 {
107 reg = <3>;
108 label = "lan4";
109 };
110
111 port@6 {
112 reg = <6>;
113 label = "cpu";
114 ethernet = <&gmac0>;
115 phy-mode = "2500base-x";
116
117 fixed-link {
118 speed = <2500>;
119 full-duplex;
120 pause;
121 };
122 };
123 };
124 };
125 };
126};
127
128&hnat {
129 mtketh-wan = "eth1";
130 mtketh-lan = "lan";
131 mtketh-max-gmac = <2>;
132 status = "okay";
133};
134
135&spi1 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&spic_pins>;
138 status = "disabled";
139};
140
141&pio {
142
143 spic_pins: spi1-pins {
144 mux {
145 function = "spi";
146 groups = "spi1_1";
147 };
148 };
149
150 mmc0_pins_default: mmc0-pins-default {
151 mux {
152 function = "flash";
153 groups = "emmc_45";
154 };
155 };
156
157 mmc0_pins_uhs: mmc0-pins-uhs {
158 mux {
159 function = "flash";
160 groups = "emmc_45";
161 };
162 };
163};
164
165&xhci {
166 mediatek,u3p-dis-msk = <0x0>;
167 phys = <&u2port0 PHY_TYPE_USB2>,
168 <&u3port0 PHY_TYPE_USB3>;
169 status = "okay";
170};