blob: 2125916f43c3b6677b3e8a863610d4546fcd6ae7 [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +08001From ab1b6a5a856d2ade01ce7f677dc8943ffc476c35 Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:06 +0800
4Subject: [PATCH] [slow-speed-io][999-2120-auxadc-add-auxadc-32k-clk.patch]
5
6---
7 drivers/iio/adc/mt6577_auxadc.c | 22 ++++++++++++++++++++++
8 1 file changed, 22 insertions(+)
9
developer2cdfa052021-08-12 10:41:52 +080010diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
developer5d148cb2023-06-02 13:08:11 +080011index 9cdb9084c..34f94554f 100644
developer2cdfa052021-08-12 10:41:52 +080012--- a/drivers/iio/adc/mt6577_auxadc.c
13+++ b/drivers/iio/adc/mt6577_auxadc.c
14@@ -42,6 +42,7 @@ struct mtk_auxadc_compatible {
15 struct mt6577_auxadc_device {
16 void __iomem *reg_base;
17 struct clk *adc_clk;
18+ struct clk *adc_32k_clk;
19 struct mutex lock;
20 const struct mtk_auxadc_compatible *dev_comp;
21 };
developer5d148cb2023-06-02 13:08:11 +080022@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_resume(struct device *dev)
developer2cdfa052021-08-12 10:41:52 +080023 return ret;
24 }
25
26+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
27+ if (ret) {
28+ pr_err("failed to enable auxadc clock\n");
29+ return ret;
30+ }
31+
32 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
33 MT6577_AUXADC_PDN_EN, 0);
34 mdelay(MT6577_AUXADC_POWER_READY_MS);
developer5d148cb2023-06-02 13:08:11 +080035@@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_suspend(struct device *dev)
developer2cdfa052021-08-12 10:41:52 +080036
37 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
38 0, MT6577_AUXADC_PDN_EN);
39+
40+ clk_disable_unprepare(adc_dev->adc_32k_clk);
41 clk_disable_unprepare(adc_dev->adc_clk);
42
43 return 0;
developer5d148cb2023-06-02 13:08:11 +080044@@ -280,6 +289,17 @@ static int mt6577_auxadc_probe(struct platform_device *pdev)
developer2cdfa052021-08-12 10:41:52 +080045 return ret;
46 }
47
48+ adc_dev->adc_32k_clk = devm_clk_get(&pdev->dev, "32k");
49+ if (IS_ERR(adc_dev->adc_32k_clk)) {
50+ dev_err(&pdev->dev, "failed to get auxadc 32k clock\n");
51+ } else {
52+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
53+ if (ret) {
54+ dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n");
55+ return ret;
56+ }
57+ }
58+
59 adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
60 if (!adc_clk_rate) {
61 ret = -EINVAL;
developer5d148cb2023-06-02 13:08:11 +080062@@ -309,6 +329,7 @@ err_power_off:
developer2cdfa052021-08-12 10:41:52 +080063 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
64 0, MT6577_AUXADC_PDN_EN);
65 err_disable_clk:
66+ clk_disable_unprepare(adc_dev->adc_32k_clk);
67 clk_disable_unprepare(adc_dev->adc_clk);
68 return ret;
69 }
developer5d148cb2023-06-02 13:08:11 +080070@@ -323,6 +344,7 @@ static int mt6577_auxadc_remove(struct platform_device *pdev)
developer2cdfa052021-08-12 10:41:52 +080071 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
72 0, MT6577_AUXADC_PDN_EN);
73
74+ clk_disable_unprepare(adc_dev->adc_32k_clk);
75 clk_disable_unprepare(adc_dev->adc_clk);
76
77 return 0;
developer5d148cb2023-06-02 13:08:11 +080078--
792.34.1
80