blob: 17dfa4e3f615c4caae06e05027dcc7ba5c47cffb [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-spim-nor-partition.dtsi"
developerfd40db22021-04-29 10:08:25 +08005/ {
6 model = "MediaTek MT7986b RFB";
developer3395eb42021-06-15 16:01:34 +08007 compatible = "mediatek,mt7986b-nor-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
developerfd40db22021-04-29 10:08:25 +080016};
developer298705c2021-06-05 18:48:19 +080017
developer565bacb2021-09-28 21:26:32 +080018&uart0 {
developerd45e4322021-06-17 10:41:47 +080019 status = "okay";
developer565bacb2021-09-28 21:26:32 +080020};
developer5b91be72021-09-27 14:03:07 +080021
developer565bacb2021-09-28 21:26:32 +080022/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
53
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 };
59 };
60
61 gmac1: mac@1 {
62 compatible = "mediatek,eth-mac";
63 reg = <1>;
64 phy-mode = "2500base-x";
65
66 fixed-link {
67 speed = <2500>;
68 full-duplex;
69 pause;
70 };
71 };
72
73 mdio: mdio-bus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 phy5: phy@5 {
78 compatible = "ethernet-phy-id67c9.de0a";
79 reg = <5>;
80 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +080081 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +080082 reset-deassert-us = <20000>;
83 phy-mode = "2500base-x";
84 };
85
86 phy6: phy@6 {
87 compatible = "ethernet-phy-id67c9.de0a";
88 reg = <6>;
89 phy-mode = "2500base-x";
90 };
91
92 switch@0 {
93 compatible = "mediatek,mt7531";
94 reg = <31>;
95 reset-gpios = <&pio 5 0>;
96
97 ports {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 port@0 {
102 reg = <0>;
103 label = "lan0";
104 };
105
106 port@1 {
107 reg = <1>;
108 label = "lan1";
109 };
110
111 port@2 {
112 reg = <2>;
113 label = "lan2";
114 };
115
116 port@3 {
117 reg = <3>;
118 label = "lan3";
119 };
120
121 port@6 {
122 reg = <6>;
123 label = "cpu";
124 ethernet = <&gmac0>;
125 phy-mode = "2500base-x";
126
127 fixed-link {
128 speed = <2500>;
129 full-duplex;
130 pause;
131 };
132 };
developer5b91be72021-09-27 14:03:07 +0800133 };
134 };
135 };
136};
137
developer565bacb2021-09-28 21:26:32 +0800138&hnat {
139 mtketh-wan = "eth1";
140 mtketh-lan = "lan";
141 mtketh-max-gmac = <2>;
142 status = "okay";
developer5b91be72021-09-27 14:03:07 +0800143};
144
developer565bacb2021-09-28 21:26:32 +0800145&spi0 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&spi_flash_pins>;
148 cs-gpios = <0>, <0>;
149 status = "okay";
150
151 spi_nor@0 {
152 #address-cells = <1>;
153 #size-cells = <1>;
154 compatible = "jedec,spi-nor";
155 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800156 spi-max-frequency = <52000000>;
developer5fb80602023-05-02 18:54:53 +0800157 spi-tx-bus-width = <4>;
158 spi-rx-bus-width = <4>;
developer565bacb2021-09-28 21:26:32 +0800159 };
160};
161
162/* Warning: pins shared with &uart2 */
163&spi1 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&spic_pins>;
166 status = "okay";
167};
168
169&wbsys {
170 mediatek,mtd-eeprom = <&factory 0x0000>;
171 status = "okay";
172};
173
174&pio {
175 spi_flash_pins: spi-flash-pins-33-to-38 {
176 mux {
177 function = "flash";
178 groups = "spi0", "spi0_wp_hold";
179 };
180 conf-pu {
181 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
182 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800183 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800184 };
185 conf-pd {
186 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
187 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800188 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800189 };
190
191 };
developer298705c2021-06-05 18:48:19 +0800192};