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developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
5 compatible = "mediatek,mt7981-spim-snand-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
developer7e6086a2022-05-18 14:50:36 +080016 gpio-keys {
17 compatible = "gpio-keys";
18 reset {
19 label = "reset";
20 linux,code = <KEY_RESTART>;
21 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
22 };
23
24 wps {
25 label = "wps";
26 linux,code = <KEY_WPS_BUTTON>;
27 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
28 };
29 };
30
developer24455dd2021-10-28 10:55:41 +080031 nmbm_spim_nand {
32 compatible = "generic,nmbm";
33
34 #address-cells = <1>;
35 #size-cells = <1>;
36
37 lower-mtd-device = <&spi_nand>;
38 forced-create;
39
40 partitions {
41 compatible = "fixed-partitions";
42 #address-cells = <1>;
43 #size-cells = <1>;
44
45 partition@0 {
46 label = "BL2";
47 reg = <0x00000 0x0100000>;
48 read-only;
49 };
50
51 partition@100000 {
52 label = "u-boot-env";
53 reg = <0x0100000 0x0080000>;
54 };
55
56 partition@180000 {
57 label = "Factory";
58 reg = <0x180000 0x0200000>;
59 };
60
61 partition@380000 {
62 label = "FIP";
63 reg = <0x380000 0x0200000>;
64 };
65
66 partition@580000 {
67 label = "ubi";
68 reg = <0x580000 0x4000000>;
69 };
70 };
71 };
developere3c7cd12021-11-30 14:49:26 +080072
developereee89f92021-12-30 10:09:49 +080073 sound_wm8960 {
74 compatible = "mediatek,mt79xx-wm8960-machine";
75 mediatek,platform = <&afe>;
76 audio-routing = "Headphone", "HP_L",
77 "Headphone", "HP_R",
78 "LINPUT1", "AMIC",
79 "RINPUT1", "AMIC";
80 mediatek,audio-codec = <&wm8960>;
81 status = "disabled";
82 };
83
84 sound_si3218x {
developere3c7cd12021-11-30 14:49:26 +080085 compatible = "mediatek,mt79xx-si3218x-machine";
86 mediatek,platform = <&afe>;
87 mediatek,ext-codec = <&proslic_spi>;
developereee89f92021-12-30 10:09:49 +080088 status = "disabled";
developere3c7cd12021-11-30 14:49:26 +080089 };
90};
91
92&afe {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pcm_pins>;
95 status = "okay";
96};
97
98&i2c0 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&i2c_pins>;
developereee89f92021-12-30 10:09:49 +0800101 status = "disabled";
developere3c7cd12021-11-30 14:49:26 +0800102
103 wm8960: wm8960@1a {
104 compatible = "wlf,wm8960";
105 reg = <0x1a>;
106 };
developer24455dd2021-10-28 10:55:41 +0800107};
108
109&uart0 {
110 status = "okay";
111};
112
113&watchdog {
114 status = "okay";
115};
116
117&eth {
118 status = "okay";
119
120 gmac0: mac@0 {
121 compatible = "mediatek,eth-mac";
122 reg = <0>;
123 phy-mode = "2500base-x";
124
125 fixed-link {
126 speed = <2500>;
127 full-duplex;
128 pause;
129 };
130 };
131
132 gmac1: mac@1 {
133 compatible = "mediatek,eth-mac";
134 reg = <1>;
135 phy-mode = "gmii";
136 phy-handle = <&phy0>;
137 };
138
139 mdio: mdio-bus {
140 #address-cells = <1>;
141 #size-cells = <0>;
142
143 phy0: ethernet-phy@0 {
developera7de8be2021-11-15 21:14:31 +0800144 compatible = "ethernet-phy-id03a2.9461";
developer24455dd2021-10-28 10:55:41 +0800145 reg = <0>;
developera7de8be2021-11-15 21:14:31 +0800146 phy-mode = "gmii";
developera7de8be2021-11-15 21:14:31 +0800147 nvmem-cells = <&phy_calibration>;
148 nvmem-cell-names = "phy-cal-data";
developer24455dd2021-10-28 10:55:41 +0800149 };
150
151 switch@0 {
152 compatible = "mediatek,mt7531";
153 reg = <31>;
154 reset-gpios = <&pio 39 0>;
155
156 ports {
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 port@0 {
161 reg = <0>;
162 label = "lan1";
163 };
164
165 port@1 {
166 reg = <1>;
167 label = "lan2";
168 };
169
170 port@2 {
171 reg = <2>;
172 label = "lan3";
173 };
174
175 port@3 {
176 reg = <3>;
177 label = "lan4";
178 };
179
180 port@6 {
181 reg = <6>;
182 label = "cpu";
183 ethernet = <&gmac0>;
184 phy-mode = "2500base-x";
185
186 fixed-link {
187 speed = <2500>;
188 full-duplex;
189 pause;
190 };
191 };
192 };
193 };
194 };
195};
196
197&hnat {
198 mtketh-wan = "eth1";
199 mtketh-lan = "lan";
200 mtketh-max-gmac = <2>;
201 status = "okay";
202};
203
204&spi0 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&spi0_flash_pins>;
207 status = "okay";
208 spi_nand: spi_nand@0 {
209 #address-cells = <1>;
210 #size-cells = <1>;
211 compatible = "spi-nand";
212 reg = <0>;
213 spi-max-frequency = <52000000>;
developer5fb80602023-05-02 18:54:53 +0800214 spi-tx-bus-width = <4>;
215 spi-rx-bus-width = <4>;
developer24455dd2021-10-28 10:55:41 +0800216 };
217};
218
219&spi1 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&spic_pins>;
developere3c7cd12021-11-30 14:49:26 +0800222 status = "okay";
223
224 proslic_spi: proslic_spi@0 {
225 compatible = "silabs,proslic_spi";
226 reg = <0>;
227 spi-max-frequency = <10000000>;
228 spi-cpha = <1>;
229 spi-cpol = <1>;
230 channel_count = <1>;
231 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
232 reset_gpio = <&pio 15 0>;
233 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
234 };
developer24455dd2021-10-28 10:55:41 +0800235};
236
237&pio {
238
239 i2c_pins: i2c-pins-g0 {
240 mux {
241 function = "i2c";
242 groups = "i2c0_0";
243 };
244 };
245
246 pcm_pins: pcm-pins-g0 {
247 mux {
248 function = "pcm";
249 groups = "pcm";
250 };
251 };
252
253 pwm0_pin: pwm0-pin-g0 {
254 mux {
255 function = "pwm";
256 groups = "pwm0_0";
257 };
258 };
259
260 pwm1_pin: pwm1-pin-g0 {
261 mux {
262 function = "pwm";
263 groups = "pwm1_0";
264 };
265 };
266
267 pwm2_pin: pwm2-pin {
268 mux {
269 function = "pwm";
270 groups = "pwm2";
271 };
272 };
273
274 spi0_flash_pins: spi0-pins {
275 mux {
276 function = "spi";
277 groups = "spi0", "spi0_wp_hold";
278 };
developer66b31fc2021-12-27 17:12:45 +0800279
280 conf-pu {
281 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
282 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800283 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800284 };
285
286 conf-pd {
287 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
288 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800289 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800290 };
developer24455dd2021-10-28 10:55:41 +0800291 };
292
293 spic_pins: spi1-pins {
294 mux {
295 function = "spi";
296 groups = "spi1_1";
297 };
298 };
299
300 uart1_pins: uart1-pins-g1 {
301 mux {
302 function = "uart";
303 groups = "uart1_1";
304 };
305 };
306
307 uart2_pins: uart2-pins-g1 {
308 mux {
309 function = "uart";
310 groups = "uart2_1";
311 };
312 };
313};
314
315&xhci {
316 mediatek,u3p-dis-msk = <0x0>;
317 phys = <&u2port0 PHY_TYPE_USB2>,
318 <&u3port0 PHY_TYPE_USB3>;
319 status = "okay";
320};