blob: 2d4bfaa9bed770234b5f24b865223880e67ecc61 [file] [log] [blame]
developer4f56ddb2023-11-29 12:16:21 +08001From 4136e3567f6904259babbe5ae5c0d0bf06413f57 Mon Sep 17 00:00:00 2001
2From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
3Date: Wed, 25 Oct 2023 09:21:06 +0800
4Subject: [PATCH] 999-2952-net-ethernet-mtk_eth_soc-modify-fq-size-4K
5
6---
7 drivers/net/ethernet/mediatek/mtk_eth_dbg.c | 2 +-
8 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 74 ++++++++++---------
9 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +-
10 .../ethernet/mediatek/mtk_hnat/hnat_debugfs.c | 2 +-
11 .../ethernet/mediatek/mtk_hnat/hnat_nf_hook.c | 23 ++++++
12 5 files changed, 69 insertions(+), 37 deletions(-)
13
14diff --git a/drivers/net/ethernet/mediatek/mtk_eth_dbg.c b/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
15index e50e1ac..7c137e5 100755
16--- a/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
17+++ b/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
18@@ -882,7 +882,7 @@ int hwtx_ring_read(struct seq_file *seq, void *v)
19 struct mtk_tx_dma_v2 *hwtx_ring;
20 int i = 0;
21
22- for (i = 0; i < MTK_DMA_SIZE; i++) {
23+ for (i = 0; i < MTK_DMA_FQ_SIZE; i++) {
24 dma_addr_t addr = eth->phy_scratch_ring +
25 i * (dma_addr_t)eth->soc->txrx.txd_size;
26
27diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
28index 1226dd6..fe9c1de 100644
29--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
30+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
31@@ -1557,10 +1557,10 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
32 {
33 const struct mtk_soc_data *soc = eth->soc;
34 dma_addr_t phy_ring_tail;
35- int cnt = MTK_DMA_SIZE;
36+ int cnt = MTK_DMA_FQ_SIZE;
37 dma_addr_t dma_addr;
38 u64 addr64 = 0;
39- int i;
40+ int i, j, len;
41
42 if (!eth->soc->has_sram) {
43 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
44@@ -1577,40 +1577,44 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
45 if (unlikely(!eth->scratch_ring))
46 return -ENOMEM;
47
48- eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
49- if (unlikely(!eth->scratch_head))
50- return -ENOMEM;
51-
52- dma_addr = dma_map_single(eth->dma_dev,
53- eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
54- DMA_FROM_DEVICE);
55- if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
56- return -ENOMEM;
57-
58 phy_ring_tail = eth->phy_scratch_ring +
59 (dma_addr_t)soc->txrx.txd_size * (cnt - 1);
60
61- for (i = 0; i < cnt; i++) {
62- struct mtk_tx_dma_v2 *txd;
63+ for (j = 0; j < DIV_ROUND_UP(MTK_DMA_FQ_SIZE, MTK_DMA_FQ_LENGTH); j++) {
64+ len = min_t(int, cnt - j * MTK_DMA_FQ_LENGTH, MTK_DMA_FQ_LENGTH);
65
66- txd = eth->scratch_ring + i * soc->txrx.txd_size;
67- txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
68- if (i < cnt - 1)
69- txd->txd2 = eth->phy_scratch_ring +
70- (i + 1) * soc->txrx.txd_size;
71+ eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
72+ if (unlikely(!eth->scratch_head[j]))
73+ return -ENOMEM;
74
75- addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
76- TX_DMA_SDP1(dma_addr + i * MTK_QDMA_PAGE_SIZE) : 0;
77+ dma_addr = dma_map_single(eth->dma_dev,
78+ eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE,
79+ DMA_FROM_DEVICE);
80+ if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
81+ return -ENOMEM;
82
83- txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE) | addr64;
84- txd->txd4 = 0;
85+ for (i = 0; i < len; i++) {
86+ struct mtk_tx_dma_v2 *txd;
87
88- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
89- MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
90- txd->txd5 = 0;
91- txd->txd6 = 0;
92- txd->txd7 = 0;
93- txd->txd8 = 0;
94+ txd = eth->scratch_ring + (j * MTK_DMA_FQ_LENGTH + i) * soc->txrx.txd_size;
95+ txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
96+ if (j * MTK_DMA_FQ_LENGTH + i < cnt)
97+ txd->txd2 = eth->phy_scratch_ring +
98+ (j * MTK_DMA_FQ_LENGTH + i + 1) * soc->txrx.txd_size;
99+
100+ addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
101+ TX_DMA_SDP1(dma_addr + i * MTK_QDMA_PAGE_SIZE) : 0;
102+
103+ txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE) | addr64;
104+ txd->txd4 = 0;
105+
106+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
107+ MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
108+ txd->txd5 = 0;
109+ txd->txd6 = 0;
110+ txd->txd7 = 0;
111+ txd->txd8 = 0;
112+ }
113 }
114 }
115
116@@ -2541,9 +2545,9 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
117 ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,
118 &ring->phys, GFP_KERNEL);
119 else {
120- ring->dma = eth->scratch_ring + MTK_DMA_SIZE * sz;
121+ ring->dma = eth->scratch_ring + MTK_DMA_FQ_SIZE * sz;
122 ring->phys = eth->phy_scratch_ring +
123- MTK_DMA_SIZE * (dma_addr_t)sz;
124+ MTK_DMA_FQ_SIZE * (dma_addr_t)sz;
125 }
126
127 if (!ring->dma)
128@@ -3349,9 +3353,11 @@ static void mtk_dma_free(struct mtk_eth *eth)
129 mtk_rx_clean(eth, &eth->rx_ring[MTK_RSS_RING(i)], 1);
130 }
131
132- if (eth->scratch_head) {
133- kfree(eth->scratch_head);
134- eth->scratch_head = NULL;
135+ for (i = 0; i < DIV_ROUND_UP(MTK_DMA_FQ_SIZE, MTK_DMA_FQ_LENGTH); i++) {
136+ if (eth->scratch_head[i]) {
137+ kfree(eth->scratch_head[i]);
138+ eth->scratch_head[i] = NULL;
139+ }
140 }
141 }
142
143diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
144index fe8bdee..cd2de23 100644
145--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
146+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
147@@ -20,6 +20,9 @@
148 #define MTK_MAX_RX_LENGTH 1536
149 #define MTK_MIN_TX_LENGTH 60
150 #define MTK_DMA_SIZE 2048
151+#define MTK_DMA_FQ_SIZE 4096
152+#define MTK_DMA_FQ_HEAD 32
153+#define MTK_DMA_FQ_LENGTH 2048
154 #define MTK_NAPI_WEIGHT 256
155
156 #if defined(CONFIG_MEDIATEK_NETSYS_V3)
157@@ -1837,7 +1840,7 @@ struct mtk_eth {
158 void *scratch_ring;
159 struct mtk_reset_event reset_event;
160 dma_addr_t phy_scratch_ring;
161- void *scratch_head;
162+ void *scratch_head[MTK_DMA_FQ_HEAD];
163 struct clk *clks[MTK_CLK_MAX];
164
165 struct mii_bus *mii_bus;
166diff --git a/drivers/net/ethernet/mediatek/mtk_hnat/hnat_debugfs.c b/drivers/net/ethernet/mediatek/mtk_hnat/hnat_debugfs.c
167index fc7d216..b97fd6a 100644
168--- a/drivers/net/ethernet/mediatek/mtk_hnat/hnat_debugfs.c
169+++ b/drivers/net/ethernet/mediatek/mtk_hnat/hnat_debugfs.c
170@@ -2784,7 +2784,7 @@ static ssize_t hnat_qos_toggle_write(struct file *file, const char __user *buffe
171 qos_toggle = 1;
172 } else if (buf[0] == '2') {
173 pr_info("Per-port-per-queue mode is going to be enabled!\n");
174- pr_info("PPPQ use qid 0~5 (scheduler 0).\n");
175+ pr_info("PPPQ use qid 0~11 (scheduler 0).\n");
176 qos_toggle = 2;
177 qos_dl_toggle = 1;
178 qos_ul_toggle = 1;
179diff --git a/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c b/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
180index 85c38e0..6a373f8 100644
181--- a/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
182+++ b/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
183@@ -1219,6 +1219,7 @@ static unsigned int skb_to_hnat_info(struct sk_buff *skb,
184 int udp = 0;
185 u32 qid = 0;
186 u32 port_id = 0;
187+ u32 payload_len = 0;
188 int mape = 0;
189
190 ct = nf_ct_get(skb, &ctinfo);
191@@ -1748,6 +1749,28 @@ static unsigned int skb_to_hnat_info(struct sk_buff *skb,
192 else
193 qid = 0;
194
195+ if (IS_PPPQ_MODE && IS_PPPQ_PATH(dev, skb)) {
196+ if (ntohs(eth->h_proto) == ETH_P_IP) {
197+ iph = ip_hdr(skb);
198+ if (iph->protocol == IPPROTO_TCP) {
199+ skb_set_transport_header(skb, sizeof(struct iphdr));
200+ payload_len = be16_to_cpu(iph->tot_len) - skb_transport_offset(skb) - tcp_hdrlen(skb);
201+ /* Dispatch ACK packets to high priority queue */
202+ if (payload_len == 0)
203+ qid += 6;
204+ }
205+ } else if (ntohs(eth->h_proto) == ETH_P_IPV6) {
206+ ip6h = ipv6_hdr(skb);
207+ if (ip6h->nexthdr == NEXTHDR_TCP) {
208+ skb_set_transport_header(skb, sizeof(struct ipv6hdr));
209+ payload_len = be16_to_cpu(ip6h->payload_len) - tcp_hdrlen(skb);
210+ /* Dispatch ACK packets to high priority queue */
211+ if (payload_len == 0)
212+ qid += 6;
213+ }
214+ }
215+ }
216+
217 if (IS_IPV4_GRP(foe)) {
218 entry.ipv4_hnapt.iblk2.dp = gmac;
219 entry.ipv4_hnapt.iblk2.port_mg =
220--
2212.18.0
222