developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 1 | From e63fdeaa652ad5fd8d7a591e346abe587fd9bede Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:25 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [high-speed-io][999-2612-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch] |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 6 | |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 7 | --- |
| 8 | drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++ |
| 9 | 1 file changed, 140 insertions(+) |
| 10 | |
| 11 | diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 12 | index fcf8c845f..6c07885be 100644 |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 13 | --- a/drivers/phy/mediatek/phy-mtk-tphy.c |
| 14 | +++ b/drivers/phy/mediatek/phy-mtk-tphy.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 15 | @@ -42,6 +42,15 @@ |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 16 | #define SSUSB_SIFSLV_V2_U3PHYD 0x200 |
| 17 | #define SSUSB_SIFSLV_V2_U3PHYA 0x400 |
| 18 | |
| 19 | +/* version V4 sub-banks offset base address */ |
| 20 | +/* pcie phy banks */ |
| 21 | +#define SSUSB_SIFSLV_V4_SPLLC 0x000 |
| 22 | +#define SSUSB_SIFSLV_V4_CHIP 0x100 |
| 23 | +#define SSUSB_SIFSLV_V4_U3PHYD 0x900 |
| 24 | +#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 |
| 25 | + |
| 26 | +#define SSUSB_LN1_OFFSET 0x10000 |
| 27 | + |
| 28 | #define U3P_MISC_REG1 0x04 |
| 29 | #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) |
| 30 | |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 31 | @@ -308,6 +317,7 @@ enum mtk_phy_version { |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 32 | MTK_PHY_V1 = 1, |
| 33 | MTK_PHY_V2, |
| 34 | MTK_PHY_V3, |
| 35 | + MTK_PHY_V4, |
| 36 | }; |
| 37 | |
| 38 | struct mtk_phy_pdata { |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 39 | @@ -352,6 +362,9 @@ struct mtk_phy_instance { |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 40 | u32 efuse_intr; |
| 41 | u32 efuse_tx_imp; |
| 42 | u32 efuse_rx_imp; |
| 43 | + u32 efuse_intr_ln1; |
| 44 | + u32 efuse_tx_imp_ln1; |
| 45 | + u32 efuse_rx_imp_ln1; |
| 46 | u32 index; |
developer | 8cdcb26 | 2022-10-27 14:36:15 +0800 | [diff] [blame] | 47 | u32 type; |
| 48 | struct regmap *type_sw; |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 49 | @@ -900,6 +913,36 @@ static void phy_v2_banks_init(struct mtk_tphy *tphy, |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 50 | } |
| 51 | } |
| 52 | |
| 53 | +static void phy_v4_banks_init(struct mtk_tphy *tphy, |
| 54 | + struct mtk_phy_instance *instance) |
| 55 | +{ |
| 56 | + struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 57 | + struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 58 | + |
| 59 | + switch (instance->type) { |
| 60 | + case PHY_TYPE_USB2: |
| 61 | + u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; |
| 62 | + u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; |
| 63 | + u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; |
| 64 | + break; |
| 65 | + case PHY_TYPE_USB3: |
| 66 | + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; |
| 67 | + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; |
| 68 | + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; |
| 69 | + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; |
| 70 | + break; |
| 71 | + case PHY_TYPE_PCIE: |
| 72 | + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; |
| 73 | + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; |
| 74 | + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; |
| 75 | + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; |
| 76 | + break; |
| 77 | + default: |
| 78 | + dev_err(tphy->dev, "incompatible PHY type\n"); |
| 79 | + return; |
| 80 | + } |
| 81 | +} |
| 82 | + |
| 83 | static void phy_parse_property(struct mtk_tphy *tphy, |
| 84 | struct mtk_phy_instance *instance) |
| 85 | { |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 86 | @@ -1082,6 +1125,40 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 87 | dev_info(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", |
| 88 | instance->efuse_intr, instance->efuse_rx_imp, |
| 89 | instance->efuse_tx_imp); |
| 90 | + |
| 91 | + if (tphy->pdata->version != MTK_PHY_V4) |
| 92 | + break; |
| 93 | + |
| 94 | + ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); |
| 95 | + if (ret) { |
| 96 | + dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); |
| 97 | + break; |
| 98 | + } |
| 99 | + |
| 100 | + ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); |
| 101 | + if (ret) { |
| 102 | + dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); |
| 103 | + break; |
| 104 | + } |
| 105 | + |
| 106 | + ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); |
| 107 | + if (ret) { |
| 108 | + dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); |
| 109 | + break; |
| 110 | + } |
| 111 | + |
| 112 | + /* no efuse, ignore it */ |
| 113 | + if (!instance->efuse_intr_ln1 && |
| 114 | + !instance->efuse_rx_imp_ln1 && |
| 115 | + !instance->efuse_tx_imp_ln1) { |
| 116 | + dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); |
| 117 | + instance->efuse_sw_en = 0; |
| 118 | + break; |
| 119 | + } |
| 120 | + |
| 121 | + dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", |
| 122 | + instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, |
| 123 | + instance->efuse_tx_imp_ln1); |
| 124 | break; |
| 125 | default: |
| 126 | dev_err(dev, "no sw efuse for type %d\n", instance->type); |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 127 | @@ -1115,6 +1192,31 @@ static void phy_efuse_set(struct mtk_phy_instance *instance) |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 128 | |
| 129 | break; |
| 130 | case PHY_TYPE_USB3: |
| 131 | + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); |
| 132 | + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; |
| 133 | + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); |
| 134 | + |
| 135 | + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); |
| 136 | + tmp &= ~P3D_RG_TX_IMPEL; |
| 137 | + tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp); |
| 138 | + tmp |= P3D_RG_FORCE_TX_IMPEL; |
| 139 | + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); |
| 140 | + |
| 141 | + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); |
| 142 | + tmp &= ~P3D_RG_RX_IMPEL; |
| 143 | + tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp); |
| 144 | + tmp |= P3D_RG_FORCE_RX_IMPEL; |
| 145 | + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); |
| 146 | + |
| 147 | + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); |
| 148 | + tmp &= ~P3A_RG_IEXT_INTR; |
| 149 | + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); |
| 150 | + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); |
| 151 | + pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", |
| 152 | + __func__, instance->efuse_tx_imp, |
| 153 | + instance->efuse_rx_imp, instance->efuse_intr); |
| 154 | + |
| 155 | + break; |
| 156 | case PHY_TYPE_PCIE: |
| 157 | tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); |
| 158 | tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 159 | @@ -1139,6 +1241,35 @@ static void phy_efuse_set(struct mtk_phy_instance *instance) |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 160 | pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", |
| 161 | __func__, instance->efuse_tx_imp, |
| 162 | instance->efuse_rx_imp, instance->efuse_intr); |
| 163 | + |
| 164 | + if (!instance->efuse_intr_ln1 && |
| 165 | + !instance->efuse_rx_imp_ln1 && |
| 166 | + !instance->efuse_tx_imp_ln1) |
| 167 | + break; |
| 168 | + |
| 169 | + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); |
| 170 | + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; |
| 171 | + writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); |
| 172 | + |
| 173 | + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); |
| 174 | + tmp &= ~P3D_RG_TX_IMPEL; |
| 175 | + tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1); |
| 176 | + tmp |= P3D_RG_FORCE_TX_IMPEL; |
| 177 | + writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); |
| 178 | + |
| 179 | + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); |
| 180 | + tmp &= ~P3D_RG_RX_IMPEL; |
| 181 | + tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1); |
| 182 | + tmp |= P3D_RG_FORCE_RX_IMPEL; |
| 183 | + writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); |
| 184 | + |
| 185 | + tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); |
| 186 | + tmp &= ~P3A_RG_IEXT_INTR; |
| 187 | + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1); |
| 188 | + writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); |
| 189 | + pr_err("%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", |
| 190 | + __func__, instance->efuse_tx_imp_ln1, |
| 191 | + instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); |
| 192 | break; |
| 193 | default: |
| 194 | dev_warn(dev, "no sw efuse for type %d\n", instance->type); |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 195 | @@ -1282,6 +1413,8 @@ static struct phy *mtk_phy_xlate(struct device *dev, |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 196 | phy_v1_banks_init(tphy, instance); |
| 197 | } else if (tphy->pdata->version == MTK_PHY_V2) { |
| 198 | phy_v2_banks_init(tphy, instance); |
| 199 | + } else if (tphy->pdata->version == MTK_PHY_V4) { |
| 200 | + phy_v4_banks_init(tphy, instance); |
| 201 | } else { |
| 202 | dev_err(dev, "phy version is not supported\n"); |
| 203 | return ERR_PTR(-EINVAL); |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 204 | @@ -1333,12 +1466,19 @@ static const struct mtk_phy_pdata mt8195_pdata = { |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 205 | .version = MTK_PHY_V3, |
| 206 | }; |
| 207 | |
| 208 | +static const struct mtk_phy_pdata tphy_v4_pdata = { |
| 209 | + .avoid_rx_sen_degradation = false, |
| 210 | + .sw_efuse_supported = true, |
| 211 | + .version = MTK_PHY_V4, |
| 212 | +}; |
| 213 | + |
| 214 | static const struct of_device_id mtk_tphy_id_table[] = { |
| 215 | { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, |
| 216 | { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, |
| 217 | { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, |
| 218 | { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, |
| 219 | { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, |
| 220 | + { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, |
| 221 | { }, |
| 222 | }; |
| 223 | MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); |
| 224 | -- |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame^] | 225 | 2.34.1 |
developer | 44e1bbf | 2022-01-28 17:20:00 +0800 | [diff] [blame] | 226 | |