developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
| 4 | #include <linux/relay.h> |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5 | #include "besra.h" |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6 | #include "eeprom.h" |
| 7 | #include "mcu.h" |
| 8 | #include "mac.h" |
| 9 | |
| 10 | #define FW_BIN_LOG_MAGIC 0x44d9c99a |
| 11 | |
| 12 | /** global debugfs **/ |
| 13 | |
| 14 | struct hw_queue_map { |
| 15 | const char *name; |
| 16 | u8 index; |
| 17 | u8 pid; |
| 18 | u8 qid; |
| 19 | }; |
| 20 | |
| 21 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 22 | besra_implicit_txbf_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 23 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 24 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 25 | |
| 26 | if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) |
| 27 | return -EBUSY; |
| 28 | |
| 29 | dev->ibf = !!val; |
| 30 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 31 | return besra_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 35 | besra_implicit_txbf_get(void *data, u64 *val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 36 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 37 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 38 | |
| 39 | *val = dev->ibf; |
| 40 | |
| 41 | return 0; |
| 42 | } |
| 43 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 44 | DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, besra_implicit_txbf_get, |
| 45 | besra_implicit_txbf_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 46 | |
| 47 | /* test knob of system layer 1/2 error recovery */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 48 | static int besra_ser_trigger_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 49 | { |
| 50 | enum { |
| 51 | SER_SET_RECOVER_L1 = 1, |
| 52 | SER_SET_RECOVER_L2, |
| 53 | SER_ENABLE = 2, |
| 54 | SER_RECOVER |
| 55 | }; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 56 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 57 | int ret = 0; |
| 58 | |
| 59 | switch (val) { |
| 60 | case SER_SET_RECOVER_L1: |
| 61 | case SER_SET_RECOVER_L2: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 62 | ret = besra_mcu_set_ser(dev, SER_ENABLE, BIT(val), 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 63 | if (ret) |
| 64 | return ret; |
| 65 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 66 | return besra_mcu_set_ser(dev, SER_RECOVER, val, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 67 | default: |
| 68 | break; |
| 69 | } |
| 70 | |
| 71 | return ret; |
| 72 | } |
| 73 | |
| 74 | DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 75 | besra_ser_trigger_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 76 | |
| 77 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 78 | besra_radar_trigger(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 79 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 80 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 81 | |
| 82 | if (val > MT_RX_SEL2) |
| 83 | return -EINVAL; |
| 84 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 85 | return besra_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 86 | val, 0, 0); |
| 87 | } |
| 88 | |
| 89 | DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 90 | besra_radar_trigger, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 91 | |
| 92 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 93 | besra_muru_debug_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 94 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 95 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 96 | |
| 97 | dev->muru_debug = val; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 98 | besra_mcu_muru_debug_set(dev, dev->muru_debug); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 99 | |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 104 | besra_muru_debug_get(void *data, u64 *val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 105 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 106 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 107 | |
| 108 | *val = dev->muru_debug; |
| 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 113 | DEFINE_DEBUGFS_ATTRIBUTE(fops_muru_debug, besra_muru_debug_get, |
| 114 | besra_muru_debug_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 115 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 116 | static int besra_muru_stats_show(struct seq_file *file, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 117 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 118 | struct besra_phy *phy = file->private; |
| 119 | struct besra_dev *dev = phy->dev; |
| 120 | struct besra_mcu_muru_stats mu_stats = {}; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 121 | static const char * const dl_non_he_type[] = { |
| 122 | "CCK", "OFDM", "HT MIX", "HT GF", |
| 123 | "VHT SU", "VHT 2MU", "VHT 3MU", "VHT 4MU" |
| 124 | }; |
| 125 | static const char * const dl_he_type[] = { |
| 126 | "HE SU", "HE EXT", "HE 2MU", "HE 3MU", "HE 4MU", |
| 127 | "HE 2RU", "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", |
| 128 | "HE >16RU" |
| 129 | }; |
| 130 | static const char * const ul_he_type[] = { |
| 131 | "HE 2MU", "HE 3MU", "HE 4MU", "HE SU", "HE 2RU", |
| 132 | "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", "HE >16RU" |
| 133 | }; |
| 134 | int ret, i; |
| 135 | u64 total_ppdu_cnt, sub_total_cnt; |
| 136 | |
| 137 | if (!dev->muru_debug) { |
| 138 | seq_puts(file, "Please enable muru_debug first.\n"); |
| 139 | return 0; |
| 140 | } |
| 141 | |
| 142 | mutex_lock(&dev->mt76.mutex); |
| 143 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 144 | ret = besra_mcu_muru_debug_get(phy, &mu_stats); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 145 | if (ret) |
| 146 | goto exit; |
| 147 | |
| 148 | /* Non-HE Downlink*/ |
| 149 | seq_puts(file, "[Non-HE]\nDownlink\nData Type: "); |
| 150 | |
| 151 | for (i = 0; i < 5; i++) |
| 152 | seq_printf(file, "%8s | ", dl_non_he_type[i]); |
| 153 | |
| 154 | #define __dl_u32(s) le32_to_cpu(mu_stats.dl.s) |
| 155 | seq_puts(file, "\nTotal Count:"); |
| 156 | seq_printf(file, "%8u | %8u | %8u | %8u | %8u | ", |
| 157 | __dl_u32(cck_cnt), |
| 158 | __dl_u32(ofdm_cnt), |
| 159 | __dl_u32(htmix_cnt), |
| 160 | __dl_u32(htgf_cnt), |
| 161 | __dl_u32(vht_su_cnt)); |
| 162 | |
| 163 | seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); |
| 164 | |
| 165 | for (i = 5; i < 8; i++) |
| 166 | seq_printf(file, "%8s | ", dl_non_he_type[i]); |
| 167 | |
| 168 | seq_puts(file, "\nTotal Count:"); |
| 169 | seq_printf(file, "%8u | %8u | %8u | ", |
| 170 | __dl_u32(vht_2mu_cnt), |
| 171 | __dl_u32(vht_3mu_cnt), |
| 172 | __dl_u32(vht_4mu_cnt)); |
| 173 | |
| 174 | sub_total_cnt = __dl_u32(vht_2mu_cnt) + |
| 175 | __dl_u32(vht_3mu_cnt) + |
| 176 | __dl_u32(vht_4mu_cnt); |
| 177 | |
| 178 | seq_printf(file, "\nTotal non-HE MU-MIMO DL PPDU count: %lld", |
| 179 | sub_total_cnt); |
| 180 | |
| 181 | total_ppdu_cnt = sub_total_cnt + |
| 182 | __dl_u32(cck_cnt) + |
| 183 | __dl_u32(ofdm_cnt) + |
| 184 | __dl_u32(htmix_cnt) + |
| 185 | __dl_u32(htgf_cnt) + |
| 186 | __dl_u32(vht_su_cnt); |
| 187 | |
| 188 | seq_printf(file, "\nAll non-HE DL PPDU count: %lld", total_ppdu_cnt); |
| 189 | |
| 190 | /* HE Downlink */ |
| 191 | seq_puts(file, "\n\n[HE]\nDownlink\nData Type: "); |
| 192 | |
| 193 | for (i = 0; i < 2; i++) |
| 194 | seq_printf(file, "%8s | ", dl_he_type[i]); |
| 195 | |
| 196 | seq_puts(file, "\nTotal Count:"); |
| 197 | seq_printf(file, "%8u | %8u | ", |
| 198 | __dl_u32(he_su_cnt), |
| 199 | __dl_u32(he_ext_su_cnt)); |
| 200 | |
| 201 | seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); |
| 202 | |
| 203 | for (i = 2; i < 5; i++) |
| 204 | seq_printf(file, "%8s | ", dl_he_type[i]); |
| 205 | |
| 206 | seq_puts(file, "\nTotal Count:"); |
| 207 | seq_printf(file, "%8u | %8u | %8u | ", |
| 208 | __dl_u32(he_2mu_cnt), |
| 209 | __dl_u32(he_3mu_cnt), |
| 210 | __dl_u32(he_4mu_cnt)); |
| 211 | |
| 212 | seq_puts(file, "\nDownlink OFDMA\nData Type: "); |
| 213 | |
| 214 | for (i = 5; i < 11; i++) |
| 215 | seq_printf(file, "%8s | ", dl_he_type[i]); |
| 216 | |
| 217 | seq_puts(file, "\nTotal Count:"); |
| 218 | seq_printf(file, "%8u | %8u | %8u | %8u | %9u | %8u | ", |
| 219 | __dl_u32(he_2ru_cnt), |
| 220 | __dl_u32(he_3ru_cnt), |
| 221 | __dl_u32(he_4ru_cnt), |
| 222 | __dl_u32(he_5to8ru_cnt), |
| 223 | __dl_u32(he_9to16ru_cnt), |
| 224 | __dl_u32(he_gtr16ru_cnt)); |
| 225 | |
| 226 | sub_total_cnt = __dl_u32(he_2mu_cnt) + |
| 227 | __dl_u32(he_3mu_cnt) + |
| 228 | __dl_u32(he_4mu_cnt); |
| 229 | total_ppdu_cnt = sub_total_cnt; |
| 230 | |
| 231 | seq_printf(file, "\nTotal HE MU-MIMO DL PPDU count: %lld", |
| 232 | sub_total_cnt); |
| 233 | |
| 234 | sub_total_cnt = __dl_u32(he_2ru_cnt) + |
| 235 | __dl_u32(he_3ru_cnt) + |
| 236 | __dl_u32(he_4ru_cnt) + |
| 237 | __dl_u32(he_5to8ru_cnt) + |
| 238 | __dl_u32(he_9to16ru_cnt) + |
| 239 | __dl_u32(he_gtr16ru_cnt); |
| 240 | total_ppdu_cnt += sub_total_cnt; |
| 241 | |
| 242 | seq_printf(file, "\nTotal HE OFDMA DL PPDU count: %lld", |
| 243 | sub_total_cnt); |
| 244 | |
| 245 | total_ppdu_cnt += __dl_u32(he_su_cnt) + |
| 246 | __dl_u32(he_ext_su_cnt); |
| 247 | |
| 248 | seq_printf(file, "\nAll HE DL PPDU count: %lld", total_ppdu_cnt); |
| 249 | #undef __dl_u32 |
| 250 | |
| 251 | /* HE Uplink */ |
| 252 | seq_puts(file, "\n\nUplink"); |
| 253 | seq_puts(file, "\nTrigger-based Uplink MU-MIMO\nData Type: "); |
| 254 | |
| 255 | for (i = 0; i < 3; i++) |
| 256 | seq_printf(file, "%8s | ", ul_he_type[i]); |
| 257 | |
| 258 | #define __ul_u32(s) le32_to_cpu(mu_stats.ul.s) |
| 259 | seq_puts(file, "\nTotal Count:"); |
| 260 | seq_printf(file, "%8u | %8u | %8u | ", |
| 261 | __ul_u32(hetrig_2mu_cnt), |
| 262 | __ul_u32(hetrig_3mu_cnt), |
| 263 | __ul_u32(hetrig_4mu_cnt)); |
| 264 | |
| 265 | seq_puts(file, "\nTrigger-based Uplink OFDMA\nData Type: "); |
| 266 | |
| 267 | for (i = 3; i < 10; i++) |
| 268 | seq_printf(file, "%8s | ", ul_he_type[i]); |
| 269 | |
| 270 | seq_puts(file, "\nTotal Count:"); |
| 271 | seq_printf(file, "%8u | %8u | %8u | %8u | %8u | %9u | %7u | ", |
| 272 | __ul_u32(hetrig_su_cnt), |
| 273 | __ul_u32(hetrig_2ru_cnt), |
| 274 | __ul_u32(hetrig_3ru_cnt), |
| 275 | __ul_u32(hetrig_4ru_cnt), |
| 276 | __ul_u32(hetrig_5to8ru_cnt), |
| 277 | __ul_u32(hetrig_9to16ru_cnt), |
| 278 | __ul_u32(hetrig_gtr16ru_cnt)); |
| 279 | |
| 280 | sub_total_cnt = __ul_u32(hetrig_2mu_cnt) + |
| 281 | __ul_u32(hetrig_3mu_cnt) + |
| 282 | __ul_u32(hetrig_4mu_cnt); |
| 283 | total_ppdu_cnt = sub_total_cnt; |
| 284 | |
| 285 | seq_printf(file, "\nTotal HE MU-MIMO UL TB PPDU count: %lld", |
| 286 | sub_total_cnt); |
| 287 | |
| 288 | sub_total_cnt = __ul_u32(hetrig_2ru_cnt) + |
| 289 | __ul_u32(hetrig_3ru_cnt) + |
| 290 | __ul_u32(hetrig_4ru_cnt) + |
| 291 | __ul_u32(hetrig_5to8ru_cnt) + |
| 292 | __ul_u32(hetrig_9to16ru_cnt) + |
| 293 | __ul_u32(hetrig_gtr16ru_cnt); |
| 294 | total_ppdu_cnt += sub_total_cnt; |
| 295 | |
| 296 | seq_printf(file, "\nTotal HE OFDMA UL TB PPDU count: %lld", |
| 297 | sub_total_cnt); |
| 298 | |
| 299 | total_ppdu_cnt += __ul_u32(hetrig_su_cnt); |
| 300 | |
| 301 | seq_printf(file, "\nAll HE UL TB PPDU count: %lld\n", total_ppdu_cnt); |
| 302 | #undef __ul_u32 |
| 303 | |
| 304 | exit: |
| 305 | mutex_unlock(&dev->mt76.mutex); |
| 306 | |
| 307 | return ret; |
| 308 | } |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 309 | DEFINE_SHOW_ATTRIBUTE(besra_muru_stats); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 310 | |
| 311 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 312 | besra_rdd_monitor(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 313 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 314 | struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 315 | struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; |
| 316 | const char *bw; |
| 317 | int ret = 0; |
| 318 | |
| 319 | mutex_lock(&dev->mt76.mutex); |
| 320 | |
| 321 | if (!cfg80211_chandef_valid(chandef)) { |
| 322 | ret = -EINVAL; |
| 323 | goto out; |
| 324 | } |
| 325 | |
| 326 | if (!dev->rdd2_phy) { |
| 327 | seq_puts(s, "not running\n"); |
| 328 | goto out; |
| 329 | } |
| 330 | |
| 331 | switch (chandef->width) { |
| 332 | case NL80211_CHAN_WIDTH_40: |
| 333 | bw = "40"; |
| 334 | break; |
| 335 | case NL80211_CHAN_WIDTH_80: |
| 336 | bw = "80"; |
| 337 | break; |
| 338 | case NL80211_CHAN_WIDTH_160: |
| 339 | bw = "160"; |
| 340 | break; |
| 341 | case NL80211_CHAN_WIDTH_80P80: |
| 342 | bw = "80P80"; |
| 343 | break; |
| 344 | default: |
| 345 | bw = "20"; |
| 346 | break; |
| 347 | } |
| 348 | |
| 349 | seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", |
| 350 | chandef->chan->hw_value, chandef->chan->center_freq, |
| 351 | bw, chandef->center_freq1); |
| 352 | out: |
| 353 | mutex_unlock(&dev->mt76.mutex); |
| 354 | |
| 355 | return ret; |
| 356 | } |
| 357 | |
| 358 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 359 | besra_fw_debug_wm_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 360 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 361 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 362 | enum { |
| 363 | DEBUG_TXCMD = 62, |
| 364 | DEBUG_CMD_RPT_TX, |
| 365 | DEBUG_CMD_RPT_TRIG, |
| 366 | DEBUG_SPL, |
| 367 | DEBUG_RPT_RX, |
| 368 | DEBUG_RPT_RA = 68, |
| 369 | } debug; |
| 370 | bool tx, rx, en; |
| 371 | int ret; |
| 372 | |
| 373 | dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; |
| 374 | |
| 375 | if (dev->fw_debug_bin) |
| 376 | val = MCU_FW_LOG_RELAY; |
| 377 | else |
| 378 | val = dev->fw_debug_wm; |
| 379 | |
| 380 | tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1)); |
| 381 | rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2)); |
| 382 | en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0)); |
| 383 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 384 | ret = besra_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 385 | if (ret) |
| 386 | return ret; |
| 387 | |
| 388 | for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) { |
| 389 | if (debug == 67) |
| 390 | continue; |
| 391 | |
| 392 | if (debug == DEBUG_RPT_RX) |
| 393 | val = en && rx; |
| 394 | else |
| 395 | val = en && tx; |
| 396 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 397 | ret = besra_mcu_fw_dbg_ctrl(dev, debug, val); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 398 | if (ret) |
| 399 | return ret; |
| 400 | } |
| 401 | |
| 402 | /* TODO */ |
| 403 | /* WM CPU info record control */ |
| 404 | /* mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0)); */ |
| 405 | /* mt76_wr(dev, MT_DIC_CMD_REG_CMD, BIT(2) | BIT(13) | !dev->fw_debug_wm); */ |
| 406 | /* mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5)); */ |
| 407 | /* mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5)); */ |
| 408 | |
| 409 | return 0; |
| 410 | } |
| 411 | |
| 412 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 413 | besra_fw_debug_wm_get(void *data, u64 *val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 414 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 415 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 416 | |
| 417 | *val = dev->fw_debug_wm; |
| 418 | |
| 419 | return 0; |
| 420 | } |
| 421 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 422 | DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, besra_fw_debug_wm_get, |
| 423 | besra_fw_debug_wm_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 424 | |
| 425 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 426 | besra_fw_debug_wa_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 427 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 428 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 429 | int ret; |
| 430 | |
| 431 | dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; |
| 432 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 433 | ret = besra_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 434 | if (ret) |
| 435 | return ret; |
| 436 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 437 | return besra_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 438 | !!dev->fw_debug_wa, 0); |
| 439 | } |
| 440 | |
| 441 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 442 | besra_fw_debug_wa_get(void *data, u64 *val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 443 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 444 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 445 | |
| 446 | *val = dev->fw_debug_wa; |
| 447 | |
| 448 | return 0; |
| 449 | } |
| 450 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 451 | DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, besra_fw_debug_wa_get, |
| 452 | besra_fw_debug_wa_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 453 | |
| 454 | static struct dentry * |
| 455 | create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, |
| 456 | struct rchan_buf *buf, int *is_global) |
| 457 | { |
| 458 | struct dentry *f; |
| 459 | |
| 460 | f = debugfs_create_file("fwlog_data", mode, parent, buf, |
| 461 | &relay_file_operations); |
| 462 | if (IS_ERR(f)) |
| 463 | return NULL; |
| 464 | |
| 465 | *is_global = 1; |
| 466 | |
| 467 | return f; |
| 468 | } |
| 469 | |
| 470 | static int |
| 471 | remove_buf_file_cb(struct dentry *f) |
| 472 | { |
| 473 | debugfs_remove(f); |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 479 | besra_fw_debug_bin_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 480 | { |
| 481 | static struct rchan_callbacks relay_cb = { |
| 482 | .create_buf_file = create_buf_file_cb, |
| 483 | .remove_buf_file = remove_buf_file_cb, |
| 484 | }; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 485 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 486 | |
| 487 | if (!dev->relay_fwlog) |
| 488 | dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, |
| 489 | 1500, 512, &relay_cb, NULL); |
| 490 | if (!dev->relay_fwlog) |
| 491 | return -ENOMEM; |
| 492 | |
| 493 | dev->fw_debug_bin = val; |
| 494 | |
| 495 | relay_reset(dev->relay_fwlog); |
| 496 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 497 | return besra_fw_debug_wm_set(dev, dev->fw_debug_wm); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 498 | } |
| 499 | |
| 500 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 501 | besra_fw_debug_bin_get(void *data, u64 *val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 502 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 503 | struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 504 | |
| 505 | *val = dev->fw_debug_bin; |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 510 | DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, besra_fw_debug_bin_get, |
| 511 | besra_fw_debug_bin_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 512 | |
| 513 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 514 | besra_fw_util_wm_show(struct seq_file *file, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 515 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 516 | struct besra_dev *dev = file->private; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 517 | |
| 518 | if (dev->fw_debug_wm) { |
| 519 | seq_printf(file, "Busy: %u%% Peak busy: %u%%\n", |
| 520 | mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT), |
| 521 | mt76_rr(dev, MT_CPU_UTIL_PEAK_BUSY_PCT)); |
| 522 | seq_printf(file, "Idle count: %u Peak idle count: %u\n", |
| 523 | mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT), |
| 524 | mt76_rr(dev, MT_CPU_UTIL_PEAK_IDLE_CNT)); |
| 525 | } |
| 526 | |
| 527 | return 0; |
| 528 | } |
| 529 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 530 | DEFINE_SHOW_ATTRIBUTE(besra_fw_util_wm); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 531 | |
| 532 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 533 | besra_fw_util_wa_show(struct seq_file *file, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 534 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 535 | struct besra_dev *dev = file->private; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 536 | |
| 537 | if (dev->fw_debug_wa) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 538 | return besra_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 539 | MCU_WA_PARAM_CPU_UTIL, 0, 0); |
| 540 | |
| 541 | return 0; |
| 542 | } |
| 543 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 544 | DEFINE_SHOW_ATTRIBUTE(besra_fw_util_wa); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 545 | |
| 546 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 547 | besra_ampdu_stat_read_phy(struct besra_phy *phy, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 548 | struct seq_file *file) |
| 549 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 550 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 551 | int bound[15], range[4], i, n; |
| 552 | |
| 553 | /* Tx ampdu stat */ |
| 554 | for (i = 0; i < ARRAY_SIZE(range); i++) |
| 555 | range[i] = mt76_rr(dev, MT_MIB_ARNG(phy->band_idx, i)); |
| 556 | |
| 557 | for (i = 0; i < ARRAY_SIZE(bound); i++) |
| 558 | bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1; |
| 559 | |
| 560 | seq_printf(file, "\nPhy %d, Phy band %d\n", phy->band_idx); |
| 561 | |
| 562 | seq_printf(file, "Length: %8d | ", bound[0]); |
| 563 | for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) |
| 564 | seq_printf(file, "%3d -%3d | ", |
| 565 | bound[i] + 1, bound[i + 1]); |
| 566 | |
| 567 | seq_puts(file, "\nCount: "); |
| 568 | n = phy->band_idx ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; |
| 569 | for (i = 0; i < ARRAY_SIZE(bound); i++) |
| 570 | seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i + n]); |
| 571 | seq_puts(file, "\n"); |
| 572 | |
| 573 | seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); |
| 574 | } |
| 575 | |
| 576 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 577 | besra_txbf_stat_read_phy(struct besra_phy *phy, struct seq_file *s) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 578 | { |
| 579 | static const char * const bw[] = { |
| 580 | "BW20", "BW40", "BW80", "BW160" |
| 581 | }; |
| 582 | struct mib_stats *mib = &phy->mib; |
| 583 | |
| 584 | /* Tx Beamformer monitor */ |
| 585 | seq_puts(s, "\nTx Beamformer applied PPDU counts: "); |
| 586 | |
| 587 | seq_printf(s, "iBF: %d, eBF: %d\n", |
| 588 | mib->tx_bf_ibf_ppdu_cnt, |
| 589 | mib->tx_bf_ebf_ppdu_cnt); |
| 590 | |
| 591 | /* Tx Beamformer Rx feedback monitor */ |
| 592 | seq_puts(s, "Tx Beamformer Rx feedback statistics: "); |
| 593 | |
| 594 | seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ", |
| 595 | mib->tx_bf_rx_fb_all_cnt, |
| 596 | mib->tx_bf_rx_fb_he_cnt, |
| 597 | mib->tx_bf_rx_fb_vht_cnt, |
| 598 | mib->tx_bf_rx_fb_ht_cnt); |
| 599 | |
| 600 | seq_printf(s, "%s, NC: %d, NR: %d\n", |
| 601 | bw[mib->tx_bf_rx_fb_bw], |
| 602 | mib->tx_bf_rx_fb_nc_cnt, |
| 603 | mib->tx_bf_rx_fb_nr_cnt); |
| 604 | |
| 605 | /* Tx Beamformee Rx NDPA & Tx feedback report */ |
| 606 | seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", |
| 607 | mib->tx_bf_fb_cpl_cnt); |
| 608 | seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", |
| 609 | mib->tx_bf_fb_trig_cnt); |
| 610 | |
| 611 | /* Tx SU & MU counters */ |
| 612 | seq_printf(s, "Tx multi-user Beamforming counts: %d\n", |
| 613 | mib->tx_bf_cnt); |
| 614 | seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); |
| 615 | seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", |
| 616 | mib->tx_mu_acked_mpdu_cnt); |
| 617 | seq_printf(s, "Tx single-user successful MPDU counts: %d\n", |
| 618 | mib->tx_su_acked_mpdu_cnt); |
| 619 | |
| 620 | seq_puts(s, "\n"); |
| 621 | } |
| 622 | |
| 623 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 624 | besra_tx_stats_show(struct seq_file *file, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 625 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 626 | struct besra_phy *phy = file->private; |
| 627 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 628 | struct mib_stats *mib = &phy->mib; |
| 629 | int i; |
| 630 | |
| 631 | mutex_lock(&dev->mt76.mutex); |
| 632 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 633 | besra_ampdu_stat_read_phy(phy, file); |
| 634 | besra_mac_update_stats(phy); |
| 635 | besra_txbf_stat_read_phy(phy, file); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 636 | |
| 637 | /* Tx amsdu info */ |
| 638 | seq_puts(file, "Tx MSDU statistics:\n"); |
| 639 | for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { |
| 640 | seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", |
| 641 | i + 1, mib->tx_amsdu[i]); |
| 642 | if (mib->tx_amsdu_cnt) |
| 643 | seq_printf(file, "(%3d%%)\n", |
| 644 | mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); |
| 645 | else |
| 646 | seq_puts(file, "\n"); |
| 647 | } |
| 648 | |
| 649 | mutex_unlock(&dev->mt76.mutex); |
| 650 | |
| 651 | return 0; |
| 652 | } |
| 653 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 654 | DEFINE_SHOW_ATTRIBUTE(besra_tx_stats); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 655 | |
| 656 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 657 | besra_hw_queue_read(struct seq_file *s, u32 size, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 658 | const struct hw_queue_map *map) |
| 659 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 660 | struct besra_phy *phy = s->private; |
| 661 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 662 | u32 i, val; |
| 663 | |
| 664 | val = mt76_rr(dev, MT_FL_Q_EMPTY); |
| 665 | for (i = 0; i < size; i++) { |
| 666 | u32 ctrl, head, tail, queued; |
| 667 | |
| 668 | if (val & BIT(map[i].index)) |
| 669 | continue; |
| 670 | |
| 671 | ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24); |
| 672 | mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); |
| 673 | |
| 674 | head = mt76_get_field(dev, MT_FL_Q2_CTRL, |
| 675 | GENMASK(11, 0)); |
| 676 | tail = mt76_get_field(dev, MT_FL_Q2_CTRL, |
| 677 | GENMASK(27, 16)); |
| 678 | queued = mt76_get_field(dev, MT_FL_Q3_CTRL, |
| 679 | GENMASK(11, 0)); |
| 680 | |
| 681 | seq_printf(s, "\t%s: ", map[i].name); |
| 682 | seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", |
| 683 | queued, head, tail); |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 688 | besra_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 689 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 690 | struct besra_sta *msta = (struct besra_sta *)sta->drv_priv; |
| 691 | struct besra_dev *dev = msta->vif->phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 692 | struct seq_file *s = data; |
| 693 | u8 ac; |
| 694 | |
| 695 | for (ac = 0; ac < 4; ac++) { |
| 696 | u32 qlen, ctrl, val; |
| 697 | u32 idx = msta->wcid.idx >> 5; |
| 698 | u8 offs = msta->wcid.idx & GENMASK(4, 0); |
| 699 | |
| 700 | ctrl = BIT(31) | BIT(11) | (ac << 24); |
| 701 | val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); |
| 702 | |
| 703 | if (val & BIT(offs)) |
| 704 | continue; |
| 705 | |
| 706 | mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx); |
| 707 | qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, |
| 708 | GENMASK(11, 0)); |
| 709 | seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", |
| 710 | sta->addr, msta->wcid.idx, |
| 711 | msta->vif->mt76.wmm_idx, ac, qlen); |
| 712 | } |
| 713 | } |
| 714 | |
| 715 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 716 | besra_hw_queues_show(struct seq_file *file, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 717 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 718 | struct besra_phy *phy = file->private; |
| 719 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 720 | static const struct hw_queue_map ple_queue_map[] = { |
| 721 | { "CPU_Q0", 0, 1, MT_CTX0 }, |
| 722 | { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, |
| 723 | { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, |
| 724 | { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, |
| 725 | { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, |
| 726 | { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, |
| 727 | { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, |
| 728 | { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, |
| 729 | { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, |
| 730 | { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, |
| 731 | { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, |
| 732 | { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, |
| 733 | }; |
| 734 | static const struct hw_queue_map pse_queue_map[] = { |
| 735 | { "CPU Q0", 0, 1, MT_CTX0 }, |
| 736 | { "CPU Q1", 1, 1, MT_CTX0 + 1 }, |
| 737 | { "CPU Q2", 2, 1, MT_CTX0 + 2 }, |
| 738 | { "CPU Q3", 3, 1, MT_CTX0 + 3 }, |
| 739 | { "HIF_Q0", 8, 0, MT_HIF0 }, |
| 740 | { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, |
| 741 | { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, |
| 742 | { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, |
| 743 | { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, |
| 744 | { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, |
| 745 | { "LMAC_Q", 16, 2, 0 }, |
| 746 | { "MDP_TXQ", 17, 2, 1 }, |
| 747 | { "MDP_RXQ", 18, 2, 2 }, |
| 748 | { "SEC_TXQ", 19, 2, 3 }, |
| 749 | { "SEC_RXQ", 20, 2, 4 }, |
| 750 | }; |
| 751 | u32 val, head, tail; |
| 752 | |
| 753 | /* ple queue */ |
| 754 | val = mt76_rr(dev, MT_PLE_FREEPG_CNT); |
| 755 | head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); |
| 756 | tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); |
| 757 | seq_puts(file, "PLE page info:\n"); |
| 758 | seq_printf(file, |
| 759 | "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", |
| 760 | val, head, tail); |
| 761 | |
| 762 | val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); |
| 763 | head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); |
| 764 | tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); |
| 765 | seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", |
| 766 | val, head, tail); |
| 767 | |
| 768 | seq_puts(file, "PLE non-empty queue info:\n"); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 769 | besra_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 770 | &ple_queue_map[0]); |
| 771 | |
| 772 | /* iterate per-sta ple queue */ |
| 773 | ieee80211_iterate_stations_atomic(phy->mt76->hw, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 774 | besra_sta_hw_queue_read, file); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 775 | /* pse queue */ |
| 776 | seq_puts(file, "PSE non-empty queue info:\n"); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 777 | besra_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 778 | &pse_queue_map[0]); |
| 779 | |
| 780 | return 0; |
| 781 | } |
| 782 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 783 | DEFINE_SHOW_ATTRIBUTE(besra_hw_queues); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 784 | |
| 785 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 786 | besra_xmit_queues_show(struct seq_file *file, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 787 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 788 | struct besra_phy *phy = file->private; |
| 789 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 790 | struct { |
| 791 | struct mt76_queue *q; |
| 792 | char *queue; |
| 793 | } queue_map[] = { |
| 794 | { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" }, |
| 795 | { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, |
| 796 | { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, |
| 797 | { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, |
| 798 | }; |
| 799 | int i; |
| 800 | |
| 801 | seq_puts(file, " queue | hw-queued | head | tail |\n"); |
| 802 | for (i = 0; i < ARRAY_SIZE(queue_map); i++) { |
| 803 | struct mt76_queue *q = queue_map[i].q; |
| 804 | |
| 805 | if (!q) |
| 806 | continue; |
| 807 | |
| 808 | seq_printf(file, " %s | %9d | %9d | %9d |\n", |
| 809 | queue_map[i].queue, q->queued, q->head, |
| 810 | q->tail); |
| 811 | } |
| 812 | |
| 813 | return 0; |
| 814 | } |
| 815 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 816 | DEFINE_SHOW_ATTRIBUTE(besra_xmit_queues); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 817 | |
| 818 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 819 | besra_rate_txpower_show(struct seq_file *file, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 820 | { |
| 821 | static const char * const sku_group_name[] = { |
| 822 | "CCK", "OFDM", "HT20", "HT40", |
| 823 | "VHT20", "VHT40", "VHT80", "VHT160", |
| 824 | "RU26", "RU52", "RU106", "RU242/SU20", |
| 825 | "RU484/SU40", "RU996/SU80", "RU2x996/SU160" |
| 826 | }; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 827 | struct besra_phy *phy = file->private; |
| 828 | s8 txpower[BESRA_SKU_RATE_NUM], *buf; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 829 | int i; |
| 830 | |
| 831 | seq_printf(file, "\nBand %d\n", phy->band_idx); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 832 | besra_mcu_get_txpower_sku(phy, txpower, sizeof(txpower)); |
| 833 | for (i = 0, buf = txpower; i < ARRAY_SIZE(besra_sku_group_len); i++) { |
| 834 | u8 mcs_num = besra_sku_group_len[i]; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 835 | |
| 836 | if (i >= SKU_VHT_BW20 && i <= SKU_VHT_BW160) |
| 837 | mcs_num = 10; |
| 838 | |
| 839 | mt76_seq_puts_array(file, sku_group_name[i], buf, mcs_num); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 840 | buf += besra_sku_group_len[i]; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 841 | } |
| 842 | |
| 843 | return 0; |
| 844 | } |
| 845 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 846 | DEFINE_SHOW_ATTRIBUTE(besra_rate_txpower); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 847 | |
| 848 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 849 | besra_twt_stats(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 850 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 851 | struct besra_dev *dev = dev_get_drvdata(s->private); |
| 852 | struct besra_twt_flow *iter; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 853 | |
| 854 | rcu_read_lock(); |
| 855 | |
| 856 | seq_puts(s, " wcid | id | flags | exp | mantissa"); |
| 857 | seq_puts(s, " | duration | tsf |\n"); |
| 858 | list_for_each_entry_rcu(iter, &dev->twt_list, list) |
| 859 | seq_printf(s, |
| 860 | "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", |
| 861 | iter->wcid, iter->id, |
| 862 | iter->sched ? 's' : 'u', |
| 863 | iter->protection ? 'p' : '-', |
| 864 | iter->trigger ? 't' : '-', |
| 865 | iter->flowtype ? '-' : 'a', |
| 866 | iter->exp, iter->mantissa, |
| 867 | iter->duration, iter->tsf); |
| 868 | |
| 869 | rcu_read_unlock(); |
| 870 | |
| 871 | return 0; |
| 872 | } |
| 873 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 874 | /* The index of RF registers use the generic regidx, combined with two parts: |
| 875 | * WF selection [31:28] and offset [27:0]. |
| 876 | */ |
| 877 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 878 | besra_rf_regval_get(void *data, u64 *val) |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 879 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 880 | struct besra_dev *dev = data; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 881 | u32 regval; |
| 882 | int ret; |
| 883 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 884 | ret = besra_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 885 | if (ret) |
| 886 | return ret; |
| 887 | |
| 888 | *val = le32_to_cpu(regval); |
| 889 | |
| 890 | return 0; |
| 891 | } |
| 892 | |
| 893 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 894 | besra_rf_regval_set(void *data, u64 val) |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 895 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 896 | struct besra_dev *dev = data; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 897 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 898 | return besra_mcu_rf_regval(dev, dev->mt76.debugfs_reg, (u32 *)&val, true); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 899 | } |
| 900 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 901 | DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, besra_rf_regval_get, |
| 902 | besra_rf_regval_set, "0x%08llx\n"); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 903 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 904 | int besra_init_debugfs(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 905 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 906 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 907 | struct dentry *dir; |
| 908 | |
| 909 | dir = mt76_register_debugfs_fops(phy->mt76, NULL); |
| 910 | if (!dir) |
| 911 | return -ENOMEM; |
| 912 | debugfs_create_file("muru_debug", 0600, dir, dev, &fops_muru_debug); |
| 913 | debugfs_create_file("muru_stats", 0400, dir, phy, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 914 | &besra_muru_stats_fops); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 915 | debugfs_create_file("hw-queues", 0400, dir, phy, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 916 | &besra_hw_queues_fops); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 917 | debugfs_create_file("xmit-queues", 0400, dir, phy, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 918 | &besra_xmit_queues_fops); |
| 919 | debugfs_create_file("tx_stats", 0400, dir, phy, &besra_tx_stats_fops); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 920 | debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); |
| 921 | debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); |
| 922 | debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); |
| 923 | debugfs_create_file("fw_util_wm", 0400, dir, dev, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 924 | &besra_fw_util_wm_fops); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 925 | debugfs_create_file("fw_util_wa", 0400, dir, dev, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 926 | &besra_fw_util_wa_fops); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 927 | debugfs_create_file("implicit_txbf", 0600, dir, dev, |
| 928 | &fops_implicit_txbf); |
| 929 | debugfs_create_file("txpower_sku", 0400, dir, phy, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 930 | &besra_rate_txpower_fops); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 931 | debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 932 | besra_twt_stats); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 933 | debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 934 | debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); |
| 935 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 936 | if (!dev->dbdc_support || phy->band_idx) { |
| 937 | debugfs_create_u32("dfs_hw_pattern", 0400, dir, |
| 938 | &dev->hw_pattern); |
| 939 | debugfs_create_file("radar_trigger", 0200, dir, dev, |
| 940 | &fops_radar_trigger); |
| 941 | debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 942 | besra_rdd_monitor); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 943 | } |
| 944 | |
| 945 | if (phy == &dev->phy) |
| 946 | dev->debugfs_dir = dir; |
| 947 | |
| 948 | return 0; |
| 949 | } |
| 950 | |
| 951 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 952 | besra_debugfs_write_fwlog(struct besra_dev *dev, const void *hdr, int hdrlen, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 953 | const void *data, int len) |
| 954 | { |
| 955 | static DEFINE_SPINLOCK(lock); |
| 956 | unsigned long flags; |
| 957 | void *dest; |
| 958 | |
| 959 | spin_lock_irqsave(&lock, flags); |
| 960 | dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); |
| 961 | if (dest) { |
| 962 | *(u32 *)dest = hdrlen + len; |
| 963 | dest += 4; |
| 964 | |
| 965 | if (hdrlen) { |
| 966 | memcpy(dest, hdr, hdrlen); |
| 967 | dest += hdrlen; |
| 968 | } |
| 969 | |
| 970 | memcpy(dest, data, len); |
| 971 | relay_flush(dev->relay_fwlog); |
| 972 | } |
| 973 | spin_unlock_irqrestore(&lock, flags); |
| 974 | } |
| 975 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 976 | void besra_debugfs_rx_fw_monitor(struct besra_dev *dev, const void *data, int len) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 977 | { |
| 978 | struct { |
| 979 | __le32 magic; |
| 980 | u8 version; |
| 981 | u8 _rsv; |
| 982 | __le16 serial_id; |
| 983 | __le32 timestamp; |
| 984 | __le16 msg_type; |
| 985 | __le16 len; |
| 986 | } hdr = { |
| 987 | .version = 0x1, |
| 988 | .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 989 | .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 990 | }; |
| 991 | |
| 992 | if (!dev->relay_fwlog) |
| 993 | return; |
| 994 | |
| 995 | hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++); |
| 996 | hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); |
| 997 | hdr.len = *(__le16 *)data; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 998 | besra_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 999 | } |
| 1000 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1001 | bool besra_debugfs_rx_log(struct besra_dev *dev, const void *data, int len) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1002 | { |
| 1003 | if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) |
| 1004 | return false; |
| 1005 | |
| 1006 | if (dev->relay_fwlog) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1007 | besra_debugfs_write_fwlog(dev, NULL, 0, data, len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1008 | |
| 1009 | return true; |
| 1010 | } |
| 1011 | |
| 1012 | #ifdef CONFIG_MAC80211_DEBUGFS |
| 1013 | /** per-station debugfs **/ |
| 1014 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1015 | static ssize_t besra_sta_fixed_rate_set(struct file *file, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1016 | const char __user *user_buf, |
| 1017 | size_t count, loff_t *ppos) |
| 1018 | { |
| 1019 | struct ieee80211_sta *sta = file->private_data; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1020 | struct besra_sta *msta = (struct besra_sta *)sta->drv_priv; |
| 1021 | struct besra_dev *dev = msta->vif->phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1022 | struct ieee80211_vif *vif; |
| 1023 | struct sta_phy phy = {}; |
| 1024 | char buf[100]; |
| 1025 | int ret; |
| 1026 | u32 field; |
| 1027 | u8 i, gi, he_ltf; |
| 1028 | |
| 1029 | if (count >= sizeof(buf)) |
| 1030 | return -EINVAL; |
| 1031 | |
| 1032 | if (copy_from_user(buf, user_buf, count)) |
| 1033 | return -EFAULT; |
| 1034 | |
| 1035 | if (count && buf[count - 1] == '\n') |
| 1036 | buf[count - 1] = '\0'; |
| 1037 | else |
| 1038 | buf[count] = '\0'; |
| 1039 | |
| 1040 | /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 |
| 1041 | * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3 |
| 1042 | * nss - vht: 1~4, he: 1~4, others: ignore |
| 1043 | * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2 |
| 1044 | * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 |
| 1045 | * ldpc - off: 0, on: 1 |
| 1046 | * stbc - off: 0, on: 1 |
| 1047 | * he_ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 |
| 1048 | */ |
| 1049 | if (sscanf(buf, "%hhu %hhu %hhu %hhu %hhu %hhu %hhu %hhu", |
| 1050 | &phy.type, &phy.bw, &phy.nss, &phy.mcs, &gi, |
| 1051 | &phy.ldpc, &phy.stbc, &he_ltf) != 8) { |
| 1052 | dev_warn(dev->mt76.dev, |
| 1053 | "format: Mode BW NSS MCS (HE)GI LDPC STBC HE_LTF\n"); |
| 1054 | field = RATE_PARAM_AUTO; |
| 1055 | goto out; |
| 1056 | } |
| 1057 | |
| 1058 | phy.ldpc = (phy.bw || phy.ldpc) * GENMASK(2, 0); |
| 1059 | for (i = 0; i <= phy.bw; i++) { |
| 1060 | phy.sgi |= gi << (i << sta->he_cap.has_he); |
| 1061 | phy.he_ltf |= he_ltf << (i << sta->he_cap.has_he); |
| 1062 | } |
| 1063 | field = RATE_PARAM_FIXED; |
| 1064 | |
| 1065 | out: |
| 1066 | vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1067 | ret = besra_mcu_set_fixed_rate_ctrl(dev, vif, sta, &phy, field); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1068 | if (ret) |
| 1069 | return -EFAULT; |
| 1070 | |
| 1071 | return count; |
| 1072 | } |
| 1073 | |
| 1074 | static const struct file_operations fops_fixed_rate = { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1075 | .write = besra_sta_fixed_rate_set, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1076 | .open = simple_open, |
| 1077 | .owner = THIS_MODULE, |
| 1078 | .llseek = default_llseek, |
| 1079 | }; |
| 1080 | |
| 1081 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1082 | besra_queues_show(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1083 | { |
| 1084 | struct ieee80211_sta *sta = s->private; |
| 1085 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1086 | besra_sta_hw_queue_read(s, sta); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1087 | |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1091 | DEFINE_SHOW_ATTRIBUTE(besra_queues); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1092 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1093 | void besra_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1094 | struct ieee80211_sta *sta, struct dentry *dir) |
| 1095 | { |
| 1096 | debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1097 | debugfs_create_file("hw-queues", 0400, dir, sta, &besra_queues_fops); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1098 | } |
| 1099 | |
| 1100 | #endif |