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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 5c2422be1b2ce4df54965b8dac051e525d1f5493 / . / feed / app / switch / src / an8855_sdk / api / src / air_qos.c
blob: c3829c8983828d7c4e4ffc0ab83df4e4bf66f1bc [file] [log] [blame]
developer5c2422b2024-03-08 00:27:44 +0800[diff] [blame^]1/* FILE NAME: air_qos.c
2 * PURPOSE:
3 * Define the Quailty of Service function in AIR SDK.
4 *
5 * NOTES:
6 * None
7 */
8
9 /* INCLUDE FILE DECLARATIONS
10 */
11#include "air.h"
12
13/* NAMING CONSTANT DECLARATIONS
14 */
15
16/* MACRO FUNCTION DECLARATIONS
17 */
18
19/* DATA TYPE DECLARATIONS
20 */
21
22/* GLOBAL VARIABLE DECLARATIONS
23 */
24
25/* LOCAL SUBPROGRAM DECLARATIONS
26 */
27
28/* STATIC VARIABLE DECLARATIONS
29 */
30
31/* LOCAL SUBPROGRAM BODIES
32 */
33
34/* EXPORTED SUBPROGRAM BODIES
35 */
36
37/* FUNCTION NAME: air_qos_setScheduleAlgo
38 * PURPOSE:
39 * Set schedule mode of a port queue.
40 * INPUT:
41 * unit -- Device unit number
42 * port -- Port id
43 * queue -- Queue id
44 * sch_mode -- AIR_QOS_SCH_MODE_T
45 * weight -- weight for WRR/WFQ
46 * OUTPUT:
47 * None
48 * RETURN:
49 * AIR_E_OK -- Operation success.
50 * AIR_E_BAD_PARAMETER -- Parameter is wrong.
51 * NOTES:
52 * Weight default value is 1, only for WRR/WFQ mode
53 */
54AIR_ERROR_NO_T
55air_qos_setScheduleAlgo(
56 const UI32_T unit,
57 const UI32_T port,
58 const UI32_T queue,
59 const AIR_QOS_SCH_MODE_T sch_mode,
60 const UI32_T weight)
61{
62 UI32_T rc = AIR_E_OK;
63 UI32_T mac_port = 0;
64 AIR_QOS_SHAPER_MIN_T min_v;
65 AIR_QOS_SHAPER_MAX_T max_v;
66
67 /* Check parameter */
68 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
69 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
70 AIR_PARAM_CHK((queue >= AIR_QOS_QUEUE_MAX_NUM), AIR_E_BAD_PARAMETER);
71 AIR_PARAM_CHK((sch_mode >= AIR_QOS_SCH_MODE_LAST), AIR_E_BAD_PARAMETER);
72 if (AIR_QOS_SHAPER_NOSETTING != weight)
73 {
74 AIR_PARAM_CHK(((weight > AIR_QOS_SHAPER_RATE_MAX_WEIGHT) ||
75 (weight < AIR_QOS_SHAPER_RATE_MIN_WEIGHT)), AIR_E_BAD_PARAMETER);
76 }
77 mac_port = port;
78 min_v.byte = 0;
79 max_v.byte = 0;
80 /*Read register data*/
81 switch(queue)
82 {
83 case AIR_QOS_QUEUE_0:
84 rc += aml_readReg(unit, MMSCR0_Q0(mac_port), &min_v.byte);
85 rc += aml_readReg(unit, MMSCR1_Q0(mac_port), &max_v.byte);
86 if(AIR_E_OK != rc)
87 {
88 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
89 return AIR_E_OTHERS;
90 }
91 break;
92
93 case AIR_QOS_QUEUE_1:
94 rc += aml_readReg(unit, MMSCR0_Q1(mac_port), &min_v.byte);
95 rc += aml_readReg(unit, MMSCR1_Q1(mac_port), &max_v.byte);
96 if(AIR_E_OK != rc)
97 {
98 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
99 return AIR_E_OTHERS;
100 }
101 break;
102
103 case AIR_QOS_QUEUE_2:
104 rc += aml_readReg(unit, MMSCR0_Q2(mac_port), &min_v.byte);
105 rc += aml_readReg(unit, MMSCR1_Q2(mac_port), &max_v.byte);
106 if(AIR_E_OK != rc)
107 {
108 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
109 return AIR_E_OTHERS;
110 }
111 break;
112
113 case AIR_QOS_QUEUE_3:
114 rc += aml_readReg(unit, MMSCR0_Q3(mac_port), &min_v.byte);
115 rc += aml_readReg(unit, MMSCR1_Q3(mac_port), &max_v.byte);
116 if(AIR_E_OK != rc)
117 {
118 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
119 return AIR_E_OTHERS;
120 }
121 break;
122
123 case AIR_QOS_QUEUE_4:
124 rc += aml_readReg(unit, MMSCR0_Q4(mac_port), &min_v.byte);
125 rc += aml_readReg(unit, MMSCR1_Q4(mac_port), &max_v.byte);
126 if(AIR_E_OK != rc)
127 {
128 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
129 return AIR_E_OTHERS;
130 }
131 break;
132
133 case AIR_QOS_QUEUE_5:
134 rc += aml_readReg(unit, MMSCR0_Q5(mac_port), &min_v.byte);
135 rc += aml_readReg(unit, MMSCR1_Q5(mac_port), &max_v.byte);
136 if(AIR_E_OK != rc)
137 {
138 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
139 return AIR_E_OTHERS;
140 }
141 break;
142
143 case AIR_QOS_QUEUE_6:
144 rc += aml_readReg(unit, MMSCR0_Q6(mac_port), &min_v.byte);
145 rc += aml_readReg(unit, MMSCR1_Q6(mac_port), &max_v.byte);
146 if(AIR_E_OK != rc)
147 {
148 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
149 return AIR_E_OTHERS;
150 }
151 break;
152
153 case AIR_QOS_QUEUE_7:
154 rc += aml_readReg(unit, MMSCR0_Q7(mac_port), &min_v.byte);
155 rc += aml_readReg(unit, MMSCR1_Q7(mac_port), &max_v.byte);
156 if(AIR_E_OK != rc)
157 {
158 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
159 return AIR_E_OTHERS;
160 }
161 break;
162
163 default:
164 AIR_PRINT("Not Support this queue %d num, please check again\n", queue);
165 return AIR_E_BAD_PARAMETER;
166 }
167
168 /*Get para*/
169 switch(sch_mode)
170 {
171 case AIR_QOS_SCH_MODE_SP:
172 min_v.raw.min_sp_wrr_q = 1;
173 min_v.raw.min_rate_en = 0;
174 break;
175
176 case AIR_QOS_SCH_MODE_WRR:
177 min_v.raw.min_sp_wrr_q = 0;
178 min_v.raw.min_rate_en = 0;
179 min_v.raw.min_weight = weight - 1;
180 break;
181
182 case AIR_QOS_SCH_MODE_WFQ:
183 min_v.raw.min_sp_wrr_q = 1;
184 min_v.raw.min_rate_en = 1;
185 min_v.raw.min_rate_man = 0;
186 min_v.raw.min_rate_exp = 0;
187
188 max_v.raw.max_rate_en = 0;
189 max_v.raw.max_sp_wfq_q = 0;
190 max_v.raw.max_weight = weight - 1;
191 break;
192 default:
193 AIR_PRINT("Not Support this mode %d num, please check again\n", sch_mode);
194 return AIR_E_BAD_PARAMETER;
195 }
196
197 /*Send to driver*/
198 switch(queue)
199 {
200 case AIR_QOS_QUEUE_0:
201 rc += aml_writeReg(unit, MMSCR0_Q0(mac_port), min_v.byte);
202 rc += aml_writeReg(unit, MMSCR1_Q0(mac_port), max_v.byte);
203 if(AIR_E_OK != rc)
204 {
205 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
206 return AIR_E_OTHERS;
207 }
208 break;
209
210 case AIR_QOS_QUEUE_1:
211 rc += aml_writeReg(unit, MMSCR0_Q1(mac_port), min_v.byte);
212 rc += aml_writeReg(unit, MMSCR1_Q1(mac_port), max_v.byte);
213 if(AIR_E_OK != rc)
214 {
215 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
216 return AIR_E_OTHERS;
217 }
218 break;
219
220 case AIR_QOS_QUEUE_2:
221 rc += aml_writeReg(unit, MMSCR0_Q2(mac_port), min_v.byte);
222 rc += aml_writeReg(unit, MMSCR1_Q2(mac_port), max_v.byte);
223 if(AIR_E_OK != rc)
224 {
225 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
226 return AIR_E_OTHERS;
227 }
228 break;
229
230 case AIR_QOS_QUEUE_3:
231 rc += aml_writeReg(unit, MMSCR0_Q3(mac_port), min_v.byte);
232 rc += aml_writeReg(unit, MMSCR1_Q3(mac_port), max_v.byte);
233 if(AIR_E_OK != rc)
234 {
235 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
236 return AIR_E_OTHERS;
237 }
238 break;
239
240 case AIR_QOS_QUEUE_4:
241 rc += aml_writeReg(unit, MMSCR0_Q4(mac_port), min_v.byte);
242 rc += aml_writeReg(unit, MMSCR1_Q4(mac_port), max_v.byte);
243 if(AIR_E_OK != rc)
244 {
245 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
246 return AIR_E_OTHERS;
247 }
248 break;
249
250 case AIR_QOS_QUEUE_5:
251 rc += aml_writeReg(unit, MMSCR0_Q5(mac_port), min_v.byte);
252 rc += aml_writeReg(unit, MMSCR1_Q5(mac_port), max_v.byte);
253 if(AIR_E_OK != rc)
254 {
255 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
256 return AIR_E_OTHERS;
257 }
258 break;
259
260 case AIR_QOS_QUEUE_6:
261 rc += aml_writeReg(unit, MMSCR0_Q6(mac_port), min_v.byte);
262 rc += aml_writeReg(unit, MMSCR1_Q6(mac_port), max_v.byte);
263 if(AIR_E_OK != rc)
264 {
265 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
266 return AIR_E_OTHERS;
267 }
268 break;
269
270 case AIR_QOS_QUEUE_7:
271 rc += aml_writeReg(unit, MMSCR0_Q7(mac_port), min_v.byte);
272 rc += aml_writeReg(unit, MMSCR1_Q7(mac_port), max_v.byte);
273 if(AIR_E_OK != rc)
274 {
275 AIR_PRINT("Set port %d queue %d failed, rc is %d", port, queue, rc);
276 return AIR_E_OTHERS;
277 }
278 break;
279
280 default:
281 AIR_PRINT("Not Support this queue %d num, please check again\n", queue);
282 return AIR_E_BAD_PARAMETER;
283 }
284 AIR_PRINT("Set schedule mode success,port is %d, queue is %d, min hex is %x, max hex is %x\n", port, queue, min_v.byte, max_v.byte);
285
286 return rc;
287}
288
289/* FUNCTION NAME: air_qos_getScheduleAlgo
290 * PURPOSE:
291 * Get schedule mode of a port queue.
292 *
293 * INPUT:
294 * unit -- Select device ID
295 * port -- Port id
296 * queue -- Queue id
297 * OUTPUT:
298 * ptr_sch_mode -- AIR_QOS_SCH_MODE_T
299 * ptr_weight -- weight for WRR/WFQ
300 * RETURN:
301 * AIR_E_OK
302 * AIR_E_BAD_PARAMETER
303 *
304 * NOTES:
305 * None
306 */
307AIR_ERROR_NO_T
308air_qos_getScheduleAlgo(
309 const UI32_T unit,
310 const UI32_T port,
311 const UI32_T queue,
312 AIR_QOS_SCH_MODE_T *ptr_sch_mode,
313 UI32_T *ptr_weight)
314{
315 UI32_T rc = AIR_E_OK;
316 UI32_T mac_port = 0;
317 AIR_QOS_SHAPER_MIN_T min_v;
318 AIR_QOS_SHAPER_MAX_T max_v;
319
320 /*Read register data*/
321 /* Check parameter */
322 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
323 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
324 AIR_PARAM_CHK((queue >= AIR_QOS_QUEUE_MAX_NUM), AIR_E_BAD_PARAMETER);
325 AIR_CHECK_PTR(ptr_sch_mode);
326 AIR_CHECK_PTR(ptr_weight);
327
328 mac_port = port;
329 min_v.byte = 0;
330 max_v.byte = 0;
331
332 switch(queue)
333 {
334 case AIR_QOS_QUEUE_0:
335 rc += aml_readReg(unit, MMSCR0_Q0(mac_port), &min_v.byte);
336 rc += aml_readReg(unit, MMSCR1_Q0(mac_port), &max_v.byte);
337 if(AIR_E_OK != rc)
338 {
339 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
340 return AIR_E_OTHERS;
341 }
342 break;
343
344 case AIR_QOS_QUEUE_1:
345 rc += aml_readReg(unit, MMSCR0_Q1(mac_port), &min_v.byte);
346 rc += aml_readReg(unit, MMSCR1_Q1(mac_port), &max_v.byte);
347 if(AIR_E_OK != rc)
348 {
349 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
350 return AIR_E_OTHERS;
351 }
352 break;
353
354 case AIR_QOS_QUEUE_2:
355 rc += aml_readReg(unit, MMSCR0_Q2(mac_port), &min_v.byte);
356 rc += aml_readReg(unit, MMSCR1_Q2(mac_port), &max_v.byte);
357 if(AIR_E_OK != rc)
358 {
359 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
360 return AIR_E_OTHERS;
361 }
362 break;
363
364 case AIR_QOS_QUEUE_3:
365 rc += aml_readReg(unit, MMSCR0_Q3(mac_port), &min_v.byte);
366 rc += aml_readReg(unit, MMSCR1_Q3(mac_port), &max_v.byte);
367 if(AIR_E_OK != rc)
368 {
369 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
370 return AIR_E_OTHERS;
371 }
372 break;
373
374 case AIR_QOS_QUEUE_4:
375 rc += aml_readReg(unit, MMSCR0_Q4(mac_port), &min_v.byte);
376 rc += aml_readReg(unit, MMSCR1_Q4(mac_port), &max_v.byte);
377 if(AIR_E_OK != rc)
378 {
379 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
380 return AIR_E_OTHERS;
381 }
382 break;
383
384 case AIR_QOS_QUEUE_5:
385 rc += aml_readReg(unit, MMSCR0_Q5(mac_port), &min_v.byte);
386 rc += aml_readReg(unit, MMSCR1_Q5(mac_port), &max_v.byte);
387 if(AIR_E_OK != rc)
388 {
389 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
390 return AIR_E_OTHERS;
391 }
392 break;
393
394 case AIR_QOS_QUEUE_6:
395 rc += aml_readReg(unit, MMSCR0_Q6(mac_port), &min_v.byte);
396 rc += aml_readReg(unit, MMSCR1_Q6(mac_port), &max_v.byte);
397 if(AIR_E_OK != rc)
398 {
399 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
400 return AIR_E_OTHERS;
401 }
402 break;
403
404 case AIR_QOS_QUEUE_7:
405 rc += aml_readReg(unit, MMSCR0_Q7(mac_port), &min_v.byte);
406 rc += aml_readReg(unit, MMSCR1_Q7(mac_port), &max_v.byte);
407 if(AIR_E_OK != rc)
408 {
409 AIR_PRINT("Get port %d queue %d failed, rc is %d", port, queue, rc);
410 return AIR_E_OTHERS;
411 }
412 break;
413
414 default:
415 AIR_PRINT("Not Support this queue %d num, please check again", queue);
416 return AIR_E_BAD_PARAMETER;
417 }
418
419 /*Send para*/
420 if ((min_v.raw.min_rate_en) && AIR_QOS_MAX_TRAFFIC_ARBITRATION_SCHEME_WFQ == max_v.raw.max_sp_wfq_q)
421 {
422 *ptr_sch_mode = AIR_QOS_SCH_MODE_WFQ;
423 *ptr_weight = max_v.raw.max_weight + 1;
424 }
425 else
426 {
427 if(AIR_QOS_MIN_TRAFFIC_ARBITRATION_SCHEME_WRR == min_v.raw.min_sp_wrr_q)
428 {
429 *ptr_sch_mode = AIR_QOS_SCH_MODE_WRR;
430 *ptr_weight = min_v.raw.min_weight + 1;
431 }
432 else if(AIR_QOS_MIN_TRAFFIC_ARBITRATION_SCHEME_SP == min_v.raw.min_sp_wrr_q)
433 {
434 *ptr_sch_mode = AIR_QOS_SCH_MODE_SP;
435 *ptr_weight = AIR_QOS_SHAPER_NOSETTING;
436 }
437 }
438 AIR_PRINT("Get schedule mode success,port is %d, queue is %d, min hex is %x, max hex is %x\n", port, queue, min_v.byte, max_v.byte);
439
440 return rc;
441}
442
443/* FUNCTION NAME: air_qos_setTrustMode
444 * PURPOSE:
445 * Set qos trust mode value.
446 * INPUT:
447 * unit -- Device unit number
448 * port -.Select port number
449 * mode -- Qos support mode
450 * AIR_QOS_TRUST_MODE_T
451 * OUTPUT:
452 * None
453 * RETURN:
454 * AIR_E_OK -- Operation success.
455 * AIR_E_BAD_PARAMETER -- Parameter is wrong.
456 * NOTES:
457 * None
458 */
459
460AIR_ERROR_NO_T
461air_qos_setTrustMode(
462 const UI32_T unit,
463 const UI32_T port,
464 const AIR_QOS_TRUST_MODE_T mode)
465
466{
467 UI32_T rc = AIR_E_OTHERS;
468 AIR_QOS_QUEUE_UPW_T stat;
469
470 /* Check parameter */
471 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
472 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
473 AIR_PARAM_CHK((mode >= AIR_QOS_TRUST_MODE_LAST), AIR_E_BAD_PARAMETER);
474
475 stat.byte = 0;
476 /*get register val*/
477 rc = aml_readReg(unit, PUPW(port), &(stat.byte));
478 AIR_PRINT("[Dbg]: get port %d rate trust weight success, UPW hex is %x\n", port, stat.byte);
479 stat.byte = AIR_QOS_QUEUE_DEFAULT_VAL;
480 if(AIR_E_OK == rc)
481 {
482 switch(mode)
483 {
484 case AIR_QOS_TRUST_MODE_PORT:
485 stat.raw.csr_port_weight = AIR_QOS_QUEUE_TRUST_HIGH_WEIGHT;
486 break;
487
488 case AIR_QOS_TRUST_MODE_1P_PORT:
489 stat.raw.csr_1p_weight = AIR_QOS_QUEUE_TRUST_HIGH_WEIGHT;
490 stat.raw.csr_port_weight = AIR_QOS_QUEUE_TRUST_MID_WEIGHT;
491 break;
492
493 case AIR_QOS_TRUST_MODE_DSCP_PORT:
494 stat.raw.csr_dscp_weight = AIR_QOS_QUEUE_TRUST_HIGH_WEIGHT;
495 stat.raw.csr_port_weight = AIR_QOS_QUEUE_TRUST_MID_WEIGHT;
496 break;
497
498 case AIR_QOS_TRUST_MODE_DSCP_1P_PORT:
499 stat.raw.csr_dscp_weight = AIR_QOS_QUEUE_TRUST_HIGH_WEIGHT;
500 stat.raw.csr_1p_weight = AIR_QOS_QUEUE_TRUST_MID_WEIGHT;
501 stat.raw.csr_port_weight = AIR_QOS_QUEUE_TRUST_LOW_WEIGHT;
502 break;
503
504 default:
505 AIR_PRINT("Not Support this mode %d yet\n", mode);
506 return AIR_E_BAD_PARAMETER;
507
508 }
509 }
510
511 /*set register val*/
512 rc = aml_writeReg(unit, PUPW(port), stat.byte);
513 if(AIR_E_OK != rc)
514 {
515 AIR_PRINT("[Dbg]: set port %d rate trust mode failed rc is %d\n", port, rc);
516 }
517 else
518 {
519 AIR_PRINT("[Dbg]: set port %d rate trust mode %d weight success, UPW hex is %x\n", port, mode, stat.byte);
520 }
521 return rc;
522}
523
524/* FUNCTION NAME: air_qos_getTrustMode
525 * PURPOSE:
526 * Get qos trust mode value.
527 *
528 * INPUT:
529 * unit -- Select device ID
530 * port -.Select port number
531 * OUTPUT:
532 * ptr_weight -- All Qos weight value
533 * RETURN:
534 * AIR_E_OK
535 * AIR_E_BAD_PARAMETER
536 *
537 * NOTES:
538 * None
539 */
540AIR_ERROR_NO_T
541air_qos_getTrustMode(
542 const UI32_T unit,
543 const UI32_T port,
544 AIR_QOS_TRUST_MODE_T *const ptr_mode)
545
546{
547 UI32_T rc = AIR_E_OTHERS;
548 AIR_QOS_QUEUE_UPW_T stat;
549
550 /* Check parameter */
551 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
552 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
553 AIR_CHECK_PTR(ptr_mode);
554
555 /*get register val*/
556 stat.byte = 0;
557 *ptr_mode = AIR_QOS_TRUST_MODE_1P_PORT;
558 rc = aml_readReg(unit, PUPW(port), &(stat.byte));
559 if(AIR_E_OK != rc)
560 {
561 AIR_PRINT("[Dbg]: get port %d rate trust mode failed rc is %d\n",port, rc);
562 }
563 else
564 {
565 if (AIR_QOS_QUEUE_TRUST_HIGH_WEIGHT == stat.raw.csr_1p_weight)
566 {
567 *ptr_mode = AIR_QOS_TRUST_MODE_1P_PORT;
568 }
569 else if (AIR_QOS_QUEUE_TRUST_HIGH_WEIGHT == stat.raw.csr_dscp_weight)
570 {
571 if (AIR_QOS_QUEUE_TRUST_MID_WEIGHT == stat.raw.csr_1p_weight)
572 {
573 *ptr_mode = AIR_QOS_TRUST_MODE_DSCP_1P_PORT;
574 }
575 else if (AIR_QOS_QUEUE_TRUST_MID_WEIGHT == stat.raw.csr_port_weight)
576 {
577 *ptr_mode = AIR_QOS_TRUST_MODE_DSCP_PORT;
578 }
579 }
580 else if (AIR_QOS_QUEUE_TRUST_HIGH_WEIGHT == stat.raw.csr_port_weight)
581 {
582 *ptr_mode = AIR_QOS_TRUST_MODE_PORT;
583 }
584 else
585 {
586 AIR_PRINT("[Dbg]: port %d Not support this trust mode, UPW hex is %x\n", port, stat.byte);
587 }
588 }
589 AIR_PRINT("[Dbg]: port %d get trust mode success, UPW hex is %x\n", port, stat.byte);
590 return rc;
591}
592
593/* FUNCTION NAME: air_qos_setPri2Queue
594 * PURPOSE:
595 * Set per port priority to out queue.
596 *
597 * INPUT:
598 * unit -- Select device ID
599 * pri -- Qos pri value
600 * queue -- Qos Queue value
601 *
602 * OUTPUT:
603 * None
604 *
605 * RETURN:
606 * AIR_E_OK
607 * AIR_E_BAD_PARAMETER
608 *
609 * NOTES:
610 * None
611 */
612AIR_ERROR_NO_T
613air_qos_setPri2Queue(
614 const UI32_T unit,
615 const UI32_T pri,
616 const UI32_T queue)
617{
618 UI32_T rc = AIR_E_OTHERS;
619 AIR_QOS_QUEUE_PEM_T stat;
620
621 /* Check parameter */
622 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
623 AIR_PARAM_CHK((queue >= AIR_QOS_QUEUE_MAX_NUM), AIR_E_BAD_PARAMETER);
624 AIR_PARAM_CHK((pri >= AIR_QOS_QUEUE_MAX_NUM), AIR_E_BAD_PARAMETER);
625
626 stat.byte = 0;
627 /*get register val*/
628 switch(pri / 2)
629 {
630 case 0:
631 rc = aml_readReg(unit, PEM1, &stat.byte);
632 if(AIR_E_OK == rc)
633 {
634 if (1 == pri % 2)
635 {
636 stat.raw.csr_que_cpu_h = queue;
637 }
638 else
639 {
640 stat.raw.csr_que_cpu_l = queue;
641 }
642 }
643 rc = aml_writeReg(unit, PEM1, stat.byte);
644 break;
645
646 case 1:
647 rc = aml_readReg(unit, PEM2, &stat.byte);
648 if(AIR_E_OK == rc)
649 {
650 if (1 == pri % 2)
651 {
652 stat.raw.csr_que_cpu_h = queue;
653 }
654 else
655 {
656 stat.raw.csr_que_cpu_l = queue;
657 }
658 }
659 rc = aml_writeReg(unit, PEM2, stat.byte);
660 break;
661
662 case 2:
663 rc = aml_readReg(unit, PEM3, &stat.byte);
664 if(AIR_E_OK == rc)
665 {
666 if (1 == pri % 2)
667 {
668 stat.raw.csr_que_cpu_h = queue;
669 }
670 else
671 {
672 stat.raw.csr_que_cpu_l = queue;
673 }
674 }
675 rc = aml_writeReg(unit, PEM3, stat.byte);
676 break;
677
678 case 3:
679 rc = aml_readReg(unit, PEM4, &stat.byte);
680 if(AIR_E_OK == rc)
681 {
682 if (1 == pri % 2)
683 {
684 stat.raw.csr_que_cpu_h = queue;
685 }
686 else
687 {
688 stat.raw.csr_que_cpu_l = queue;
689 }
690 }
691 rc = aml_writeReg(unit, PEM4, stat.byte);
692 break;
693
694 default:
695 AIR_PRINT("[Dbg]: Not Support this pri %d yet\n", pri);
696 return AIR_E_BAD_PARAMETER;
697 }
698 AIR_PRINT("[Dbg]: set pri %d to queue %d success, PEM hex is %x\n"
699 , pri, queue, stat.byte);
700 return rc;
701}
702
703/* FUNCTION NAME: air_qos_getPri2Queue
704 * PURPOSE:
705 * Get per port priority to out queue.
706 *
707 * INPUT:
708 * unit -- Select device ID
709 * pri -- Qos pri value
710 *
711 * OUTPUT:
712 * ptr_queue -- Select out queue (0..7)
713 *
714 * RETURN:
715 * AIR_E_OK
716 * AIR_E_BAD_PARAMETER
717 *
718 * NOTES:
719 * None
720 */
721AIR_ERROR_NO_T
722air_qos_getPri2Queue(
723 const UI32_T unit,
724 const UI32_T pri,
725 UI32_T *const ptr_queue)
726{
727 UI32_T rc = AIR_E_OTHERS;
728 AIR_QOS_QUEUE_PEM_T stat;
729
730 /* Check parameter */
731 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
732 AIR_PARAM_CHK((pri >= AIR_QOS_QUEUE_MAX_NUM), AIR_E_BAD_PARAMETER);
733 AIR_CHECK_PTR(ptr_queue);
734
735 /*get register val*/
736 stat.byte = 0;
737 switch(pri / 2)
738 {
739 case 0:
740 rc = aml_readReg(unit, PEM1, &stat.byte);
741 if(AIR_E_OK == rc)
742 {
743 if (1 == pri % 2)
744 {
745 *ptr_queue = stat.raw.csr_que_cpu_h;
746 }
747 else
748 {
749 *ptr_queue = stat.raw.csr_que_cpu_l;
750 }
751 }
752 break;
753
754 case 1:
755 rc = aml_readReg(unit, PEM2, &stat.byte);
756 if(AIR_E_OK == rc)
757 {
758 if (1 == pri % 2)
759 {
760 *ptr_queue = stat.raw.csr_que_cpu_h;
761 }
762 else
763 {
764 *ptr_queue = stat.raw.csr_que_cpu_l;
765 }
766 }
767 break;
768
769 case 2:
770 rc = aml_readReg(unit, PEM3, &stat.byte);
771 if(AIR_E_OK == rc)
772 {
773 if (1 == pri % 2)
774 {
775 *ptr_queue = stat.raw.csr_que_cpu_h;
776 }
777 else
778 {
779 *ptr_queue = stat.raw.csr_que_cpu_l;
780 }
781 }
782 break;
783
784 case 3:
785 rc = aml_readReg(unit, PEM4, &stat.byte);
786 if(AIR_E_OK == rc)
787 {
788 if (1 == pri % 2)
789 {
790 *ptr_queue = stat.raw.csr_que_cpu_h;
791 }
792 else
793 {
794 *ptr_queue = stat.raw.csr_que_cpu_l;
795 }
796 }
797 break;
798
799 default:
800 AIR_PRINT("[Dbg]: Not Support this pri %d yet\n", pri);
801 return AIR_E_BAD_PARAMETER;
802 }
803
804 if(AIR_E_OK != rc)
805 {
806 AIR_PRINT("[Dbg]: get pri to queue failed rc is %d\n", rc);
807 }
808
809 AIR_PRINT("[Dbg]: get pri %d to queue %d mode success, PEM hex is %x\n"
810 , pri, *ptr_queue, stat.byte);
811 return rc;
812}
813
814/* FUNCTION NAME: air_qos_setDscp2Pri
815 * PURPOSE:
816 * Set DSCP mapping to priority.
817 *
818 * INPUT:
819 * unit -- Select device ID
820 * dscp -- Select DSCP value (0..63)
821 * priority -- Select priority (0..7)
822 *
823 * OUTPUT:
824 * None
825 *
826 * RETURN:
827 * AIR_E_OK
828 * AIR_E_BAD_PARAMETER
829 *
830 * NOTES:
831 * None
832 */
833AIR_ERROR_NO_T
834air_qos_setDscp2Pri(
835 const UI32_T unit,
836 const UI32_T dscp,
837 const UI32_T pri)
838{
839 UI32_T rc = AIR_E_OTHERS;
840 UI32_T reg = 0;
841
842 /* Check parameter */
843 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
844 AIR_PARAM_CHK((dscp >= AIR_QOS_QUEUE_DSCP_MAX_NUM), AIR_E_BAD_PARAMETER);
845 AIR_PARAM_CHK((pri >= AIR_QOS_QUEUE_MAX_NUM), AIR_E_BAD_PARAMETER);
846
847 /*get register val*/
848 switch (dscp/10)
849 {
850 case 0:
851 rc = aml_readReg(unit, PIM1, &reg);
852 if(AIR_E_OK == rc)
853 {
854 reg &= ~(AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10));
855 reg |= pri << 3 * (dscp % 10);
856 rc = aml_writeReg(unit, PIM1, reg);
857 }
858 break;
859
860 case 1:
861 rc = aml_readReg(unit, PIM2, &reg);
862 if(AIR_E_OK == rc)
863 {
864 reg &= ~(AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10));
865 reg |= pri << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
866 rc = aml_writeReg(unit, PIM2, reg);
867 }
868 break;
869
870 case 2:
871 rc = aml_readReg(unit, PIM3, &reg);
872 if(AIR_E_OK == rc)
873 {
874 reg &= ~(AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10));
875 reg |= pri << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
876 rc = aml_writeReg(unit, PIM3, reg);
877 }
878 break;
879
880 case 3:
881 rc = aml_readReg(unit, PIM4, &reg);
882 if(AIR_E_OK == rc)
883 {
884 reg &= ~(AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10));
885 reg |= pri << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
886 rc = aml_writeReg(unit, PIM4, reg);
887 }
888 break;
889
890 case 4:
891 rc = aml_readReg(unit, PIM5, &reg);
892 if(AIR_E_OK == rc)
893 {
894 reg &= ~(AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10));
895 reg |= pri << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
896 rc = aml_writeReg(unit, PIM5, reg);
897 }
898 break;
899
900 case 5:
901 rc = aml_readReg(unit, PIM6, &reg);
902 if(AIR_E_OK == rc)
903 {
904 reg &= ~(AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10));
905 reg |= pri << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
906 rc = aml_writeReg(unit, PIM6, reg);
907 }
908 break;
909
910 case 6:
911 rc = aml_readReg(unit, PIM7, &reg);
912 if(AIR_E_OK == rc)
913 {
914 reg &= ~(AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10));
915 reg |= pri << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
916 rc = aml_writeReg(unit, PIM7, reg);
917 }
918 break;
919
920 default:
921 AIR_PRINT("Not Support this dscp %d to pri, rc is %d\n", dscp, rc);
922 return AIR_E_BAD_PARAMETER;
923 }
924
925 if(AIR_E_OK != rc)
926 {
927 AIR_PRINT("set dscp to pri failed ,rc is %d\n", rc);
928 }
929 else
930 {
931 AIR_PRINT("set dscp %u to pri %u success, PIM hex is %x\n", dscp, pri, reg);
932 }
933 return rc;
934}
935
936/* FUNCTION NAME: air_qos_getDscp2Pri
937 * PURPOSE:
938 * Get DSCP mapping priority.
939 *
940 * INPUT:
941 * unit -- Select device ID
942 * dscp -- Select DSCP value (0..63)
943 *
944 * OUTPUT:
945 * ptr_pri -- Priority value (0..7)
946 *
947 * RETURN:
948 * AIR_E_OK
949 * AIR_E_BAD_PARAMETER
950 *
951 * NOTES:
952 * None
953 */
954AIR_ERROR_NO_T
955air_qos_getDscp2Pri(
956 const UI32_T unit,
957 const UI32_T dscp,
958 UI32_T * const ptr_pri)
959{
960 UI32_T rc = AIR_E_OTHERS;
961 UI32_T reg = 0;
962
963 /* Check parameter */
964 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
965 AIR_PARAM_CHK((dscp >= AIR_QOS_QUEUE_DSCP_MAX_NUM), AIR_E_BAD_PARAMETER);
966 AIR_CHECK_PTR(ptr_pri);
967
968 /*get register val*/
969 switch (dscp/10)
970 {
971 case 0:
972 rc = aml_readReg(unit, PIM1, &reg);
973 if(AIR_E_OK == rc)
974 {
975 *ptr_pri = (reg & (AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10)))
976 >> AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
977 }
978 break;
979
980 case 1:
981 rc = aml_readReg(unit, PIM2, &reg);
982 if(AIR_E_OK == rc)
983 {
984 *ptr_pri = (reg & (AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10)))
985 >> AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
986 }
987 break;
988
989 case 2:
990 rc = aml_readReg(unit, PIM3, &reg);
991 if(AIR_E_OK == rc)
992 {
993 *ptr_pri = (reg & (AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10)))
994 >> AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
995 }
996 break;
997
998 case 3:
999 rc = aml_readReg(unit, PIM4, &reg);
1000 if(AIR_E_OK == rc)
1001 {
1002 *ptr_pri = (reg & (AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10)))
1003 >> AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
1004 }
1005 break;
1006
1007 case 4:
1008 rc = aml_readReg(unit, PIM5, &reg);
1009 if(AIR_E_OK == rc)
1010 {
1011 *ptr_pri = (reg & (AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10)))
1012 >> AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
1013 }
1014 break;
1015
1016 case 5:
1017 rc = aml_readReg(unit, PIM6, &reg);
1018 if(AIR_E_OK == rc)
1019 {
1020 *ptr_pri = (reg & (AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10)))
1021 >> AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
1022 }
1023 break;
1024
1025 case 6:
1026 rc = aml_readReg(unit, PIM7, &reg);
1027 if(AIR_E_OK == rc)
1028 {
1029 *ptr_pri = (reg & (AIR_QOS_QUEUE_PIM_MASK << AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10)))
1030 >> AIR_QOS_QUEUE_PIM_WIDTH * (dscp % 10);
1031 }
1032 break;
1033
1034 default:
1035 AIR_PRINT("Not Support this dscp %d to pri, rc is %d\n", dscp, rc);
1036 return AIR_E_BAD_PARAMETER;
1037 }
1038
1039 if(AIR_E_OK != rc)
1040 {
1041 AIR_PRINT("[Dbg]: get dscp %d to pri failed, rc is %d\n", dscp, rc);
1042 }
1043
1044 AIR_PRINT("[Dbg]: get dscp %u to pri %d success, PIM hex is %d \n", dscp, *ptr_pri, reg);
1045 return rc;
1046}
1047
1048/* FUNCTION NAME: air_qos_setRateLimitEnable
1049 * PURPOSE:
1050 * Enable or disable port rate limit.
1051 *
1052 * INPUT:
1053 * unit -- Select device ID
1054 * port -- Select port number (0..6)
1055 * dir -- AIR_QOS_RATE_DIR_INGRESS
1056 * AIR_QOS_RATE_DIR_EGRESS
1057 * rate_en -- TRUE: eanble rate limit
1058 * FALSE: disable rate limit
1059 * OUTPUT:
1060 * None
1061 *
1062 * RETURN:
1063 * AIR_E_OK
1064 * AIR_E_BAD_PARAMETER
1065 *
1066 * NOTES:
1067 * None
1068 */
1069AIR_ERROR_NO_T
1070air_qos_setRateLimitEnable(
1071 const UI32_T unit,
1072 const UI32_T port,
1073 const AIR_QOS_RATE_DIR_T dir,
1074 const BOOL_T enable)
1075{
1076 UI32_T u32dat = 0, reg = 0;
1077 UI32_T u32glo = 0, greg = 0;
1078 UI32_T mac_port = 0;
1079
1080 /* Check parameter */
1081 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1082 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
1083 AIR_PARAM_CHK((dir >= AIR_QOS_RATE_DIR_LAST), AIR_E_BAD_PARAMETER);
1084 AIR_PARAM_CHK((enable != TRUE && enable != FALSE), AIR_E_BAD_PARAMETER);
1085
1086 mac_port = port;
1087 if(AIR_QOS_RATE_DIR_EGRESS == dir)
1088 {
1089 reg = ERLCR(mac_port);
1090 greg = GERLCR;
1091 }
1092 else if (AIR_QOS_RATE_DIR_INGRESS == dir)
1093 {
1094 reg = IRLCR(mac_port);
1095 greg = GIRLCR;
1096 }
1097 else
1098 {
1099 AIR_PRINT("Not Support this dir %d yet\n", dir);
1100 return AIR_E_BAD_PARAMETER;
1101 }
1102
1103 aml_readReg(unit, reg, &u32dat);
1104 if(TRUE == enable)
1105 {
1106 u32dat |= BIT(REG_RATE_EN_OFFT);
1107 /* Enable tobke bucket mode */
1108 u32dat |= BIT(REG_TB_EN_OFFT);
1109 }
1110 else
1111 {
1112 u32dat &= ~(BIT(REG_RATE_EN_OFFT));
1113 /* Disable tobke bucket mode */
1114 u32dat &= ~(BIT(REG_TB_EN_OFFT));
1115 }
1116 aml_writeReg(unit, reg, u32dat);
1117
1118 /* Rate include preamble/IPG/CRC */
1119 aml_readReg(unit, greg, &u32glo);
1120 u32glo &= ~(BITS_RANGE(REG_IPG_BYTE_OFFT, REG_IPG_BYTE_LENG));
1121 u32glo |= AIR_QOS_L1_RATE_LIMIT;
1122 aml_writeReg(unit, greg, u32glo);
1123
1124 return AIR_E_OK;
1125}
1126
1127/* FUNCTION NAME: air_qos_getRateLimitEnable
1128 * PURPOSE:
1129 * Get port rate limit state.
1130 *
1131 * INPUT:
1132 * unit -- Select device ID
1133 * port -- Select port number (0..6)
1134 * dir -- AIR_QOS_RATE_DIR_T
1135 * OUTPUT:
1136 * ptr_enable -- TRUE: eanble rate limit
1137 * FALSE: disable rate limit
1138 * RETURN:
1139 * AIR_E_OK
1140 * AIR_E_BAD_PARAMETER
1141 *
1142 * NOTES:
1143 * None
1144 */
1145AIR_ERROR_NO_T
1146air_qos_getRateLimitEnable(
1147 const UI32_T unit,
1148 const UI32_T port,
1149 const AIR_QOS_RATE_DIR_T dir,
1150 BOOL_T *ptr_enable)
1151{
1152 UI32_T u32dat = 0, reg = 0, ret = 0;
1153 UI32_T mac_port = 0;
1154
1155 /* Check parameter */
1156 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1157 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
1158 AIR_PARAM_CHK((dir >= AIR_QOS_RATE_DIR_LAST), AIR_E_BAD_PARAMETER);
1159 AIR_CHECK_PTR(ptr_enable);
1160
1161 mac_port = port;
1162 /* Get ingress / egress register value */
1163 if(AIR_QOS_RATE_DIR_EGRESS == dir)
1164 {
1165 reg = ERLCR(mac_port);
1166 }
1167 else
1168 {
1169 reg = IRLCR(mac_port);
1170 }
1171 aml_readReg(unit, reg, &u32dat);
1172
1173 ret = (u32dat & BIT(REG_RATE_EN_OFFT));
1174 if(!ret)
1175 {
1176 *ptr_enable = FALSE;
1177 }
1178 else
1179 {
1180 *ptr_enable = TRUE;
1181 }
1182
1183 return AIR_E_OK;
1184}
1185
1186/* FUNCTION NAME: air_qos_setRateLimit
1187 * PURPOSE:
1188 * Set per port rate limit.
1189 *
1190 * INPUT:
1191 * unit -- Select device ID
1192 * port -- Select port number
1193 * ptr_cfg -- AIR_QOS_RATE_LIMIT_CFG_T
1194 *
1195 * OUTPUT:
1196 * None
1197 *
1198 * RETURN:
1199 * AIR_E_OK
1200 * AIR_E_BAD_PARAMETER
1201 *
1202 * NOTES:
1203 * None
1204 */
1205AIR_ERROR_NO_T
1206air_qos_setRateLimit(
1207 const UI32_T unit,
1208 const UI32_T port,
1209 AIR_QOS_RATE_LIMIT_CFG_T *ptr_cfg)
1210{
1211 UI32_T u32dat = 0;
1212 UI32_T mac_port = 0;
1213
1214 /* Check parameter */
1215 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1216 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
1217 AIR_CHECK_PTR(ptr_cfg);
1218 AIR_PARAM_CHK((ptr_cfg->egress_cbs >= AIR_QOS_MAX_TOKEN), AIR_E_BAD_PARAMETER);
1219 AIR_PARAM_CHK((ptr_cfg->ingress_cbs >= AIR_QOS_MAX_TOKEN), AIR_E_BAD_PARAMETER);
1220 AIR_PARAM_CHK((ptr_cfg->egress_cir >= AIR_QOS_MAX_CIR), AIR_E_BAD_PARAMETER);
1221 AIR_PARAM_CHK((ptr_cfg->ingress_cir >= AIR_QOS_MAX_CIR), AIR_E_BAD_PARAMETER);
1222
1223 mac_port = port;
1224 /* For Egress rate setting */
1225 /* Set egress rate CIR */
1226 aml_readReg(unit, ERLCR(mac_port), &u32dat);
1227 u32dat &= ~ BITS_RANGE(REG_RATE_CIR_OFFT, REG_RATE_CIR_LENG);
1228 u32dat |= ptr_cfg->egress_cir;
1229 /* Set egress rate CBS */
1230 u32dat &= ~ BITS_RANGE(REG_RATE_CBS_OFFT, REG_RATE_CBS_LENG);
1231 u32dat |= BITS_OFF_L(ptr_cfg->egress_cbs, REG_RATE_CBS_OFFT, REG_RATE_CBS_LENG);
1232 /* Enable tobke bucket mode */
1233 u32dat |= BIT(REG_TB_EN_OFFT);
1234 /* Set token period to 4ms */
1235 u32dat &= ~ BITS_RANGE(REG_RATE_TB_OFFT, REG_RATE_TB_LENG);
1236 u32dat |= BITS_OFF_L(AIR_QOS_TOKEN_PERIOD_4MS, REG_RATE_TB_OFFT, REG_RATE_TB_LENG);
1237 if(ptr_cfg->flags & AIR_QOS_RATE_LIMIT_CFG_FLAGS_ENABLE_EGRESS)
1238 {
1239 /* Enable ratelimit mode*/
1240 u32dat |= BIT(REG_RATE_EN_OFFT);
1241 }
1242 aml_writeReg(unit, ERLCR(mac_port), u32dat);
1243
1244
1245 /* For Ingress rate setting */
1246 /* Set ingress rate CIR */
1247 aml_readReg(unit, IRLCR(mac_port), &u32dat);
1248 u32dat &= ~ BITS_RANGE(REG_RATE_CIR_OFFT, REG_RATE_CIR_LENG);
1249 u32dat |= ptr_cfg->ingress_cir;
1250 /* Set egress rate CBS */
1251 u32dat &= ~ BITS_RANGE(REG_RATE_CBS_OFFT, REG_RATE_CBS_LENG);
1252 u32dat |= BITS_OFF_L(ptr_cfg->ingress_cbs, REG_RATE_CBS_OFFT, REG_RATE_CBS_LENG);
1253 /* Enable tobke bucket mode */
1254 u32dat |= BIT(REG_TB_EN_OFFT);
1255 /* Set token period to 4ms */
1256 u32dat &= ~ BITS_RANGE(REG_RATE_TB_OFFT, REG_RATE_TB_LENG);
1257 u32dat |= BITS_OFF_L(AIR_QOS_TOKEN_PERIOD_4MS, REG_RATE_TB_OFFT, REG_RATE_TB_LENG);
1258 if(ptr_cfg->flags & AIR_QOS_RATE_LIMIT_CFG_FLAGS_ENABLE_INGRESS)
1259 {
1260 /* Enable ratelimit mode*/
1261 u32dat |= BIT(REG_RATE_EN_OFFT);
1262 }
1263 aml_writeReg(unit, IRLCR(mac_port), u32dat);
1264
1265 return AIR_E_OK;
1266}
1267
1268/* FUNCTION NAME: air_qos_getRateLimit
1269 * PURPOSE:
1270 * Get per port rate limit.
1271 *
1272 * INPUT:
1273 * unit -- Select device ID
1274 * port -- Select port number
1275 *
1276 * OUTPUT:
1277 * ptr_cfg -- AIR_QOS_RATE_LIMIT_CFG_T
1278 *
1279 * RETURN:
1280 * AIR_E_OK
1281 * AIR_E_BAD_PARAMETER
1282 *
1283 * NOTES:
1284 * None
1285 */
1286AIR_ERROR_NO_T
1287air_qos_getRateLimit(
1288 const UI32_T unit,
1289 const UI32_T port,
1290 AIR_QOS_RATE_LIMIT_CFG_T *ptr_cfg)
1291{
1292 UI32_T u32dat = 0;
1293 UI32_T mac_port = 0;
1294
1295 /* Check parameter */
1296 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1297 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
1298 AIR_CHECK_PTR(ptr_cfg);
1299
1300 mac_port = port;
1301 /* For Egress rate info */
1302 aml_readReg(unit, ERLCR(mac_port), &u32dat);
1303 ptr_cfg->egress_cir = BITS_OFF_R(u32dat, REG_RATE_CIR_OFFT, REG_RATE_CIR_LENG);
1304 ptr_cfg->egress_cbs = BITS_OFF_R(u32dat, REG_RATE_CBS_OFFT, REG_RATE_CBS_LENG);
1305
1306 /* For Ingress rate info */
1307 aml_readReg(unit, IRLCR(mac_port), &u32dat);
1308 ptr_cfg->ingress_cir = BITS_OFF_R(u32dat, REG_RATE_CIR_OFFT, REG_RATE_CIR_LENG);
1309 ptr_cfg->ingress_cbs = BITS_OFF_R(u32dat, REG_RATE_CBS_OFFT, REG_RATE_CBS_LENG);
1310
1311 return AIR_E_OK;
1312}
1313
1314/* FUNCTION NAME: air_qos_setPortPriority
1315 * PURPOSE:
1316 * Get poer port based priority.
1317 *
1318 * INPUT:
1319 * unit -- Select device ID
1320 * port -- Select port number
1321 * priority -- Select port priority
1322 *
1323 * OUTPUT:
1324 * None
1325 *
1326 * RETURN:
1327 * AIR_E_OK
1328 * AIR_E_BAD_PARAMETER
1329 *
1330 * NOTES:
1331 * None
1332 */
1333AIR_ERROR_NO_T
1334air_qos_setPortPriority(
1335 const UI32_T unit,
1336 const UI32_T port,
1337 const UI32_T priority)
1338{
1339 UI32_T regPCR = 0;
1340 UI32_T mac_port = 0;
1341
1342 /* Check parameter */
1343 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1344 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
1345 AIR_PARAM_CHK((priority >= AIR_QOS_QUEUE_MAX_NUM), AIR_E_BAD_PARAMETER);
1346 mac_port = port;
1347 aml_readReg(unit, PCR(mac_port), &regPCR);
1348 regPCR &= ~PCR_PORT_PRI_MASK;
1349 regPCR |= (priority & PCR_PORT_PRI_RELMASK) << PCR_PORT_PRI_OFFT;
1350 aml_writeReg(unit, PCR(mac_port), regPCR);
1351
1352 return AIR_E_OK;
1353}
1354
1355/* FUNCTION NAME: air_qos_getPortPriority
1356 * PURPOSE:
1357 * Set per port based priority.
1358 *
1359 * INPUT:
1360 * unit -- Select device ID
1361 * port -- Select port number
1362 *
1363 * OUTPUT:
1364 * ptr_pri -- Get port based priority
1365 *
1366 * RETURN:
1367 * AIR_E_OK
1368 * AIR_E_BAD_PARAMETER
1369 *
1370 * NOTES:
1371 * None
1372 */
1373AIR_ERROR_NO_T
1374air_qos_getPortPriority(
1375 const UI32_T unit,
1376 const UI32_T port,
1377 UI32_T *ptr_pri)
1378{
1379 UI32_T regPCR = 0;
1380 UI32_T mac_port = 0;
1381
1382 /* Check parameter */
1383 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1384 AIR_PARAM_CHK((port >= AIR_MAX_NUM_OF_PORTS), AIR_E_BAD_PARAMETER);
1385 AIR_CHECK_PTR(ptr_pri);
1386 mac_port = port;
1387 aml_readReg(unit, PCR(mac_port), &regPCR);
1388 *ptr_pri = (regPCR >> PCR_PORT_PRI_OFFT) & PCR_PORT_PRI_RELMASK;
1389 return AIR_E_OK;
1390}
1391
1392/* FUNCTION NAME: air_qos_setRateLimitExMngFrm
1393 * PURPOSE:
1394 * Set rate limit control exclude/include management frames.
1395 *
1396 * INPUT:
1397 * unit -- Select device ID
1398 * dir -- AIR_RATE_DIR_INGRESS
1399 * AIR_RATE_DIR_EGRESS
1400 * exclude -- TRUE: Exclude management frame
1401 * FALSE:Include management frame
1402 * OUTPUT:
1403 * None
1404 *
1405 * RETURN:
1406 * AIR_E_OK
1407 * AIR_E_BAD_PARAMETER
1408 *
1409 * NOTES:
1410 * None
1411 */
1412AIR_ERROR_NO_T
1413air_qos_setRateLimitExMngFrm(
1414 const UI32_T unit,
1415 const AIR_QOS_RATE_DIR_T dir,
1416 const BOOL_T exclude)
1417{
1418 UI32_T u32dat = 0, reg = 0;
1419
1420 /* Check parameter */
1421 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1422 AIR_PARAM_CHK((dir != AIR_QOS_RATE_DIR_EGRESS), AIR_E_BAD_PARAMETER);
1423 AIR_PARAM_CHK(((TRUE != exclude) && (FALSE != exclude)), AIR_E_BAD_PARAMETER);
1424
1425 reg = GERLCR;
1426 /* Set to register */
1427 aml_readReg(unit, reg, &u32dat);
1428 if(TRUE == exclude)
1429 {
1430 u32dat |= BIT(REG_MFRM_EX_OFFT);
1431 }
1432 else
1433 {
1434 u32dat &= ~(BIT(REG_MFRM_EX_OFFT));
1435 }
1436 aml_writeReg(unit, reg, u32dat);
1437
1438 return AIR_E_OK;
1439}
1440
1441/* FUNCTION NAME: air_qos_getRateLimitExMngFrm
1442 * PURPOSE:
1443 * Get rate limit control exclude/include management frames.
1444 *
1445 * INPUT:
1446 * unit -- Select device ID
1447 * dir -- AIR_RATE_DIR_INGRESS
1448 * AIR_RATE_DIR_EGRESS
1449 * OUTPUT:
1450 * ptr_exclude -- TRUE: Exclude management frame
1451 * FALSE:Include management frame
1452 * RETURN:
1453 * AIR_E_OK
1454 * AIR_E_BAD_PARAMETER
1455 *
1456 * NOTES:
1457 * None
1458 */
1459AIR_ERROR_NO_T
1460air_qos_getRateLimitExMngFrm(
1461 const UI32_T unit,
1462 const AIR_QOS_RATE_DIR_T dir,
1463 BOOL_T *ptr_exclude)
1464{
1465 UI32_T reg = 0, u32dat = 0;
1466
1467 /* Check parameter */
1468 AIR_PARAM_CHK((unit >= AIR_MAX_NUM_OF_UNIT), AIR_E_BAD_PARAMETER);
1469 AIR_PARAM_CHK((dir >= AIR_QOS_RATE_DIR_LAST), AIR_E_BAD_PARAMETER);
1470 AIR_CHECK_PTR(ptr_exclude);
1471
1472
1473 if(AIR_QOS_RATE_DIR_EGRESS == dir)
1474 {
1475 reg = GERLCR;
1476 }
1477 else
1478 {
1479 reg = GIRLCR;
1480 }
1481
1482 /* Set to register */
1483 aml_readReg(unit, reg, &u32dat);
1484 if(BITS_OFF_R(u32dat, REG_MFRM_EX_OFFT, REG_MFRM_EX_LENG))
1485 {
1486 *ptr_exclude = TRUE;
1487 }
1488 else
1489 {
1490 *ptr_exclude = FALSE;
1491 }
1492
1493 return AIR_E_OK;
1494}
1495