developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */ |
| 3 | #include "mt76.h" |
| 4 | |
| 5 | const struct nla_policy mt76_tm_policy[NUM_MT76_TM_ATTRS] = { |
| 6 | [MT76_TM_ATTR_RESET] = { .type = NLA_FLAG }, |
| 7 | [MT76_TM_ATTR_STATE] = { .type = NLA_U8 }, |
| 8 | [MT76_TM_ATTR_TX_COUNT] = { .type = NLA_U32 }, |
| 9 | [MT76_TM_ATTR_TX_RATE_MODE] = { .type = NLA_U8 }, |
| 10 | [MT76_TM_ATTR_TX_RATE_NSS] = { .type = NLA_U8 }, |
| 11 | [MT76_TM_ATTR_TX_RATE_IDX] = { .type = NLA_U8 }, |
| 12 | [MT76_TM_ATTR_TX_RATE_SGI] = { .type = NLA_U8 }, |
| 13 | [MT76_TM_ATTR_TX_RATE_LDPC] = { .type = NLA_U8 }, |
| 14 | [MT76_TM_ATTR_TX_RATE_STBC] = { .type = NLA_U8 }, |
| 15 | [MT76_TM_ATTR_TX_LTF] = { .type = NLA_U8 }, |
| 16 | [MT76_TM_ATTR_TX_ANTENNA] = { .type = NLA_U8 }, |
| 17 | [MT76_TM_ATTR_TX_SPE_IDX] = { .type = NLA_U8 }, |
| 18 | [MT76_TM_ATTR_TX_POWER_CONTROL] = { .type = NLA_U8 }, |
| 19 | [MT76_TM_ATTR_TX_POWER] = { .type = NLA_NESTED }, |
| 20 | [MT76_TM_ATTR_TX_DUTY_CYCLE] = { .type = NLA_U8 }, |
| 21 | [MT76_TM_ATTR_TX_IPG] = { .type = NLA_U32 }, |
| 22 | [MT76_TM_ATTR_TX_TIME] = { .type = NLA_U32 }, |
| 23 | [MT76_TM_ATTR_FREQ_OFFSET] = { .type = NLA_U32 }, |
| 24 | [MT76_TM_ATTR_DRV_DATA] = { .type = NLA_NESTED }, |
| 25 | }; |
| 26 | EXPORT_SYMBOL_GPL(mt76_tm_policy); |
| 27 | |
| 28 | void mt76_testmode_tx_pending(struct mt76_phy *phy) |
| 29 | { |
| 30 | struct mt76_testmode_data *td = &phy->test; |
| 31 | struct mt76_dev *dev = phy->dev; |
| 32 | struct mt76_wcid *wcid = &dev->global_wcid; |
| 33 | struct sk_buff *skb = td->tx_skb; |
| 34 | struct mt76_queue *q; |
| 35 | u16 tx_queued_limit; |
| 36 | int qid; |
| 37 | |
| 38 | if (!skb || !td->tx_pending) |
| 39 | return; |
| 40 | |
| 41 | qid = skb_get_queue_mapping(skb); |
| 42 | q = phy->q_tx[qid]; |
| 43 | |
| 44 | tx_queued_limit = td->tx_queued_limit ? td->tx_queued_limit : 1000; |
| 45 | |
| 46 | spin_lock_bh(&q->lock); |
| 47 | |
| 48 | while (td->tx_pending > 0 && |
| 49 | td->tx_queued - td->tx_done < tx_queued_limit && |
| 50 | q->queued < q->ndesc / 2) { |
| 51 | int ret; |
| 52 | |
| 53 | ret = dev->queue_ops->tx_queue_skb(dev, q, skb_get(skb), wcid, |
| 54 | NULL); |
| 55 | if (ret < 0) |
| 56 | break; |
| 57 | |
| 58 | td->tx_pending--; |
| 59 | td->tx_queued++; |
| 60 | } |
| 61 | |
| 62 | dev->queue_ops->kick(dev, q); |
| 63 | |
| 64 | spin_unlock_bh(&q->lock); |
| 65 | } |
| 66 | |
| 67 | static u32 |
| 68 | mt76_testmode_max_mpdu_len(struct mt76_phy *phy, u8 tx_rate_mode) |
| 69 | { |
| 70 | switch (tx_rate_mode) { |
| 71 | case MT76_TM_TX_MODE_HT: |
| 72 | return IEEE80211_MAX_MPDU_LEN_HT_7935; |
| 73 | case MT76_TM_TX_MODE_VHT: |
| 74 | case MT76_TM_TX_MODE_HE_SU: |
| 75 | case MT76_TM_TX_MODE_HE_EXT_SU: |
| 76 | case MT76_TM_TX_MODE_HE_TB: |
| 77 | case MT76_TM_TX_MODE_HE_MU: |
| 78 | if (phy->sband_5g.sband.vht_cap.cap & |
| 79 | IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991) |
| 80 | return IEEE80211_MAX_MPDU_LEN_VHT_7991; |
| 81 | return IEEE80211_MAX_MPDU_LEN_VHT_11454; |
| 82 | case MT76_TM_TX_MODE_CCK: |
| 83 | case MT76_TM_TX_MODE_OFDM: |
| 84 | default: |
| 85 | return IEEE80211_MAX_FRAME_LEN; |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | static void |
| 90 | mt76_testmode_free_skb(struct mt76_phy *phy) |
| 91 | { |
| 92 | struct mt76_testmode_data *td = &phy->test; |
| 93 | |
| 94 | dev_kfree_skb(td->tx_skb); |
| 95 | td->tx_skb = NULL; |
| 96 | } |
| 97 | |
| 98 | int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len) |
| 99 | { |
| 100 | #define MT_TXP_MAX_LEN 4095 |
| 101 | u16 fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_DATA | |
| 102 | IEEE80211_FCTL_FROMDS; |
| 103 | struct mt76_testmode_data *td = &phy->test; |
| 104 | u8 phy_idx = mt76_get_phy_id(phy); |
| 105 | struct sk_buff **frag_tail, *head; |
| 106 | struct ieee80211_tx_info *info; |
| 107 | struct ieee80211_hdr *hdr; |
| 108 | u32 max_len, head_len; |
| 109 | int nfrags, i; |
| 110 | |
| 111 | max_len = mt76_testmode_max_mpdu_len(phy, td->tx_rate_mode); |
| 112 | if (len > max_len) |
| 113 | len = max_len; |
| 114 | else if (len < sizeof(struct ieee80211_hdr)) |
| 115 | len = sizeof(struct ieee80211_hdr); |
| 116 | |
| 117 | nfrags = len / MT_TXP_MAX_LEN; |
| 118 | head_len = nfrags ? MT_TXP_MAX_LEN : len; |
| 119 | |
| 120 | if (len > IEEE80211_MAX_FRAME_LEN) |
| 121 | fc |= IEEE80211_STYPE_QOS_DATA; |
| 122 | |
| 123 | head = alloc_skb(head_len, GFP_KERNEL); |
| 124 | if (!head) |
| 125 | return -ENOMEM; |
| 126 | |
| 127 | hdr = __skb_put_zero(head, head_len); |
| 128 | hdr->frame_control = cpu_to_le16(fc); |
| 129 | memcpy(hdr->addr1, td->addr[0], ETH_ALEN); |
| 130 | memcpy(hdr->addr2, td->addr[1], ETH_ALEN); |
| 131 | memcpy(hdr->addr3, td->addr[2], ETH_ALEN); |
| 132 | skb_set_queue_mapping(head, IEEE80211_AC_BE); |
| 133 | |
| 134 | info = IEEE80211_SKB_CB(head); |
| 135 | info->flags = IEEE80211_TX_CTL_INJECTED | |
| 136 | IEEE80211_TX_CTL_NO_ACK | |
| 137 | IEEE80211_TX_CTL_NO_PS_BUFFER; |
| 138 | |
| 139 | info->hw_queue |= FIELD_PREP(MT_TX_HW_QUEUE_PHY, phy_idx); |
| 140 | |
| 141 | frag_tail = &skb_shinfo(head)->frag_list; |
| 142 | |
| 143 | for (i = 0; i < nfrags; i++) { |
| 144 | struct sk_buff *frag; |
| 145 | u16 frag_len; |
| 146 | |
| 147 | if (i == nfrags - 1) |
| 148 | frag_len = len % MT_TXP_MAX_LEN; |
| 149 | else |
| 150 | frag_len = MT_TXP_MAX_LEN; |
| 151 | |
| 152 | frag = alloc_skb(frag_len, GFP_KERNEL); |
| 153 | if (!frag) { |
| 154 | mt76_testmode_free_skb(phy); |
| 155 | dev_kfree_skb(head); |
| 156 | return -ENOMEM; |
| 157 | } |
| 158 | |
| 159 | __skb_put_zero(frag, frag_len); |
| 160 | head->len += frag->len; |
| 161 | head->data_len += frag->len; |
| 162 | |
| 163 | *frag_tail = frag; |
| 164 | frag_tail = &(*frag_tail)->next; |
| 165 | } |
| 166 | |
| 167 | mt76_testmode_free_skb(phy); |
| 168 | td->tx_skb = head; |
| 169 | |
| 170 | return 0; |
| 171 | } |
| 172 | EXPORT_SYMBOL(mt76_testmode_alloc_skb); |
| 173 | |
| 174 | static int |
| 175 | mt76_testmode_tx_init(struct mt76_phy *phy) |
| 176 | { |
| 177 | struct mt76_testmode_data *td = &phy->test; |
| 178 | struct ieee80211_tx_info *info; |
| 179 | struct ieee80211_tx_rate *rate; |
| 180 | u8 max_nss = hweight8(phy->antenna_mask); |
| 181 | int ret; |
| 182 | |
| 183 | ret = mt76_testmode_alloc_skb(phy, td->tx_mpdu_len); |
| 184 | if (ret) |
| 185 | return ret; |
| 186 | |
| 187 | if (td->tx_rate_mode > MT76_TM_TX_MODE_VHT) |
| 188 | goto out; |
| 189 | |
| 190 | if (td->tx_antenna_mask) |
| 191 | max_nss = min_t(u8, max_nss, hweight8(td->tx_antenna_mask)); |
| 192 | |
| 193 | info = IEEE80211_SKB_CB(td->tx_skb); |
| 194 | rate = &info->control.rates[0]; |
| 195 | rate->count = 1; |
| 196 | rate->idx = td->tx_rate_idx; |
| 197 | |
| 198 | switch (td->tx_rate_mode) { |
| 199 | case MT76_TM_TX_MODE_CCK: |
| 200 | if (phy->chandef.chan->band != NL80211_BAND_2GHZ) |
| 201 | return -EINVAL; |
| 202 | |
| 203 | if (rate->idx > 4) |
| 204 | return -EINVAL; |
| 205 | break; |
| 206 | case MT76_TM_TX_MODE_OFDM: |
| 207 | if (phy->chandef.chan->band != NL80211_BAND_2GHZ) |
| 208 | break; |
| 209 | |
| 210 | if (rate->idx > 8) |
| 211 | return -EINVAL; |
| 212 | |
| 213 | rate->idx += 4; |
| 214 | break; |
| 215 | case MT76_TM_TX_MODE_HT: |
| 216 | if (rate->idx > 8 * max_nss && |
| 217 | !(rate->idx == 32 && |
| 218 | phy->chandef.width >= NL80211_CHAN_WIDTH_40)) |
| 219 | return -EINVAL; |
| 220 | |
| 221 | rate->flags |= IEEE80211_TX_RC_MCS; |
| 222 | break; |
| 223 | case MT76_TM_TX_MODE_VHT: |
| 224 | if (rate->idx > 9) |
| 225 | return -EINVAL; |
| 226 | |
| 227 | if (td->tx_rate_nss > max_nss) |
| 228 | return -EINVAL; |
| 229 | |
| 230 | ieee80211_rate_set_vht(rate, td->tx_rate_idx, td->tx_rate_nss); |
| 231 | rate->flags |= IEEE80211_TX_RC_VHT_MCS; |
| 232 | break; |
| 233 | default: |
| 234 | break; |
| 235 | } |
| 236 | |
| 237 | if (td->tx_rate_sgi) |
| 238 | rate->flags |= IEEE80211_TX_RC_SHORT_GI; |
| 239 | |
| 240 | if (td->tx_rate_ldpc) |
| 241 | info->flags |= IEEE80211_TX_CTL_LDPC; |
| 242 | |
| 243 | if (td->tx_rate_stbc) |
| 244 | info->flags |= IEEE80211_TX_CTL_STBC; |
| 245 | |
| 246 | if (td->tx_rate_mode >= MT76_TM_TX_MODE_HT) { |
| 247 | switch (phy->chandef.width) { |
| 248 | case NL80211_CHAN_WIDTH_40: |
| 249 | rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; |
| 250 | break; |
| 251 | case NL80211_CHAN_WIDTH_80: |
| 252 | rate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; |
| 253 | break; |
| 254 | case NL80211_CHAN_WIDTH_80P80: |
| 255 | case NL80211_CHAN_WIDTH_160: |
| 256 | rate->flags |= IEEE80211_TX_RC_160_MHZ_WIDTH; |
| 257 | break; |
| 258 | default: |
| 259 | break; |
| 260 | } |
| 261 | } |
| 262 | out: |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static void |
| 267 | mt76_testmode_tx_start(struct mt76_phy *phy) |
| 268 | { |
| 269 | struct mt76_testmode_data *td = &phy->test; |
| 270 | struct mt76_dev *dev = phy->dev; |
| 271 | |
| 272 | td->tx_queued = 0; |
| 273 | td->tx_done = 0; |
| 274 | td->tx_pending = td->tx_count; |
| 275 | mt76_worker_schedule(&dev->tx_worker); |
| 276 | } |
| 277 | |
| 278 | static void |
| 279 | mt76_testmode_tx_stop(struct mt76_phy *phy) |
| 280 | { |
| 281 | struct mt76_testmode_data *td = &phy->test; |
| 282 | struct mt76_dev *dev = phy->dev; |
| 283 | |
| 284 | mt76_worker_disable(&dev->tx_worker); |
| 285 | |
| 286 | td->tx_pending = 0; |
| 287 | |
| 288 | mt76_worker_enable(&dev->tx_worker); |
| 289 | |
| 290 | wait_event_timeout(dev->tx_wait, td->tx_done == td->tx_queued, |
| 291 | MT76_TM_TIMEOUT * HZ); |
| 292 | |
| 293 | mt76_testmode_free_skb(phy); |
| 294 | } |
| 295 | |
| 296 | static inline void |
| 297 | mt76_testmode_param_set(struct mt76_testmode_data *td, u16 idx) |
| 298 | { |
| 299 | td->param_set[idx / 32] |= BIT(idx % 32); |
| 300 | } |
| 301 | |
| 302 | static inline bool |
| 303 | mt76_testmode_param_present(struct mt76_testmode_data *td, u16 idx) |
| 304 | { |
| 305 | return td->param_set[idx / 32] & BIT(idx % 32); |
| 306 | } |
| 307 | |
| 308 | static void |
| 309 | mt76_testmode_init_defaults(struct mt76_phy *phy) |
| 310 | { |
| 311 | struct mt76_testmode_data *td = &phy->test; |
| 312 | |
| 313 | if (td->tx_mpdu_len > 0) |
| 314 | return; |
| 315 | |
| 316 | td->tx_mpdu_len = 1024; |
| 317 | td->tx_count = 1; |
| 318 | td->tx_rate_mode = MT76_TM_TX_MODE_OFDM; |
| 319 | td->tx_rate_nss = 1; |
| 320 | |
| 321 | memcpy(td->addr[0], phy->macaddr, ETH_ALEN); |
| 322 | memcpy(td->addr[1], phy->macaddr, ETH_ALEN); |
| 323 | memcpy(td->addr[2], phy->macaddr, ETH_ALEN); |
| 324 | } |
| 325 | |
| 326 | static int |
| 327 | __mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state) |
| 328 | { |
| 329 | enum mt76_testmode_state prev_state = phy->test.state; |
| 330 | struct mt76_dev *dev = phy->dev; |
| 331 | int err; |
| 332 | |
| 333 | if (prev_state == MT76_TM_STATE_TX_FRAMES) |
| 334 | mt76_testmode_tx_stop(phy); |
| 335 | |
| 336 | if (state == MT76_TM_STATE_TX_FRAMES) { |
| 337 | err = mt76_testmode_tx_init(phy); |
| 338 | if (err) |
| 339 | return err; |
| 340 | } |
| 341 | |
| 342 | err = dev->test_ops->set_state(phy, state); |
| 343 | if (err) { |
| 344 | if (state == MT76_TM_STATE_TX_FRAMES) |
| 345 | mt76_testmode_tx_stop(phy); |
| 346 | |
| 347 | return err; |
| 348 | } |
| 349 | |
| 350 | if (state == MT76_TM_STATE_TX_FRAMES) |
| 351 | mt76_testmode_tx_start(phy); |
| 352 | else if (state == MT76_TM_STATE_RX_FRAMES) { |
| 353 | memset(&phy->test.rx_stats, 0, sizeof(phy->test.rx_stats)); |
| 354 | } |
| 355 | |
| 356 | phy->test.state = state; |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state) |
| 362 | { |
| 363 | struct mt76_testmode_data *td = &phy->test; |
| 364 | struct ieee80211_hw *hw = phy->hw; |
| 365 | |
| 366 | if (state == td->state && state == MT76_TM_STATE_OFF) |
| 367 | return 0; |
| 368 | |
| 369 | if (state > MT76_TM_STATE_OFF && |
| 370 | (!test_bit(MT76_STATE_RUNNING, &phy->state) || |
| 371 | !(hw->conf.flags & IEEE80211_CONF_MONITOR))) |
| 372 | return -ENOTCONN; |
| 373 | |
| 374 | if (state != MT76_TM_STATE_IDLE && |
| 375 | td->state != MT76_TM_STATE_IDLE) { |
| 376 | int ret; |
| 377 | |
| 378 | ret = __mt76_testmode_set_state(phy, MT76_TM_STATE_IDLE); |
| 379 | if (ret) |
| 380 | return ret; |
| 381 | } |
| 382 | |
| 383 | return __mt76_testmode_set_state(phy, state); |
| 384 | |
| 385 | } |
| 386 | EXPORT_SYMBOL(mt76_testmode_set_state); |
| 387 | |
| 388 | static int |
| 389 | mt76_tm_get_u8(struct nlattr *attr, u8 *dest, u8 min, u8 max) |
| 390 | { |
| 391 | u8 val; |
| 392 | |
| 393 | if (!attr) |
| 394 | return 0; |
| 395 | |
| 396 | val = nla_get_u8(attr); |
| 397 | if (val < min || val > max) |
| 398 | return -EINVAL; |
| 399 | |
| 400 | *dest = val; |
| 401 | return 0; |
| 402 | } |
| 403 | |
| 404 | int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 405 | void *data, int len) |
| 406 | { |
| 407 | struct mt76_phy *phy = hw->priv; |
| 408 | struct mt76_dev *dev = phy->dev; |
| 409 | struct mt76_testmode_data *td = &phy->test; |
| 410 | struct nlattr *tb[NUM_MT76_TM_ATTRS]; |
| 411 | u32 state; |
| 412 | int err; |
| 413 | int i; |
| 414 | |
| 415 | if (!dev->test_ops) |
| 416 | return -EOPNOTSUPP; |
| 417 | |
| 418 | err = nla_parse_deprecated(tb, MT76_TM_ATTR_MAX, data, len, |
| 419 | mt76_tm_policy, NULL); |
| 420 | if (err) |
| 421 | return err; |
| 422 | |
| 423 | err = -EINVAL; |
| 424 | |
| 425 | mutex_lock(&dev->mutex); |
| 426 | |
| 427 | if (tb[MT76_TM_ATTR_RESET]) { |
| 428 | mt76_testmode_set_state(phy, MT76_TM_STATE_OFF); |
| 429 | memset(td, 0, sizeof(*td)); |
| 430 | } |
| 431 | |
| 432 | mt76_testmode_init_defaults(phy); |
| 433 | |
| 434 | if (tb[MT76_TM_ATTR_TX_COUNT]) |
| 435 | td->tx_count = nla_get_u32(tb[MT76_TM_ATTR_TX_COUNT]); |
| 436 | |
| 437 | if (tb[MT76_TM_ATTR_TX_RATE_IDX]) |
| 438 | td->tx_rate_idx = nla_get_u8(tb[MT76_TM_ATTR_TX_RATE_IDX]); |
| 439 | |
| 440 | if (mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_MODE], &td->tx_rate_mode, |
| 441 | 0, MT76_TM_TX_MODE_MAX) || |
| 442 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_NSS], &td->tx_rate_nss, |
| 443 | 1, hweight8(phy->antenna_mask)) || |
| 444 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_SGI], &td->tx_rate_sgi, 0, 2) || |
| 445 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_LDPC], &td->tx_rate_ldpc, 0, 1) || |
| 446 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_STBC], &td->tx_rate_stbc, 0, 1) || |
| 447 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_LTF], &td->tx_ltf, 0, 2) || |
| 448 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_ANTENNA], |
| 449 | &td->tx_antenna_mask, 0, 0xff) || |
| 450 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_SPE_IDX], &td->tx_spe_idx, 0, 27) || |
| 451 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE], |
| 452 | &td->tx_duty_cycle, 0, 99) || |
| 453 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_POWER_CONTROL], |
| 454 | &td->tx_power_control, 0, 1)) |
| 455 | goto out; |
| 456 | |
| 457 | if (tb[MT76_TM_ATTR_TX_LENGTH]) { |
| 458 | u32 val = nla_get_u32(tb[MT76_TM_ATTR_TX_LENGTH]); |
| 459 | |
| 460 | if (val > mt76_testmode_max_mpdu_len(phy, td->tx_rate_mode) || |
| 461 | val < sizeof(struct ieee80211_hdr)) |
| 462 | goto out; |
| 463 | |
| 464 | td->tx_mpdu_len = val; |
| 465 | } |
| 466 | |
| 467 | if (tb[MT76_TM_ATTR_TX_IPG]) |
| 468 | td->tx_ipg = nla_get_u32(tb[MT76_TM_ATTR_TX_IPG]); |
| 469 | |
| 470 | if (tb[MT76_TM_ATTR_TX_TIME]) |
| 471 | td->tx_time = nla_get_u32(tb[MT76_TM_ATTR_TX_TIME]); |
| 472 | |
| 473 | if (tb[MT76_TM_ATTR_FREQ_OFFSET]) |
| 474 | td->freq_offset = nla_get_u32(tb[MT76_TM_ATTR_FREQ_OFFSET]); |
| 475 | |
| 476 | if (tb[MT76_TM_ATTR_STATE]) { |
| 477 | state = nla_get_u32(tb[MT76_TM_ATTR_STATE]); |
| 478 | if (state > MT76_TM_STATE_MAX) |
| 479 | goto out; |
| 480 | } else { |
| 481 | state = td->state; |
| 482 | } |
| 483 | |
| 484 | if (tb[MT76_TM_ATTR_TX_POWER]) { |
| 485 | struct nlattr *cur; |
| 486 | int idx = 0; |
| 487 | int rem; |
| 488 | |
| 489 | nla_for_each_nested(cur, tb[MT76_TM_ATTR_TX_POWER], rem) { |
| 490 | if (nla_len(cur) != 1 || |
| 491 | idx >= ARRAY_SIZE(td->tx_power)) |
| 492 | goto out; |
| 493 | |
| 494 | td->tx_power[idx++] = nla_get_u8(cur); |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | if (tb[MT76_TM_ATTR_MAC_ADDRS]) { |
| 499 | struct nlattr *cur; |
| 500 | int idx = 0; |
| 501 | int rem; |
| 502 | |
| 503 | nla_for_each_nested(cur, tb[MT76_TM_ATTR_MAC_ADDRS], rem) { |
| 504 | if (nla_len(cur) != ETH_ALEN || idx >= 3) |
| 505 | goto out; |
| 506 | |
| 507 | memcpy(td->addr[idx], nla_data(cur), ETH_ALEN); |
| 508 | idx++; |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | if (dev->test_ops->set_params) { |
| 513 | err = dev->test_ops->set_params(phy, tb, state); |
| 514 | if (err) |
| 515 | goto out; |
| 516 | } |
| 517 | |
| 518 | for (i = MT76_TM_ATTR_STATE; i < ARRAY_SIZE(tb); i++) |
| 519 | if (tb[i]) |
| 520 | mt76_testmode_param_set(td, i); |
| 521 | |
| 522 | err = 0; |
| 523 | if (tb[MT76_TM_ATTR_STATE]) |
| 524 | err = mt76_testmode_set_state(phy, state); |
| 525 | |
| 526 | out: |
| 527 | mutex_unlock(&dev->mutex); |
| 528 | |
| 529 | return err; |
| 530 | } |
| 531 | EXPORT_SYMBOL(mt76_testmode_cmd); |
| 532 | |
| 533 | static int |
| 534 | mt76_testmode_dump_stats(struct mt76_phy *phy, struct sk_buff *msg) |
| 535 | { |
| 536 | struct mt76_testmode_data *td = &phy->test; |
| 537 | struct mt76_dev *dev = phy->dev; |
| 538 | u64 rx_packets = 0; |
| 539 | u64 rx_fcs_error = 0; |
| 540 | int i; |
| 541 | |
| 542 | if (dev->test_ops->dump_stats) { |
| 543 | int ret; |
| 544 | |
| 545 | ret = dev->test_ops->dump_stats(phy, msg); |
| 546 | if (ret) |
| 547 | return ret; |
| 548 | } |
| 549 | |
| 550 | for (i = 0; i < ARRAY_SIZE(td->rx_stats.packets); i++) { |
| 551 | rx_packets += td->rx_stats.packets[i]; |
| 552 | rx_fcs_error += td->rx_stats.fcs_error[i]; |
| 553 | } |
| 554 | |
| 555 | if (nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_PENDING, td->tx_pending) || |
| 556 | nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_QUEUED, td->tx_queued) || |
| 557 | nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_DONE, td->tx_done) || |
| 558 | nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_PACKETS, rx_packets, |
| 559 | MT76_TM_STATS_ATTR_PAD) || |
| 560 | nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_FCS_ERROR, rx_fcs_error, |
| 561 | MT76_TM_STATS_ATTR_PAD)) |
| 562 | return -EMSGSIZE; |
| 563 | |
| 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg, |
| 568 | struct netlink_callback *cb, void *data, int len) |
| 569 | { |
| 570 | struct mt76_phy *phy = hw->priv; |
| 571 | struct mt76_dev *dev = phy->dev; |
| 572 | struct mt76_testmode_data *td = &phy->test; |
| 573 | struct nlattr *tb[NUM_MT76_TM_ATTRS] = {}; |
| 574 | int err = 0; |
| 575 | void *a; |
| 576 | int i; |
| 577 | |
| 578 | if (!dev->test_ops) |
| 579 | return -EOPNOTSUPP; |
| 580 | |
| 581 | if (cb->args[2]++ > 0) |
| 582 | return -ENOENT; |
| 583 | |
| 584 | if (data) { |
| 585 | err = nla_parse_deprecated(tb, MT76_TM_ATTR_MAX, data, len, |
| 586 | mt76_tm_policy, NULL); |
| 587 | if (err) |
| 588 | return err; |
| 589 | } |
| 590 | |
| 591 | mutex_lock(&dev->mutex); |
| 592 | |
| 593 | if (tb[MT76_TM_ATTR_STATS]) { |
| 594 | err = -EINVAL; |
| 595 | |
| 596 | a = nla_nest_start(msg, MT76_TM_ATTR_STATS); |
| 597 | if (a) { |
| 598 | err = mt76_testmode_dump_stats(phy, msg); |
| 599 | nla_nest_end(msg, a); |
| 600 | } |
| 601 | |
| 602 | goto out; |
| 603 | } |
| 604 | |
| 605 | mt76_testmode_init_defaults(phy); |
| 606 | |
| 607 | err = -EMSGSIZE; |
| 608 | if (nla_put_u32(msg, MT76_TM_ATTR_STATE, td->state)) |
| 609 | goto out; |
| 610 | |
| 611 | if (dev->test_mtd.name && |
| 612 | (nla_put_string(msg, MT76_TM_ATTR_MTD_PART, dev->test_mtd.name) || |
| 613 | nla_put_u32(msg, MT76_TM_ATTR_MTD_OFFSET, dev->test_mtd.offset))) |
| 614 | goto out; |
| 615 | |
| 616 | if (nla_put_u32(msg, MT76_TM_ATTR_TX_COUNT, td->tx_count) || |
| 617 | nla_put_u32(msg, MT76_TM_ATTR_TX_LENGTH, td->tx_mpdu_len) || |
| 618 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_MODE, td->tx_rate_mode) || |
| 619 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_NSS, td->tx_rate_nss) || |
| 620 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_IDX, td->tx_rate_idx) || |
| 621 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_SGI, td->tx_rate_sgi) || |
| 622 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, td->tx_rate_ldpc) || |
| 623 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_STBC, td->tx_rate_stbc) || |
| 624 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_LTF) && |
| 625 | nla_put_u8(msg, MT76_TM_ATTR_TX_LTF, td->tx_ltf)) || |
| 626 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_ANTENNA) && |
| 627 | nla_put_u8(msg, MT76_TM_ATTR_TX_ANTENNA, td->tx_antenna_mask)) || |
| 628 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_SPE_IDX) && |
| 629 | nla_put_u8(msg, MT76_TM_ATTR_TX_SPE_IDX, td->tx_spe_idx)) || |
| 630 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_DUTY_CYCLE) && |
| 631 | nla_put_u8(msg, MT76_TM_ATTR_TX_DUTY_CYCLE, td->tx_duty_cycle)) || |
| 632 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_IPG) && |
| 633 | nla_put_u32(msg, MT76_TM_ATTR_TX_IPG, td->tx_ipg)) || |
| 634 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_TIME) && |
| 635 | nla_put_u32(msg, MT76_TM_ATTR_TX_TIME, td->tx_time)) || |
| 636 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_POWER_CONTROL) && |
| 637 | nla_put_u8(msg, MT76_TM_ATTR_TX_POWER_CONTROL, td->tx_power_control)) || |
| 638 | (mt76_testmode_param_present(td, MT76_TM_ATTR_FREQ_OFFSET) && |
| 639 | nla_put_u8(msg, MT76_TM_ATTR_FREQ_OFFSET, td->freq_offset))) |
| 640 | goto out; |
| 641 | |
| 642 | if (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_POWER)) { |
| 643 | a = nla_nest_start(msg, MT76_TM_ATTR_TX_POWER); |
| 644 | if (!a) |
| 645 | goto out; |
| 646 | |
| 647 | for (i = 0; i < ARRAY_SIZE(td->tx_power); i++) |
| 648 | if (nla_put_u8(msg, i, td->tx_power[i])) |
| 649 | goto out; |
| 650 | |
| 651 | nla_nest_end(msg, a); |
| 652 | } |
| 653 | |
| 654 | if (mt76_testmode_param_present(td, MT76_TM_ATTR_MAC_ADDRS)) { |
| 655 | a = nla_nest_start(msg, MT76_TM_ATTR_MAC_ADDRS); |
| 656 | if (!a) |
| 657 | goto out; |
| 658 | |
| 659 | for (i = 0; i < 3; i++) |
| 660 | if (nla_put(msg, i, ETH_ALEN, td->addr[i])) |
| 661 | goto out; |
| 662 | |
| 663 | nla_nest_end(msg, a); |
| 664 | } |
| 665 | |
| 666 | err = 0; |
| 667 | |
| 668 | out: |
| 669 | mutex_unlock(&dev->mutex); |
| 670 | |
| 671 | return err; |
| 672 | } |
| 673 | EXPORT_SYMBOL(mt76_testmode_dump); |