developer | e3d0147 | 2022-05-09 14:01:49 +0800 | [diff] [blame] | 1 | From f3f9ccbb417cae6e503084e13d627b68a141b0bd Mon Sep 17 00:00:00 2001 |
| 2 | From: Bo Jiao <Bo.Jiao@mediatek.com> |
| 3 | Date: Thu, 5 May 2022 11:45:23 +0800 |
| 4 | Subject: [PATCH 02/10] mt76: mt7915: reowrk SER debugfs knob |
| 5 | |
| 6 | 1. get status of system recovery from firmware. |
| 7 | 2. add more recovery points. |
| 8 | 3. make knob per phy. |
| 9 | |
| 10 | Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com> |
| 11 | Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> |
| 12 | --- |
| 13 | mt7915/debugfs.c | 106 ++++++++++++++++++++++++++++++++++++++++------- |
| 14 | mt7915/mcu.c | 5 +-- |
| 15 | mt7915/mcu.h | 14 +++++++ |
| 16 | mt7915/mmio.c | 3 ++ |
| 17 | mt7915/regs.h | 18 +++++++- |
| 18 | 5 files changed, 126 insertions(+), 20 deletions(-) |
| 19 | |
| 20 | diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c |
| 21 | index 77bbeeed..b45181c1 100644 |
| 22 | --- a/mt7915/debugfs.c |
| 23 | +++ b/mt7915/debugfs.c |
| 24 | @@ -44,35 +44,113 @@ mt7915_implicit_txbf_get(void *data, u64 *val) |
| 25 | DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get, |
| 26 | mt7915_implicit_txbf_set, "%lld\n"); |
| 27 | |
| 28 | -/* test knob of system layer 1/2 error recovery */ |
| 29 | -static int mt7915_ser_trigger_set(void *data, u64 val) |
| 30 | +/* test knob of system error recovery */ |
| 31 | +static ssize_t |
| 32 | +mt7915_fw_ser_set(struct file *file, const char __user *user_buf, |
| 33 | + size_t count, loff_t *ppos) |
| 34 | { |
| 35 | - enum { |
| 36 | - SER_SET_RECOVER_L1 = 1, |
| 37 | - SER_SET_RECOVER_L2, |
| 38 | - SER_ENABLE = 2, |
| 39 | - SER_RECOVER |
| 40 | - }; |
| 41 | - struct mt7915_dev *dev = data; |
| 42 | + struct mt7915_phy *phy = file->private_data; |
| 43 | + struct mt7915_dev *dev = phy->dev; |
| 44 | + bool ext_phy = phy != &dev->phy; |
| 45 | + char buf[16]; |
| 46 | int ret = 0; |
| 47 | + u16 val; |
| 48 | + |
| 49 | + if (count >= sizeof(buf)) |
| 50 | + return -EINVAL; |
| 51 | + |
| 52 | + if (copy_from_user(buf, user_buf, count)) |
| 53 | + return -EFAULT; |
| 54 | + |
| 55 | + if (count && buf[count - 1] == '\n') |
| 56 | + buf[count - 1] = '\0'; |
| 57 | + else |
| 58 | + buf[count] = '\0'; |
| 59 | + |
| 60 | + if (kstrtou16(buf, 0, &val)) |
| 61 | + return -EINVAL; |
| 62 | |
| 63 | switch (val) { |
| 64 | + case SER_QUERY: |
| 65 | + /* grab firmware SER stats */ |
| 66 | + ret = mt7915_mcu_set_ser(dev, 0, 0, ext_phy); |
| 67 | + break; |
| 68 | case SER_SET_RECOVER_L1: |
| 69 | case SER_SET_RECOVER_L2: |
| 70 | - ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), 0); |
| 71 | + case SER_SET_RECOVER_L3_RX_ABORT: |
| 72 | + case SER_SET_RECOVER_L3_TX_ABORT: |
| 73 | + case SER_SET_RECOVER_L3_TX_DISABLE: |
| 74 | + case SER_SET_RECOVER_L3_BF: |
| 75 | + ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), ext_phy); |
| 76 | if (ret) |
| 77 | return ret; |
| 78 | |
| 79 | - return mt7915_mcu_set_ser(dev, SER_RECOVER, val, 0); |
| 80 | + ret = mt7915_mcu_set_ser(dev, SER_RECOVER, val, ext_phy); |
| 81 | + break; |
| 82 | default: |
| 83 | break; |
| 84 | } |
| 85 | |
| 86 | + return ret ? ret : count; |
| 87 | +} |
| 88 | + |
| 89 | +static ssize_t |
| 90 | +mt7915_fw_ser_get(struct file *file, char __user *user_buf, |
| 91 | + size_t count, loff_t *ppos) |
| 92 | +{ |
| 93 | + struct mt7915_phy *phy = file->private_data; |
| 94 | + struct mt7915_dev *dev = phy->dev; |
| 95 | + char *buff; |
| 96 | + int desc = 0; |
| 97 | + ssize_t ret; |
| 98 | + static const size_t bufsz = 400; |
| 99 | + |
| 100 | + buff = kmalloc(bufsz, GFP_KERNEL); |
| 101 | + if (!buff) |
| 102 | + return -ENOMEM; |
| 103 | + |
| 104 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 105 | + "::E R , SER_STATUS = 0x%08x\n", |
| 106 | + mt76_rr(dev, MT_SWDEF_SER_STATS)); |
| 107 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 108 | + "::E R , SER_PLE_ERR = 0x%08x\n", |
| 109 | + mt76_rr(dev, MT_SWDEF_PLE_STATS)); |
| 110 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 111 | + "::E R , SER_PLE_ERR_1 = 0x%08x\n", |
| 112 | + mt76_rr(dev, MT_SWDEF_PLE1_STATS)); |
| 113 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 114 | + "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n", |
| 115 | + mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); |
| 116 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 117 | + "::E R , SER_PSE_ERR = 0x%08x\n", |
| 118 | + mt76_rr(dev, MT_SWDEF_PSE_STATS)); |
| 119 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 120 | + "::E R , SER_PSE_ERR_1 = 0x%08x\n", |
| 121 | + mt76_rr(dev, MT_SWDEF_PSE1_STATS)); |
| 122 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 123 | + "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n", |
| 124 | + mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); |
| 125 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 126 | + "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n", |
| 127 | + mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); |
| 128 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 129 | + "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n", |
| 130 | + mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); |
| 131 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 132 | + "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n", |
| 133 | + mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); |
| 134 | + |
| 135 | + ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); |
| 136 | + kfree(buff); |
| 137 | return ret; |
| 138 | } |
| 139 | |
| 140 | -DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL, |
| 141 | - mt7915_ser_trigger_set, "%lld\n"); |
| 142 | +static const struct file_operations mt7915_fw_ser_ops = { |
| 143 | + .write = mt7915_fw_ser_set, |
| 144 | + .read = mt7915_fw_ser_get, |
| 145 | + .open = simple_open, |
| 146 | + .llseek = default_llseek, |
| 147 | +}; |
| 148 | |
| 149 | static int |
| 150 | mt7915_radar_trigger(void *data, u64 val) |
| 151 | @@ -914,6 +992,7 @@ int mt7915_init_debugfs(struct mt7915_phy *phy) |
| 152 | debugfs_create_file("xmit-queues", 0400, dir, phy, |
| 153 | &mt7915_xmit_queues_fops); |
| 154 | debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops); |
| 155 | + debugfs_create_file("fw_ser", 0600, dir, phy, &mt7915_fw_ser_ops); |
| 156 | debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); |
| 157 | debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); |
| 158 | debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); |
| 159 | @@ -927,7 +1006,6 @@ int mt7915_init_debugfs(struct mt7915_phy *phy) |
| 160 | &mt7915_rate_txpower_fops); |
| 161 | debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, |
| 162 | mt7915_twt_stats); |
| 163 | - debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger); |
| 164 | debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); |
| 165 | |
| 166 | if (!dev->dbdc_support || phy->band_idx) { |
| 167 | diff --git a/mt7915/mcu.c b/mt7915/mcu.c |
| 168 | index c215bc9e..20f32f7f 100644 |
| 169 | --- a/mt7915/mcu.c |
| 170 | +++ b/mt7915/mcu.c |
| 171 | @@ -2471,10 +2471,7 @@ int mt7915_mcu_init(struct mt7915_dev *dev) |
| 172 | /* force firmware operation mode into normal state, |
| 173 | * which should be set before firmware download stage. |
| 174 | */ |
| 175 | - if (is_mt7915(&dev->mt76)) |
| 176 | - mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE); |
| 177 | - else |
| 178 | - mt76_wr(dev, MT_SWDEF_MODE_MT7916, MT_SWDEF_NORMAL_MODE); |
| 179 | + mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE); |
| 180 | |
| 181 | ret = mt7915_driver_own(dev, 0); |
| 182 | if (ret) |
| 183 | diff --git a/mt7915/mcu.h b/mt7915/mcu.h |
| 184 | index df7aefca..5cbc3ecf 100644 |
| 185 | --- a/mt7915/mcu.h |
| 186 | +++ b/mt7915/mcu.h |
| 187 | @@ -464,6 +464,20 @@ enum { |
| 188 | MURU_GET_TXC_TX_STATS = 151, |
| 189 | }; |
| 190 | |
| 191 | +enum { |
| 192 | + SER_QUERY, |
| 193 | + /* recovery */ |
| 194 | + SER_SET_RECOVER_L1, |
| 195 | + SER_SET_RECOVER_L2, |
| 196 | + SER_SET_RECOVER_L3_RX_ABORT, |
| 197 | + SER_SET_RECOVER_L3_TX_ABORT, |
| 198 | + SER_SET_RECOVER_L3_TX_DISABLE, |
| 199 | + SER_SET_RECOVER_L3_BF, |
| 200 | + /* action */ |
| 201 | + SER_ENABLE = 2, |
| 202 | + SER_RECOVER |
| 203 | +}; |
| 204 | + |
| 205 | #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ |
| 206 | sizeof(struct bss_info_omac) + \ |
| 207 | sizeof(struct bss_info_basic) +\ |
| 208 | diff --git a/mt7915/mmio.c b/mt7915/mmio.c |
| 209 | index 0bd32daa..2d733d32 100644 |
| 210 | --- a/mt7915/mmio.c |
| 211 | +++ b/mt7915/mmio.c |
| 212 | @@ -22,6 +22,7 @@ static const u32 mt7915_reg[] = { |
| 213 | [WFDMA_EXT_CSR_ADDR] = 0xd7000, |
| 214 | [CBTOP1_PHY_END] = 0x77ffffff, |
| 215 | [INFRA_MCU_ADDR_END] = 0x7c3fffff, |
| 216 | + [SWDEF_BASE_ADDR] = 0x41f200, |
| 217 | }; |
| 218 | |
| 219 | static const u32 mt7916_reg[] = { |
| 220 | @@ -36,6 +37,7 @@ static const u32 mt7916_reg[] = { |
| 221 | [WFDMA_EXT_CSR_ADDR] = 0xd7000, |
| 222 | [CBTOP1_PHY_END] = 0x7fffffff, |
| 223 | [INFRA_MCU_ADDR_END] = 0x7c085fff, |
| 224 | + [SWDEF_BASE_ADDR] = 0x411400, |
| 225 | }; |
| 226 | |
| 227 | static const u32 mt7986_reg[] = { |
| 228 | @@ -50,6 +52,7 @@ static const u32 mt7986_reg[] = { |
| 229 | [WFDMA_EXT_CSR_ADDR] = 0x27000, |
| 230 | [CBTOP1_PHY_END] = 0x7fffffff, |
| 231 | [INFRA_MCU_ADDR_END] = 0x7c085fff, |
| 232 | + [SWDEF_BASE_ADDR] = 0x411400, |
| 233 | }; |
| 234 | |
| 235 | static const u32 mt7915_offs[] = { |
| 236 | diff --git a/mt7915/regs.h b/mt7915/regs.h |
| 237 | index 97984aaf..4251cf78 100644 |
| 238 | --- a/mt7915/regs.h |
| 239 | +++ b/mt7915/regs.h |
| 240 | @@ -30,6 +30,7 @@ enum reg_rev { |
| 241 | WFDMA_EXT_CSR_ADDR, |
| 242 | CBTOP1_PHY_END, |
| 243 | INFRA_MCU_ADDR_END, |
| 244 | + SWDEF_BASE_ADDR, |
| 245 | __MT_REG_MAX, |
| 246 | }; |
| 247 | |
| 248 | @@ -942,12 +943,25 @@ enum offs_rev { |
| 249 | #define MT_ADIE_TYPE_MASK BIT(1) |
| 250 | |
| 251 | /* FW MODE SYNC */ |
| 252 | -#define MT_SWDEF_MODE 0x41f23c |
| 253 | -#define MT_SWDEF_MODE_MT7916 0x41143c |
| 254 | +#define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR) |
| 255 | + |
| 256 | +#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) |
| 257 | +#define MT_SWDEF_MODE MT_SWDEF(0x3c) |
| 258 | #define MT_SWDEF_NORMAL_MODE 0 |
| 259 | #define MT_SWDEF_ICAP_MODE 1 |
| 260 | #define MT_SWDEF_SPECTRUM_MODE 2 |
| 261 | |
| 262 | +#define MT_SWDEF_SER_STATS MT_SWDEF(0x040) |
| 263 | +#define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) |
| 264 | +#define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) |
| 265 | +#define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C) |
| 266 | +#define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) |
| 267 | +#define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) |
| 268 | +#define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) |
| 269 | +#define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C) |
| 270 | +#define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060) |
| 271 | +#define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064) |
| 272 | + |
| 273 | #define MT_DIC_CMD_REG_BASE 0x41f000 |
| 274 | #define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs)) |
| 275 | #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10) |
| 276 | -- |
| 277 | 2.18.0 |
| 278 | |