| developer | e5e687d | 2023-08-08 16:05:33 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Copyright (c) 2023 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TOPS_NETSYS_H_ |
| 9 | #define _TOPS_NETSYS_H_ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | #include <linux/bitfield.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | |
| 15 | #include "tunnel.h" |
| 16 | |
| 17 | /* FE BASE */ |
| 18 | #define FE_BASE (0x0000) |
| 19 | |
| 20 | /* PPE BASE */ |
| 21 | #define PPE0_BASE (0x2000) |
| 22 | #define PPE1_BASE (0x2400) |
| 23 | #define PPE2_BASE (0x2C00) |
| 24 | |
| 25 | /* FE_INT */ |
| 26 | #define FE_INT_GRP (0x0020) |
| 27 | #define FE_INT_STA2 (0x0028) |
| 28 | #define FE_INT_EN2 (0x002C) |
| 29 | |
| 30 | /* PSE IQ/OQ */ |
| 31 | #define PSE_IQ_STA6 (0x0194) |
| 32 | #define PSE_OQ_STA6 (0x01B4) |
| 33 | |
| 34 | /* PPE */ |
| 35 | #define PPE_TBL_CFG (0x021C) |
| 36 | |
| 37 | /* FE_INT_GRP */ |
| 38 | #define FE_MISC_INT_ASG_SHIFT (0) |
| 39 | #define FE_MISC_INT_ASG_MASK GENMASK(3, 0) |
| 40 | |
| 41 | /* FE_INT_STA2/FE_INT_EN2 */ |
| 42 | #define PSE_FC_ON_1_SHIFT (0) |
| 43 | #define PSE_FC_ON_1_MASK GENMASK(6, 0) |
| 44 | #define TDMA_TX_PAUSE (BIT(2)) |
| 45 | |
| 46 | /* PSE IQ/OQ PORT */ |
| 47 | #define TDMA_PORT_SHIFT (0) |
| 48 | #define TDMA_PORT_MASK GENMASK(15, 0) |
| 49 | |
| 50 | u32 mtk_tops_netsys_ppe_get_max_entry_num(u32 ppe_id); |
| 51 | int mtk_tops_netsys_init(struct platform_device *pdev); |
| 52 | void mtk_tops_netsys_deinit(struct platform_device *pdev); |
| 53 | #endif /* _TOPS_NETSYS_H_ */ |