blob: fed76758c68991e33b9b961def830744022e458b [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +08001From 475f064022a716bda4574406d8365627c3bcf131 Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:19 +0800
4Subject: [PATCH]
5 [spi-and-storage][999-2366-fix-SPIM-dma-buffer-not-aligned.patch]
6
7---
8 drivers/spi/spi-mt65xx.c | 33 +++++++++++++++++++++++----------
9 1 file changed, 23 insertions(+), 10 deletions(-)
10
11diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
12index 05697e1d1..2883dc908 100644
developere451caf2021-05-11 21:57:51 +080013--- a/drivers/spi/spi-mt65xx.c
14+++ b/drivers/spi/spi-mt65xx.c
developer5d148cb2023-06-02 13:08:11 +080015@@ -184,7 +184,7 @@ static const struct mtk_spi_compatible mt8183_compat = {
developere451caf2021-05-11 21:57:51 +080016 */
17 static const struct mtk_chip_config mtk_default_chip_info = {
18 .sample_sel = 0,
19- .get_tick_dly = 0,
20+ .get_tick_dly = 1,
21 };
22
23 static const struct of_device_id mtk_spi_of_match[] = {
developer5d148cb2023-06-02 13:08:11 +080024@@ -731,8 +731,11 @@ static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
developere451caf2021-05-11 21:57:51 +080025
26 if (op->data.dir != SPI_MEM_NO_DATA) {
27 opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
28- if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE)
29+ if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
30 op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE -opcode_len;
31+ /* force data buffer dma-aligned. */
32+ op->data.nbytes -= op->data.nbytes % 4;
33+ }
34 }
35
36 return 0;
developer5d148cb2023-06-02 13:08:11 +080037@@ -759,10 +762,6 @@ static bool mtk_spi_mem_supports_op(struct spi_mem *mem,
developere451caf2021-05-11 21:57:51 +080038 return false;
39 }
40
41- if (op->data.dir == SPI_MEM_DATA_IN &&
42- !IS_ALIGNED((size_t)op->data.buf.in, 4))
43- return false;
44-
45 return true;
46 }
47
developer5d148cb2023-06-02 13:08:11 +080048@@ -821,6 +820,7 @@ static int mtk_spi_mem_exec_op(struct spi_mem *mem,
developere451caf2021-05-11 21:57:51 +080049 struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
50 u32 reg_val, nio = 1, tx_size;
51 char *tx_tmp_buf;
52+ char *rx_tmp_buf;
53 int ret = 0;
54
55 mdata->use_spimem = true;
developer5d148cb2023-06-02 13:08:11 +080056@@ -915,10 +915,18 @@ static int mtk_spi_mem_exec_op(struct spi_mem *mem,
developere451caf2021-05-11 21:57:51 +080057 }
58
59 if (op->data.dir == SPI_MEM_DATA_IN) {
60+ if(!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
61+ rx_tmp_buf = kzalloc(op->data.nbytes, GFP_KERNEL | GFP_DMA);
62+ if (!rx_tmp_buf)
63+ return -ENOMEM;
64+ }
65+ else
66+ rx_tmp_buf = op->data.buf.in;
67+
68 mdata->rx_dma = dma_map_single(mdata->dev,
69- op->data.buf.in,
70- op->data.nbytes,
71- DMA_FROM_DEVICE);
72+ rx_tmp_buf,
73+ op->data.nbytes,
74+ DMA_FROM_DEVICE);
75 if (dma_mapping_error(mdata->dev, mdata->rx_dma)) {
76 ret = -ENOMEM;
77 goto unmap_tx_dma;
developer5d148cb2023-06-02 13:08:11 +080078@@ -948,9 +956,14 @@ static int mtk_spi_mem_exec_op(struct spi_mem *mem,
developere451caf2021-05-11 21:57:51 +080079 writel(reg_val, mdata->base + SPI_CMD_REG);
80
81 unmap_rx_dma:
82- if (op->data.dir == SPI_MEM_DATA_IN)
83+ if (op->data.dir == SPI_MEM_DATA_IN) {
84+ if(!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
85+ memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
86+ kfree(rx_tmp_buf);
87+ }
88 dma_unmap_single(mdata->dev, mdata->rx_dma,
89 op->data.nbytes, DMA_FROM_DEVICE);
90+ }
91 unmap_tx_dma:
92 dma_unmap_single(mdata->dev, mdata->tx_dma,
93 tx_size, DMA_TO_DEVICE);
developer5d148cb2023-06-02 13:08:11 +080094--
952.34.1
96