blob: a662dc38c99dee2a34ba551cc94d7d0cbfbf3652 [file] [log] [blame]
developer75e4dad2022-11-16 15:17:14 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2022 MediaTek Inc. */
3
4#ifndef MTK_IPSEC_H
5#define MTK_IPSEC_H
6
7#define CTRL_WORD0_OUT 0x196b1006
8#define CTRL_WORD1_OUT 0x51400001
9#define CTRL_WORD0_IN 0x096ba20f
10#define CTRL_WORD1_IN 0x00010001
developer141ccec2023-02-16 09:51:22 +080011#define CTRL_WORD0_OUT_SHA256 0x19eb1606
12#define CTRL_WORD1_OUT_SHA256 0x57400001
13#define CTRL_WORD0_IN_SHA256 0x09eba20f
14#define CTRL_WORD1_IN_SHA256 0x00010001
developer75e4dad2022-11-16 15:17:14 +080015#define SIZE_IN_WORDS(x) ((x) >> 2)
16
17/* Global memory */
18#define MTK_GLO_MEM_CFG 0x600
19#define MTK_GLO_MEM_CTRL 0x604
20#define MTK_GLO_MEM_DATA0 0x608
21#define MTK_GLO_MEM_DATA1 0x60c
22#define MTK_GLO_MEM_DATA2 0x610
23#define MTK_GLO_MEM_DATA3 0x614
24#define MTK_GLO_MEM_DATA4 0x618
25#define MTK_GLO_MEM_DATA5 0x61c
26#define MTK_GLO_MEM_DATA6 0x620
27#define MTK_GLO_MEM_DATA7 0x624
28#define MTK_GLO_MEM_DATA8 0x628
29#define MTK_GLO_MEM_DATA9 0x62c
30
31/* GLO MEM CTRL */
32#define CTRL_CMD(x) ((x) << 30)
33#define CTRL_CMD_SFT 30
34#define CTRL_CMD_MASK GENMASK(31, 30)
35#define CTRL_INDEX(x) ((x) << 20)
36#define CTRL_INDEX_SFT 20
37#define CTRL_INDEX_MASK GENMASK(29, 20)
38#define CTRL_ADDR(x) ((x) << 0)
39#define CTRL_ADDR_SFT 0
40#define CTRL_ADDR_MASK GENMASK(19, 0)
41
42/* CDR Word0 */
43#define TYPE(x) ((x) << 30)
44#define TYPE_SFT 30
45#define TYPE_MASK GENMASK(31, 30)
46#define ENCLASTDEST BIT(25)
47#define ENCLASTDEST_MASK BIT(25)
48
49/* CDR Word1 */
50#define TOKEN_LEN(x) ((x) << 16)
51#define TOKEN_LEN_SFT 16
52#define TOKEN_LEN_MASK GENMASK(23, 16)
53#define APP_ID(x) ((x) << 9)
54#define APP_ID_SFT 9
55#define APP_ID_MASK GENMASK(15, 9)
56#define ADD_LEN(x) ((x) << 0)
57#define ADD_LEN_SFT 0
58#define ADD_LEN_MASK GENMASK(7, 0)
59
60/* CDR Word4 */
61#define FLOW_LOOKUP BIT(31)
62#define FLOW_LOOKUP_MASK BIT(31)
63#define HW_SER(x) ((x) << 24)
64#define HW_SER_SFT 24
65#define HW_SER_MASK GENMASK(29, 24)
66#define ALLOW_PAD BIT(23)
67#define ALLOW_PAD_MASK BIT(23)
68#define STRIP_PAD BIT(22)
69#define STRIP_PAD_MASK BIT(22)
70#define USER_DEF(x) ((x) << 0)
71#define USER_DEF_SFT 0
72#define USER_DEF_MASK GENMASK(15, 0)
73
74/* CDR Word5 */
75#define KEEP_OUTER BIT(28)
76#define KEEP_OUTER_MASK BIT(28)
77#define PARSE_ETH BIT(27)
78#define PARSE_ETH_MASK BIT(27)
79#define L4CHECKSUM BIT(26)
80#define L4CHECKSUM_MASK BIT(26)
81#define IPV4CHECKSUM BIT(25)
82#define IPV4CHECKSUM_MASK BIT(25)
83#define FL BIT(24)
84#define FL_MASK BIT(24)
85#define NEXT_HEADER(x) ((x) << 16)
86#define NEXT_HEADER_SFT 16
87#define NEXT_HEADER_MASK GENMASK(23, 16)
88
89#define HASH_CACHE_SIZE SHA512_BLOCK_SIZE
90
91struct ahash_export_state {
92 u64 len;
93 u64 processed;
94
95 u32 digest;
96
97 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
98 u8 cache[HASH_CACHE_SIZE];
99};
100
101/* Context Control */
102struct context_record {
103 __le32 control0;
104 __le32 control1;
105
106 __le32 data[62];
107};
108
109void mtk_ipsec_offload_init(struct mtk_eth *eth);
110#endif /* MTK_IPSEC_H */