developer | bc62736 | 2023-08-08 16:05:33 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Copyright (c) 2023 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TOPS_HPDMA_H_ |
| 9 | #define _TOPS_HPDMA_H_ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | #include <linux/bitfield.h> |
| 13 | |
| 14 | /* AXI DMA */ |
| 15 | #define TOPS_HPDMA_X_SRC(x) (0x100 * (x) + 0x0000) |
| 16 | #define TOPS_HPDMA_X_DST(x) (0x100 * (x) + 0x0004) |
| 17 | #define TOPS_HPDMA_X_NUM(x) (0x100 * (x) + 0x0008) |
| 18 | #define TOPS_HPDMA_X_CTRL(x) (0x100 * (x) + 0x000C) |
| 19 | #define TOPS_HPDMA_X_CLRIRQ(x) (0x100 * (x) + 0x0010) |
| 20 | #define TOPS_HPDMA_X_START(x) (0x100 * (x) + 0x0014) |
| 21 | #define TOPS_HPDMA_X_RRESP(x) (0x100 * (x) + 0x0018) |
| 22 | #define TOPS_HPDMA_X_BRESP(x) (0x100 * (x) + 0x001C) |
| 23 | #define TOPS_HPDMA_X_HW(x) (0x100 * (x) + 0x0020) |
| 24 | #define TOPS_HPDMA_X_ERR(x) (0x100 * (x) + 0x0024) |
| 25 | |
| 26 | |
| 27 | /* AXI DMA NUM */ |
| 28 | #define HPDMA_TOTALNUM_SHIFT (0) |
| 29 | #define HPDMA_TOTALNUM_MASK GENMASK(15, 0) |
| 30 | |
| 31 | /* AXI DMA CTRL */ |
| 32 | #define HPDMA_AXLEN_SHIFT (0) |
| 33 | #define HPDMA_AXLEN_MASK GENMASK(3, 0) |
| 34 | #define HPDMA_AXSIZE_SHIFT (8) |
| 35 | #define HPDMA_AXSIZE_MASK GENMASK(10, 8) |
| 36 | #define HPDMA_IRQEN BIT(16) |
| 37 | #define HPDMA_AWMODE_EN BIT(24) |
| 38 | #define HPDMA_OUTSTD_SHIFT (25) |
| 39 | #define HPDMA_OUTSTD_MASK GENMASK(29, 25) |
| 40 | |
| 41 | /* AXI DMA START */ |
| 42 | #define HPDMA_STATUS_SHIFT (0) |
| 43 | #define HPDMA_STATUS_MASK GENMASK(0, 0) |
| 44 | #define HPDMA_SKIP_RACE_SHIFT (7) |
| 45 | #define HPDMA_SKIP_RACE_MASK GENMASK(7, 7) |
| 46 | #define HPDMA_START BIT(15) |
| 47 | |
| 48 | /* AXI DMA RRESP */ |
| 49 | #define HPDMA_LOG_SHIFT (0) |
| 50 | #define HPDMA_LOG_MASK GENMASK(15, 0) |
| 51 | #define HPDMA_RESP_SHIFT (16) |
| 52 | #define HPDMA_RESP_MASK GENMASK(17, 16) |
| 53 | |
| 54 | /* AXI DMA HW */ |
| 55 | #define HPDMA_FIFO_DEPTH_SHIFT (0) |
| 56 | #define HPDMA_FIFO_DEPTH_MASK GENMASK(7, 0) |
| 57 | #define HPDMA_MAX_AXSIZE_SHIFT (8) |
| 58 | #define HPDMA_MAX_AXSIZE_MASK GENMASK(15, 8) |
| 59 | |
| 60 | enum hpdma_err { |
| 61 | AWMODE_ERR = 0x1 << 0, |
| 62 | AXSIZE_ERR = 0x1 << 1, |
| 63 | ARADDR_ERR = 0x1 << 2, |
| 64 | AWADDR_ERR = 0x1 << 3, |
| 65 | RACE_ERR = 0x1 << 4, |
| 66 | }; |
| 67 | |
| 68 | enum top_hpdma_req { |
| 69 | TOP_HPDMA_TNL_SYNC_REQ, |
| 70 | |
| 71 | __TOP_HPDMA_REQ, |
| 72 | }; |
| 73 | |
| 74 | enum clust_hpdma_req { |
| 75 | CLUST_HPDMA_DUMMY_REQ, |
| 76 | |
| 77 | __CLUST_HPDMA_REQ, |
| 78 | }; |
| 79 | |
| 80 | int mtk_tops_hpdma_init(void); |
| 81 | void mtk_tops_hpdma_exit(void); |
| 82 | #endif /* _TOPS_HPDMA_H_ */ |