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developereb6a0182022-12-12 18:53:32 +08001From 0431d98e1a656f59c4fab110897e7e9bc092cc5a Mon Sep 17 00:00:00 2001
developer1f23e2f2022-12-05 10:14:25 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Fri, 2 Dec 2022 17:17:06 +0800
developereb6a0182022-12-12 18:53:32 +08004Subject: [PATCH 3011/3011] mt76: mt7915: wed: add mt7916 2 pcie support when
5 wed on
developer1f23e2f2022-12-05 10:14:25 +08006
7It should use bit 23 in interrupt mask for wfdma band1 data
8for 2 pcie mt7916, and use bit 19 for band1 data for 1 pcie.
9
10Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
11---
12 mt7915/dma.c | 8 ++++++--
13 mt7915/mcu.c | 2 +-
14 mt7915/mmio.c | 10 +++++-----
15 3 files changed, 12 insertions(+), 8 deletions(-)
16
17diff --git a/mt7915/dma.c b/mt7915/dma.c
developereb6a0182022-12-12 18:53:32 +080018index 1ae6c339..36260085 100644
developer1f23e2f2022-12-05 10:14:25 +080019--- a/mt7915/dma.c
20+++ b/mt7915/dma.c
developereb6a0182022-12-12 18:53:32 +080021@@ -88,8 +88,12 @@ static void mt7915_dma_config(struct mt7915_dev *dev)
developer1f23e2f2022-12-05 10:14:25 +080022 MT7916_RXQ_BAND0);
23 RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MT7916,
24 MT7916_RXQ_MCU_WA);
25- RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916,
26- MT7916_RXQ_BAND1);
27+ if (dev->hif2)
28+ RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916,
29+ MT7916_RXQ_BAND1);
30+ else
31+ RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916,
32+ MT7916_RXQ_BAND1);
33 RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MAIN_MT7916,
34 MT7916_RXQ_MCU_WA_MAIN);
35 TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0,
36diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developereb6a0182022-12-12 18:53:32 +080037index ff207f70..737a714f 100644
developer1f23e2f2022-12-05 10:14:25 +080038--- a/mt7915/mcu.c
39+++ b/mt7915/mcu.c
developereb6a0182022-12-12 18:53:32 +080040@@ -2352,7 +2352,7 @@ int mt7915_mcu_init_firmware(struct mt7915_dev *dev)
developer1f23e2f2022-12-05 10:14:25 +080041 return ret;
42
43 if (mtk_wed_device_active(wed)) {
44- if (is_mt7915(&dev->mt76))
45+ if (is_mt7915(&dev->mt76) || !mtk_wed_get_rx_capa(wed))
46 mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY),
47 0, 0, 0);
48 else
49diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developereb6a0182022-12-12 18:53:32 +080050index 6fb3419d..e30a8d4c 100644
developer1f23e2f2022-12-05 10:14:25 +080051--- a/mt7915/mmio.c
52+++ b/mt7915/mmio.c
developereb6a0182022-12-12 18:53:32 +080053@@ -964,13 +964,13 @@ irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
developer1f23e2f2022-12-05 10:14:25 +080054 struct mt7915_dev *dev = dev_instance;
55 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
56
57- if (mtk_wed_device_active(wed)) {
58+ if (mtk_wed_device_active(wed))
59 mtk_wed_device_irq_set_mask(wed, 0);
60- } else {
61+ else
62 mt76_wr(dev, MT_INT_MASK_CSR, 0);
63- if (dev->hif2)
64- mt76_wr(dev, MT_INT1_MASK_CSR, 0);
65- }
66+
67+ if (dev->hif2)
68+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
69
70 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
71 return IRQ_NONE;
72--
developereb6a0182022-12-12 18:53:32 +0800732.25.1
developer1f23e2f2022-12-05 10:14:25 +080074