blob: f8a85662d8900bb72e7b9f5951f073dc054afee5 [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
5 compatible = "mediatek,mt7981-emmc-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000 \
developer4bd45c72023-03-15 17:20:06 +08009 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
developer24455dd2021-10-28 10:55:41 +080010 };
11
12 memory {
13 // fpga ddr2: 128MB*2
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_3p3v: regulator-3p3v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-3.3V";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
25};
26
27&uart0 {
28 status = "okay";
29};
30
31&watchdog {
32 status = "okay";
33};
34
35&mmc0 {
36 pinctrl-names = "default", "state_uhs";
37 pinctrl-0 = <&mmc0_pins_default>;
38 pinctrl-1 = <&mmc0_pins_uhs>;
39 bus-width = <8>;
40 max-frequency = <52000000>;
41 cap-mmc-highspeed;
42 vmmc-supply = <&reg_3p3v>;
43 non-removable;
44 status = "okay";
45};
46
47&eth {
48 status = "okay";
49
50 gmac0: mac@0 {
51 compatible = "mediatek,eth-mac";
52 reg = <0>;
53 phy-mode = "2500base-x";
54
55 fixed-link {
56 speed = <2500>;
57 full-duplex;
58 pause;
59 };
60 };
61
62 gmac1: mac@1 {
63 compatible = "mediatek,eth-mac";
64 reg = <1>;
65 phy-mode = "gmii";
66 phy-handle = <&phy0>;
67 };
68
69 mdio: mdio-bus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 phy0: ethernet-phy@0 {
developera7de8be2021-11-15 21:14:31 +080074 compatible = "ethernet-phy-id03a2.9461";
developer24455dd2021-10-28 10:55:41 +080075 reg = <0>;
developera7de8be2021-11-15 21:14:31 +080076 phy-mode = "gmii";
developera7de8be2021-11-15 21:14:31 +080077 nvmem-cells = <&phy_calibration>;
78 nvmem-cell-names = "phy-cal-data";
developer24455dd2021-10-28 10:55:41 +080079 };
80
81 switch@0 {
82 compatible = "mediatek,mt7531";
83 reg = <31>;
84 reset-gpios = <&pio 39 0>;
85
86 ports {
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 port@0 {
91 reg = <0>;
92 label = "lan1";
93 };
94
95 port@1 {
96 reg = <1>;
97 label = "lan2";
98 };
99
100 port@2 {
101 reg = <2>;
102 label = "lan3";
103 };
104
105 port@3 {
106 reg = <3>;
107 label = "lan4";
108 };
109
110 port@6 {
111 reg = <6>;
112 label = "cpu";
113 ethernet = <&gmac0>;
114 phy-mode = "2500base-x";
115
116 fixed-link {
117 speed = <2500>;
118 full-duplex;
119 pause;
120 };
121 };
122 };
123 };
124 };
125};
126
127&hnat {
128 mtketh-wan = "eth1";
129 mtketh-lan = "lan";
130 mtketh-max-gmac = <2>;
131 status = "okay";
132};
133
134&spi1 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&spic_pins>;
137 status = "disabled";
138};
139
140&pio {
141
142 spic_pins: spi1-pins {
143 mux {
144 function = "spi";
145 groups = "spi1_1";
146 };
147 };
148
149 mmc0_pins_default: mmc0-pins-default {
150 mux {
151 function = "flash";
152 groups = "emmc_45";
153 };
154 };
155
156 mmc0_pins_uhs: mmc0-pins-uhs {
157 mux {
158 function = "flash";
159 groups = "emmc_45";
160 };
161 };
162};
163
164&xhci {
165 mediatek,u3p-dis-msk = <0x0>;
166 phys = <&u2port0 PHY_TYPE_USB2>,
167 <&u3port0 PHY_TYPE_USB3>;
168 status = "okay";
169};