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developer0f312e82022-11-01 12:31:52 +08001/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6#ifndef __MT7996_REGS_H
7#define __MT7996_REGS_H
8
9struct __map {
10 u32 phys;
11 u32 mapped;
12 u32 size;
13};
14
15struct __base {
16 u32 band_base[__MT_MAX_BAND];
17};
18
19/* used to differentiate between generations */
20struct mt7996_reg_desc {
21 const struct __base *base;
22 const struct __map *map;
23 u32 map_size;
24};
25
26enum base_rev {
27 WF_AGG_BASE,
28 WF_MIB_BASE,
29 WF_TMAC_BASE,
30 WF_RMAC_BASE,
31 WF_ARB_BASE,
32 WF_LPON_BASE,
33 WF_ETBF_BASE,
34 WF_DMA_BASE,
35 __MT_REG_BASE_MAX,
36};
37
38#define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)])
39
40#define MT_MCU_INT_EVENT 0x2108
41#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
42#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
43#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
44
45/* PLE */
46#define MT_PLE_BASE 0x820c0000
47#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
48
49#define MT_FL_Q_EMPTY MT_PLE(0x360)
50#define MT_FL_Q0_CTRL MT_PLE(0x3e0)
51#define MT_FL_Q2_CTRL MT_PLE(0x3e8)
52#define MT_FL_Q3_CTRL MT_PLE(0x3ec)
53
54#define MT_PLE_FREEPG_CNT MT_PLE(0x380)
55#define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384)
56#define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c)
57#define MT_PLE_HIF_PG_INFO MT_PLE(0x388)
58
59#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2))
60#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
61
62/* WF MDP TOP */
63#define MT_MDP_BASE 0x820cc000
64#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
65
66#define MT_MDP_DCR2 MT_MDP(0x8e8)
67#define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2)
68
69/* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */
70#define MT_WF_TMAC_BASE(_band) __BASE(WF_TMAC_BASE, (_band))
71#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
72
73#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
74#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
75
76#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8)
77#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc)
78#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
79#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
80
81#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014)
82#define MT_IFS_EIFS_OFDM GENMASK(8, 0)
83#define MT_IFS_RIFS GENMASK(14, 10)
84#define MT_IFS_SIFS GENMASK(22, 16)
85#define MT_IFS_SLOT GENMASK(30, 24)
86
87#define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018)
88#define MT_IFS_EIFS_CCK GENMASK(8, 0)
89
90/* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */
91#define MT_WF_DMA_BASE(_band) __BASE(WF_DMA_BASE, (_band))
92#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
93
94#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
95#define MT_DMA_DCR0_RXD_G5_EN BIT(23)
96
97#define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054)
98#define MT_DMA_TCRF1_QIDX GENMASK(15, 13)
99
100/* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */
101#define MT_WF_ETBF_BASE(_band) __BASE(WF_ETBF_BASE, (_band))
102#define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs))
103
104#define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100)
105#define MT_ETBF_RX_FB_BW GENMASK(10, 8)
106#define MT_ETBF_RX_FB_NC GENMASK(7, 4)
107#define MT_ETBF_RX_FB_NR GENMASK(3, 0)
108
109/* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */
110#define MT_WF_LPON_BASE(_band) __BASE(WF_LPON_BASE, (_band))
111#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
112
113#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360)
114#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364)
115#define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c)
116
117#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4))
118#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
119#define MT_LPON_TCR_SW_WRITE BIT(0)
120#define MT_LPON_TCR_SW_ADJUST BIT(1)
121#define MT_LPON_TCR_SW_READ GENMASK(1, 0)
122
123/* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/
124/* These counters are (mostly?) clear-on-read. So, some should not
125 * be read at all in case firmware is already reading them. These
126 * are commented with 'DNR' below. The DNR stats will be read by querying
127 * the firmware API for the appropriate message. For counters the driver
128 * does read, the driver should accumulate the counters.
129 */
130#define MT_WF_MIB_BASE(_band) __BASE(WF_MIB_BASE, (_band))
131#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
132
133#define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, 0x9cc)
134#define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, 0x9d0)
135#define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, 0x9d4)
136#define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, 0x9d8)
137#define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, 0x9dc)
138#define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, 0x9e0)
139#define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, 0x9e4)
140#define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, 0x9e8)
141#define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, 0xa10)
142
143#define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4)
144#define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8)
145#define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0)
146
147#define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, 0x7ac)
148/* rx mpdu counter, full 32 bits */
149#define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, 0x964)
150#define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, 0x96c)
151
152#define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
153#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
154
155#define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, 0x720)
156
157#define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, 0x974)
158#define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, 0x978)
159
160/* tx ampdu cnt, full 32 bits */
161#define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0)
162#define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8)
163
164/* counts all mpdus in ampdu, regardless of success */
165#define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc)
166
167/* counts all successfully tx'd mpdus in ampdu */
168#define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0)
169
170/* rx ampdu count, 32-bit */
171#define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, 0x954)
172
173/* rx ampdu bytes count, 32-bit */
174#define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, 0x958)
175
176/* rx ampdu valid subframe count */
177#define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, 0x95c)
178
179/* rx ampdu valid subframe bytes count, 32bits */
180#define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, 0x960)
181
182/* remaining windows protected stats */
183#define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080)
184#define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0)
185
186#define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084)
187#define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0)
188
189#define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, 0x724)
190
191/* rx blockack count, 32 bits */
192#define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4)
193
194#define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0)
195#define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, 0x788)
196#define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, 0x798)
197
198#define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0)
199
200#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa28 + ((n) << 2))
201#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
202#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0))
203
204/* UMIB */
205#define MT_WF_UMIB_BASE 0x820cd000
206#define MT_WF_UMIB(ofs) (MT_WF_UMIB_BASE + (ofs))
207
208#define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + _band * 0x164)
209
210/* WTBLON TOP */
211#define MT_WTBLON_TOP_BASE 0x820d4000
212#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
213#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370)
214#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
215
216#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380)
217#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)
218#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14)
219#define MT_WTBL_UPDATE_BUSY BIT(31)
220
221/* WTBL */
222#define MT_WTBL_BASE 0x820d8000
223#define MT_WTBL_LMAC_ID GENMASK(14, 8)
224#define MT_WTBL_LMAC_DW GENMASK(7, 2)
225#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
226 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
227 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
228
229/* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */
230#define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band))
231#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
232
233#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x054)
234#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
235
236/* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */
237#define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band))
238#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
239
240#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000)
241#define MT_ARB_SCR_TX_DISABLE BIT(8)
242#define MT_ARB_SCR_RX_DISABLE BIT(9)
243
244/* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */
245#define MT_WF_RMAC_BASE(_band) __BASE(WF_RMAC_BASE, (_band))
246#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
247
248#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
249#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
250#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
251#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
252#define MT_WF_RFCR_DROP_MCAST BIT(5)
253#define MT_WF_RFCR_DROP_BCAST BIT(6)
254#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
255#define MT_WF_RFCR_DROP_A3_MAC BIT(8)
256#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
257#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
258#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
259#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
260#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
261#define MT_WF_RFCR_DROP_CTS BIT(14)
262#define MT_WF_RFCR_DROP_RTS BIT(15)
263#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
264#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
265#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
266#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
267#define MT_WF_RFCR_DROP_NDPA BIT(20)
268#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
269
270#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
271#define MT_WF_RFCR1_DROP_ACK BIT(4)
272#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
273#define MT_WF_RFCR1_DROP_BA BIT(6)
274#define MT_WF_RFCR1_DROP_CFEND BIT(7)
275#define MT_WF_RFCR1_DROP_CFACK BIT(8)
276
277#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
278#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
279#define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16)
280#define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0)
281
282#define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384)
283#define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16)
284
285#define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c)
286#define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0)
287
288#define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390)
289#define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0)
290
291#define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0)
292#define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21)
293
294/* WFDMA0 */
295#define MT_WFDMA0_BASE 0xd4000
296#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
297
298#define MT_WFDMA0_RST MT_WFDMA0(0x100)
299#define MT_WFDMA0_RST_LOGIC_RST BIT(4)
300#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
301
302#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
303#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
304#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
305#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
306
307#define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154)
308#define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3)
309
310#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
311#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
312#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
313#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
314#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
315#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
316
317#define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
318#define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18)
319#define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14)
320
321#define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)
322#define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE BIT(31)
323#define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE BIT(28)
324
325#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
326#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
327#define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
328#define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
329
330/* WFDMA1 */
331#define MT_WFDMA1_BASE 0xd5000
332
333/* WFDMA CSR */
334#define MT_WFDMA_EXT_CSR_BASE 0xd7000
335#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
336
337#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)
338#define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
339
340#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
341#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
342
343#define MT_PCIE_RECOG_ID 0xd7090
344#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
345#define MT_PCIE_RECOG_ID_SEM BIT(31)
346
347/* WFDMA0 PCIE1 */
348#define MT_WFDMA0_PCIE1_BASE 0xd8000
349#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
350
351#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
352#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
353#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
354#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
355
356/* WFDMA COMMON */
357#define __RXQ(q) ((q) + __MT_MCUQ_MAX)
358#define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX)
359
360#define MT_Q_ID(q) (dev->q_id[(q)])
361#define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \
362 MT_WFDMA1_BASE : MT_WFDMA0_BASE)
363
364#define MT_MCUQ_ID(q) MT_Q_ID(q)
365#define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q))
366#define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q))
367
368#define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300)
369#define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300)
370#define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500)
371
372#define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \
373 MT_MCUQ_ID(q)* 0x4)
374#define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
375 MT_RXQ_ID(q)* 0x4)
376#define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
377 MT_TXQ_ID(q)* 0x4)
378
379#define MT_INT_SOURCE_CSR MT_WFDMA0(0x200)
380#define MT_INT_MASK_CSR MT_WFDMA0(0x204)
381
382#define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200)
383#define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204)
384
385#define MT_INT_RX_DONE_BAND0 BIT(12)
386#define MT_INT_RX_DONE_BAND1 BIT(12)
387#define MT_INT_RX_DONE_BAND2 BIT(13)
388#define MT_INT_RX_DONE_WM BIT(0)
389#define MT_INT_RX_DONE_WA BIT(1)
390#define MT_INT_RX_DONE_WA_MAIN BIT(2)
391#define MT_INT_RX_DONE_WA_EXT BIT(2)
392#define MT_INT_RX_DONE_WA_TRI BIT(3)
393#define MT_INT_RX_TXFREE_MAIN BIT(17)
394#define MT_INT_RX_TXFREE_TRI BIT(15)
395#define MT_INT_MCU_CMD BIT(29)
396
397#define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)])
398#define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)])
399
400#define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \
401 MT_INT_RX(MT_RXQ_MCU_WA))
402
403#define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \
404 MT_INT_RX(MT_RXQ_MAIN_WA))
405
406#define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \
407 MT_INT_RX(MT_RXQ_BAND1_WA) | \
408 MT_INT_RX(MT_RXQ_MAIN_WA))
409
410#define MT_INT_BAND2_RX_DONE (MT_INT_RX(MT_RXQ_BAND2) | \
411 MT_INT_RX(MT_RXQ_BAND2_WA) | \
412 MT_INT_RX(MT_RXQ_MAIN_WA))
413
414#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \
415 MT_INT_BAND0_RX_DONE | \
416 MT_INT_BAND1_RX_DONE | \
417 MT_INT_BAND2_RX_DONE)
418
419#define MT_INT_TX_DONE_FWDL BIT(26)
420#define MT_INT_TX_DONE_MCU_WM BIT(27)
421#define MT_INT_TX_DONE_MCU_WA BIT(22)
422#define MT_INT_TX_DONE_BAND0 BIT(30)
423#define MT_INT_TX_DONE_BAND1 BIT(31)
424#define MT_INT_TX_DONE_BAND2 BIT(15)
425
426#define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \
427 MT_INT_TX_MCU(MT_MCUQ_WM) | \
428 MT_INT_TX_MCU(MT_MCUQ_FWDL))
429
430#define MT_MCU_CMD MT_WFDMA0(0x1f0)
431#define MT_MCU_CMD_STOP_DMA BIT(2)
432#define MT_MCU_CMD_RESET_DONE BIT(3)
433#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
434#define MT_MCU_CMD_NORMAL_STATE BIT(5)
435#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
436
437/* l1/l2 remap */
438#define MT_HIF_REMAP_L1 0x155024
439#define MT_HIF_REMAP_L1_MASK GENMASK(31, 16)
440#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
441#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
442#define MT_HIF_REMAP_BASE_L1 0x130000
443
444#define MT_HIF_REMAP_L2 0x1b4
445#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
446#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
447#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
448#define MT_HIF_REMAP_BASE_L2 0x1000
449
450#define MT_INFRA_BASE 0x18000000
451#define MT_WFSYS0_PHY_START 0x18400000
452#define MT_WFSYS1_PHY_START 0x18800000
453#define MT_WFSYS1_PHY_END 0x18bfffff
454#define MT_CBTOP1_PHY_START 0x70000000
455#define MT_CBTOP1_PHY_END 0x77ffffff
456#define MT_CBTOP2_PHY_START 0xf0000000
457#define MT_CBTOP2_PHY_END 0xffffffff
458#define MT_INFRA_MCU_START 0x7c000000
459#define MT_INFRA_MCU_END 0x7c3fffff
460
461/* FW MODE SYNC */
462#define MT_SWDEF_MODE 0x9143c
463#define MT_SWDEF_NORMAL_MODE 0
464
465/* LED */
466#define MT_LED_TOP_BASE 0x18013000
467#define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n))
468
469#define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4))
470#define MT_LED_CTRL_KICK BIT(7)
471#define MT_LED_CTRL_BLINK_MODE BIT(2)
472#define MT_LED_CTRL_POLARITY BIT(1)
473
474#define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4))
475#define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)
476#define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8)
477
478#define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))
479
480#define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */
481#define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */
482#define MT_LED_GPIO_SEL_MASK GENMASK(11, 8)
483
484/* MT TOP */
485#define MT_TOP_BASE 0xe0000
486#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
487
488#define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))
489#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
490#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
491#define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2)
492
493#define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))
494#define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
495
496#define MT_TOP_MISC MT_TOP(0xf0)
497#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
498
499#define MT_HW_REV 0x70010204
500#define MT_WF_SUBSYS_RST 0x70002600
501
502/* PCIE MAC */
503#define MT_PCIE_MAC_BASE 0x74030000
504#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
505#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
506
507#define MT_PCIE1_MAC_BASE 0x74090000
508#define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs))
509
510#define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)
511
512/* PHYRX CTRL */
513#define MT_WF_PHYRX_BAND_BASE 0x83080000
514#define MT_WF_PHYRX_BAND(_band, ofs) (MT_WF_PHYRX_BAND_BASE + \
515 ((_band) << 20) + (ofs))
516
517#define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004)
518#define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0)
519#define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN GENMASK(11, 9)
520
521/* PHYRX CSD */
522#define MT_WF_PHYRX_CSD_BASE 0x83000000
523#define MT_WF_PHYRX_CSD(_band, _wf, ofs) (MT_WF_PHYRX_CSD_BASE + \
524 ((_band) << 20) + \
525 ((_wf) << 16) + (ofs))
526#define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000)
527
528/* PHYRX CSD BAND */
529#define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230)
530#define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
531#define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR BIT(29)
532
533#endif