blob: 8b398d5773693d682ed6941be603a765021ae57e [file] [log] [blame]
developer0f312e82022-11-01 12:31:52 +08001// SPDX-License-Identifier: ISC
2/* Copyright (C) 2022 MediaTek Inc. */
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/platform_device.h>
7#include <linux/of.h>
8#include <linux/of_device.h>
9#include <linux/of_reserved_mem.h>
10#include <linux/of_gpio.h>
11#include <linux/iopoll.h>
12#include <linux/reset.h>
13#include <linux/of_net.h>
14#include <linux/clk.h>
15
16#include "mt7915.h"
17
18/* INFRACFG */
19#define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0
20#define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4
21
22#define MT_INFRACFG_RX_EN_MASK BIT(16)
23#define MT_INFRACFG_TX_RDY_MASK BIT(4)
24#define MT_INFRACFG_TX_EN_MASK BIT(0)
25
26/* TOP POS */
27#define MT_TOP_POS_FAST_CTRL 0x114
28#define MT_TOP_POS_FAST_EN_MASK BIT(3)
29
30#define MT_TOP_POS_SKU 0x21c
31#define MT_TOP_POS_SKU_MASK GENMASK(31, 28)
32#define MT_TOP_POS_SKU_ADIE_DBDC_MASK BIT(2)
33
34enum {
35 ADIE_SB,
36 ADIE_DBDC
37};
38
39static int
40mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val)
41{
42 int ret;
43 u32 cur;
44
45 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
46 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
47 dev, MT_TOP_SPI_BUSY_CR(adie));
48 if (ret)
49 return ret;
50
51 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
52 MT_TOP_SPI_READ_ADDR_FORMAT | addr);
53 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0);
54
55 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
56 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
57 dev, MT_TOP_SPI_BUSY_CR(adie));
58 if (ret)
59 return ret;
60
61 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie));
62
63 return 0;
64}
65
66static int
67mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val)
68{
69 int ret;
70 u32 cur;
71
72 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
73 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
74 dev, MT_TOP_SPI_BUSY_CR(adie));
75 if (ret)
76 return ret;
77
78 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
79 MT_TOP_SPI_WRITE_ADDR_FORMAT | addr);
80 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val);
81
82 return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
83 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
84 dev, MT_TOP_SPI_BUSY_CR(adie));
85}
86
87static int
88mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie,
89 u32 addr, u32 mask, u32 val)
90{
91 u32 cur, ret;
92
93 ret = mt76_wmac_spi_read(dev, adie, addr, &cur);
94 if (ret)
95 return ret;
96
97 cur &= ~mask;
98 cur |= val;
99
100 return mt76_wmac_spi_write(dev, adie, addr, cur);
101}
102
103static int
104mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie,
105 u32 addr, u32 *data)
106{
107 int ret, temp;
108 u32 val, mask;
109
110 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG,
111 MT_ADIE_EFUSE_CTRL_MASK);
112 if (ret)
113 return ret;
114
115 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0);
116 if (ret)
117 return ret;
118
119 mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK |
120 MT_ADIE_EFUSE_KICK_MASK);
121 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) |
122 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) |
123 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1);
124 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val);
125 if (ret)
126 return ret;
127
128 ret = read_poll_timeout(mt76_wmac_spi_read, temp,
129 !temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val),
130 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
131 dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
132 if (ret)
133 return ret;
134
135 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
136 if (ret)
137 return ret;
138
139 if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1)
140 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0,
141 data);
142
143 return ret;
144}
145
146static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev)
147{
148 u32 cur;
149
150 read_poll_timeout(mt76_rr, cur,
151 FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur),
152 1000, 1000 * MSEC_PER_SEC, false, dev,
153 MT_SEMA_RFSPI_STATUS);
154}
155
156static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev)
157{
158 mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1);
159}
160
161static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
162{
163 val |= readl(base + offset) & ~mask;
164 writel(val, base + offset);
165
166 return val;
167}
168
169static u8 mt7986_wmac_check_adie_type(struct mt7915_dev *dev)
170{
171 u32 val;
172
173 val = readl(dev->sku + MT_TOP_POS_SKU);
174
175 return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val);
176}
177
178static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable)
179{
180 if (!enable)
181 return reset_control_assert(dev->rstc);
182
183 mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL,
184 MT_TOP_POS_FAST_EN_MASK,
185 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1));
186
187 return reset_control_deassert(dev->rstc);
188}
189
190static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev)
191{
192 struct pinctrl_state *state;
193 struct pinctrl *pinctrl;
194 int ret;
195 u8 type;
196
197 type = mt7986_wmac_check_adie_type(dev);
198 pinctrl = devm_pinctrl_get(dev->mt76.dev);
199 if (IS_ERR(pinctrl))
200 return PTR_ERR(pinctrl);
201
202 switch (type) {
203 case ADIE_SB:
204 state = pinctrl_lookup_state(pinctrl, "default");
205 if (IS_ERR_OR_NULL(state))
206 return -EINVAL;
207 break;
208 case ADIE_DBDC:
209 state = pinctrl_lookup_state(pinctrl, "dbdc");
210 if (IS_ERR_OR_NULL(state))
211 return -EINVAL;
212 break;
213 default:
214 return -EINVAL;
215 }
216
217 ret = pinctrl_select_state(pinctrl, state);
218 if (ret)
219 return ret;
220
221 usleep_range(500, 1000);
222
223 return 0;
224}
225
226static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable)
227{
228 int ret;
229 u32 cur;
230
231 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
232 MT_INFRACFG_RX_EN_MASK,
233 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
234 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK),
235 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
236 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
237 if (ret)
238 return ret;
239
240 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
241 MT_INFRACFG_TX_EN_MASK,
242 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
243 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK),
244 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
245 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
246 if (ret)
247 return ret;
248
249 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
250 MT_INFRACFG_RX_EN_MASK,
251 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
252 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
253 MT_INFRACFG_TX_EN_MASK,
254 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
255
256 return 0;
257}
258
259static int mt7986_wmac_coninfra_check(struct mt7915_dev *dev)
260{
261 u32 cur;
262
263 return read_poll_timeout(mt76_rr, cur, (cur == 0x02070000),
264 USEC_PER_MSEC, 50 * USEC_PER_MSEC,
265 false, dev, MT_CONN_INFRA_BASE);
266}
267
268static int mt7986_wmac_coninfra_setup(struct mt7915_dev *dev)
269{
270 struct device *pdev = dev->mt76.dev;
271 struct reserved_mem *rmem;
272 struct device_node *np;
273 u32 val;
274
275 np = of_parse_phandle(pdev->of_node, "memory-region", 0);
276 if (!np)
277 return -EINVAL;
278
279 rmem = of_reserved_mem_lookup(np);
280 if (!rmem)
281 return -EINVAL;
282
283 val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK;
284
285 /* Set conninfra subsys PLL check */
286 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
287 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
288 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
289 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
290
291 mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE,
292 MT_TOP_MCU_EMI_BASE_MASK, val);
293
294 mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base);
295 mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size);
296
297 mt76_rr(dev, MT_CONN_INFRA_EFUSE);
298
299 /* Set conninfra sysram */
300 mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0);
301 mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1);
302
303 return 0;
304}
305
306static int mt7986_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type)
307{
308 int ret;
309 u32 adie_main, adie_ext;
310
311 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
312 MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1);
313 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
314 MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1);
315
316 mt76_wmac_spi_lock(dev);
317
318 ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main);
319 if (ret)
320 goto out;
321
322 ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext);
323 if (ret)
324 goto out;
325
326 *adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) |
327 (MT_ADIE_CHIP_ID_MASK & adie_ext);
328
329out:
330 mt76_wmac_spi_unlock(dev);
331
332 return 0;
333}
334
335static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type)
336{
337 if (adie == 0)
338 return u32_get_bits(adie_type, MT_ADIE_IDX0);
339 else
340 return u32_get_bits(adie_type, MT_ADIE_IDX1);
341}
342
343static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type)
344{
345 return mt7986_adie_idx(adie, adie_type) == 0x7975;
346}
347
348static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type)
349{
350 return mt7986_adie_idx(adie, adie_type) == 0x7976;
351}
352
353static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie)
354{
355 int ret;
356 u32 data, val;
357
358 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG,
359 &data);
360 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
361 val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data);
362 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG,
363 MT_ADIE_VRPI_SEL_CR_MASK,
364 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val));
365 if (ret)
366 return ret;
367
368 val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data);
369 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
370 MT_ADIE_PGA_GAIN_MASK,
371 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val));
372 if (ret)
373 return ret;
374 }
375
376 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP,
377 &data);
378 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
379 val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data);
380
381 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
382 MT_ADIE_LDO_CTRL_MASK,
383 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val));
384 }
385
386 return 0;
387}
388
389static int
390mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie,
391 bool is_40m, int *result)
392{
393 int ret;
394 u32 data, addr;
395
396 addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC;
397 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
398 if (ret)
399 return ret;
400
401 if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) {
402 *result = 64;
403 } else {
404 *result = FIELD_GET(MT_ADIE_TRIM_MASK, data);
405 addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC :
406 MT_ADIE_XTAL_TRIM1_80M_OSC;
407 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
408 if (ret)
409 return ret;
410
411 if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) &&
412 FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data))
413 *result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
414 else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data))
415 *result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
416
417 *result = max(0, min(127, *result));
418 }
419
420 return 0;
421}
422
423static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie)
424{
425 int ret, trim_80m, trim_40m;
426 u32 data, val, mode;
427
428 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW,
429 &data);
430 if (ret || !FIELD_GET(BIT(1), data))
431 return 0;
432
433 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m);
434 if (ret)
435 return ret;
436
437 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m);
438 if (ret)
439 return ret;
440
441 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val);
442 if (ret)
443 return ret;
444
445 mode = FIELD_PREP(GENMASK(6, 4), val);
446 if (!mode || mode == 0x2) {
447 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
448 GENMASK(31, 24),
449 FIELD_PREP(GENMASK(31, 24), trim_80m));
450 if (ret)
451 return ret;
452
453 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
454 GENMASK(31, 24),
455 FIELD_PREP(GENMASK(31, 24), trim_80m));
456 } else if (mode == 0x3 || mode == 0x4 || mode == 0x6) {
457 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
458 GENMASK(23, 16),
459 FIELD_PREP(GENMASK(23, 16), trim_40m));
460 if (ret)
461 return ret;
462
463 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
464 GENMASK(23, 16),
465 FIELD_PREP(GENMASK(23, 16), trim_40m));
466 }
467
468 return ret;
469}
470
471static int mt7986_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie)
472{
473 u32 id, version, rg_xo_01, rg_xo_03;
474 int ret;
475
476 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_CHIP_ID, &id);
477 if (ret)
478 return ret;
479
480 version = FIELD_GET(MT_ADIE_VERSION_MASK, id);
481
482 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00);
483 if (ret)
484 return ret;
485
486 if (version == 0x8a00 || version == 0x8a10 || version == 0x8b00) {
487 rg_xo_01 = 0x1d59080f;
488 rg_xo_03 = 0x34c00fe0;
489 } else {
490 rg_xo_01 = 0x1959f80f;
491 rg_xo_03 = 0x34d00fe0;
492 }
493
494 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, rg_xo_01);
495 if (ret)
496 return ret;
497
498 return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, rg_xo_03);
499}
500
501static int
502mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie,
503 u32 addr, u32 *result)
504{
505 int ret;
506 u32 data;
507
508 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
509 if (ret)
510 return ret;
511
512 if ((data & MT_ADIE_XO_TRIM_EN_MASK)) {
513 if ((data & MT_ADIE_XTAL_DECREASE_MASK))
514 *result -= (data & MT_ADIE_EFUSE_TRIM_MASK);
515 else
516 *result += (data & MT_ADIE_EFUSE_TRIM_MASK);
517
518 *result = (*result & MT_ADIE_TRIM_MASK);
519 }
520
521 return 0;
522}
523
524static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie)
525{
526 int ret;
527 u32 data, result = 0, value;
528
529 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN,
530 &data);
531 if (ret || !(data & BIT(1)))
532 return 0;
533
534 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL,
535 &data);
536 if (ret)
537 return ret;
538
539 if (data & MT_ADIE_XO_TRIM_EN_MASK)
540 result = (data & MT_ADIE_TRIM_MASK);
541
542 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2,
543 &result);
544 if (ret)
545 return ret;
546
547 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3,
548 &result);
549 if (ret)
550 return ret;
551
552 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4,
553 &result);
554 if (ret)
555 return ret;
556
557 /* Update trim value to C1 and C2*/
558 value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) |
559 FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result);
560 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2,
561 MT_ADIE_7975_XO_CTRL2_MASK, value);
562 if (ret)
563 return ret;
564
565 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value);
566 if (ret)
567 return ret;
568
569 if (value & MT_ADIE_7975_XTAL_EN_MASK) {
570 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2,
571 MT_ADIE_7975_XO_2_FIX_EN, 0x0);
572 if (ret)
573 return ret;
574 }
575
576 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6,
577 MT_ADIE_7975_XO_CTRL6_MASK, 0x1);
578}
579
580static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie)
581{
582 int ret;
583
584 /* disable CAL LDO and fine tune RFDIG LDO */
585 ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002);
586 if (ret)
587 return ret;
588
589 ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002);
590 if (ret)
591 return ret;
592
593 ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002);
594 if (ret)
595 return ret;
596
597 ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002);
598 if (ret)
599 return ret;
600
601 /* set CKA driving and filter */
602 ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa);
603 if (ret)
604 return ret;
605
606 /* set CKB LDO to 1.4V */
607 ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a);
608 if (ret)
609 return ret;
610
611 /* turn on SX0 LTBUF */
612 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002);
613 if (ret)
614 return ret;
615
616 /* CK_BUF_SW_EN = 1 (all buf in manual mode.) */
617 ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0);
618 if (ret)
619 return ret;
620
621 /* BT mode/WF normal mode 00000005 */
622 ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005);
623 if (ret)
624 return ret;
625
626 /* BG thermal sensor offset update */
627 ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088);
628 if (ret)
629 return ret;
630
631 ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088);
632 if (ret)
633 return ret;
634
635 ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088);
636 if (ret)
637 return ret;
638
639 ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088);
640 if (ret)
641 return ret;
642
643 /* set WCON VDD IPTAT to "0000" */
644 ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000);
645 if (ret)
646 return ret;
647
648 /* change back LTBUF SX3 drving to default value */
649 ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa);
650 if (ret)
651 return ret;
652
653 /* SM input cap off */
654 ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000);
655 if (ret)
656 return ret;
657
658 /* set CKB driving and filter */
659 return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072);
660}
661
662static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type)
663{
664 int ret;
665
666 mt76_wmac_spi_lock(dev);
667 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0);
668 if (ret)
669 goto out;
670
671 if (is_7975(dev, adie, adie_type)) {
672 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK,
673 BIT(1), 0x1);
674 if (ret)
675 goto out;
676
677 ret = mt7986_wmac_adie_thermal_cal(dev, adie);
678 if (ret)
679 goto out;
680
681 ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie);
682 if (ret)
683 goto out;
684
685 ret = mt7986_wmac_adie_patch_7975(dev, adie);
686 } else if (is_7976(dev, adie, adie_type)) {
687 if (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC) {
688 ret = mt76_wmac_spi_write(dev, adie,
689 MT_ADIE_WRI_CK_SEL, 0x1c);
690 if (ret)
691 goto out;
692 }
693
694 ret = mt7986_wmac_adie_thermal_cal(dev, adie);
695 if (ret)
696 goto out;
697
698 ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie);
699 if (ret)
700 goto out;
701
702 ret = mt7986_wmac_adie_patch_7976(dev, adie);
703 }
704out:
705 mt76_wmac_spi_unlock(dev);
706
707 return ret;
708}
709
710static int
711mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type)
712{
713 int ret;
714 u8 idx;
715
716 mt76_wmac_spi_lock(dev);
717 if (is_7975(dev, adie, adie_type))
718 ret = mt76_wmac_spi_write(dev, adie,
719 MT_AFE_RG_ENCAL_WBTAC_IF_SW,
720 0x80000000);
721 else
722 ret = mt76_wmac_spi_write(dev, adie,
723 MT_AFE_RG_ENCAL_WBTAC_IF_SW,
724 0x88888005);
725 if (ret)
726 goto out;
727
728 idx = dbdc ? ADIE_DBDC : adie;
729
730 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx),
731 MT_AFE_RG_WBG_EN_RCK_MASK, 0x1);
732 usleep_range(60, 100);
733
734 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx),
735 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0);
736
737 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
738 MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1);
739 usleep_range(30, 100);
740
741 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
742 MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1);
743 usleep_range(60, 100);
744
745 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx),
746 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x1f);
747 usleep_range(800, 1000);
748
749 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx),
750 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x0);
751 mt76_rmw(dev, MT_AFE_DIG_EN_03(idx),
752 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0);
753
754 ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW,
755 0x5);
756
757out:
758 mt76_wmac_spi_unlock(dev);
759
760 return ret;
761}
762
763static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band)
764{
765 mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band),
766 MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL);
767
768 mt76_rmw(dev, MT_AFE_DIG_EN_02(band),
769 MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL);
770
771 mt76_rmw(dev, MT_AFE_DIG_TOP_01(band),
772 MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL);
773}
774
775static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev)
776{
777 /* Subsys pll init */
778 mt7986_wmac_subsys_pll_initial(dev, 0);
779 mt7986_wmac_subsys_pll_initial(dev, 1);
780
781 /* Set legacy OSC control stable time*/
782 mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN,
783 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0);
784 mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL,
785 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706);
786
787 /* prevent subsys from power on/of in a short time interval */
788 mt76_rmw(dev, MT_TOP_WFSYS_PWR,
789 MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK,
790 MT_TOP_PWR_KEY);
791}
792
793static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev)
794{
795 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
796 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2);
797
798 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
799 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
800
801 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
802 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc);
803
804 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
805 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
806
807 return mt7986_wmac_coninfra_check(dev);
808}
809
810static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type)
811{
812 u32 cur;
813
814 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
815 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
816
817 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
818 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
819
820 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
821 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
822
823 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
824 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
825
826 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
827 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8);
828
829 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
830 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
831
832 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
833 MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0);
834
835 mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL,
836 MT_CONN_INFRA_HW_CTRL_MASK, 0x1);
837
838 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
839 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1);
840
841 usleep_range(900, 1000);
842
843 mt76_wmac_spi_lock(dev);
844 if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) {
845 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0),
846 MT_SLP_CTRL_EN_MASK, 0x1);
847
848 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
849 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
850 dev, MT_ADIE_SLP_CTRL_CK0(0));
851 }
852 if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) {
853 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1),
854 MT_SLP_CTRL_EN_MASK, 0x1);
855
856 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
857 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
858 dev, MT_ADIE_SLP_CTRL_CK0(0));
859 }
860 mt76_wmac_spi_unlock(dev);
861
862 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
863 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0);
864 usleep_range(900, 1000);
865}
866
867static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable)
868{
869 mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP,
870 MT_TOP_WFSYS_WAKEUP_MASK, enable);
871
872 usleep_range(900, 1000);
873
874 if (!enable)
875 return 0;
876
877 return mt7986_wmac_coninfra_check(dev);
878}
879
880static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable)
881{
882 u32 cur;
883
884 mt76_rmw_field(dev, MT7986_TOP_WM_RESET,
885 MT7986_TOP_WM_RESET_MASK, enable);
886 if (!enable)
887 return 0;
888
889 return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e),
890 USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false,
891 dev, MT_TOP_CFG_ON_ROM_IDX);
892}
893
894static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable)
895{
896 u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK;
897 u32 cur;
898
899 mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask,
900 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable));
901
902 return read_poll_timeout(mt76_rr, cur,
903 (FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable),
904 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
905 dev, MT_TOP_WFSYS_RESET_STATUS);
906}
907
908static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev)
909{
910 int ret;
911 u32 cur;
912
913 /* Turn off wfsys2conn bus sleep protect */
914 mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT,
915 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0);
916
917 ret = mt7986_wmac_wfsys_poweron(dev, true);
918 if (ret)
919 return ret;
920
921 /* Check bus sleep protect */
922
923 ret = read_poll_timeout(mt76_rr, cur,
924 !(cur & MT_CONN_INFRA_CONN_WF_MASK),
925 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
926 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
927 if (ret)
928 return ret;
929
930 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK),
931 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
932 dev, MT_SLP_STATUS);
933 if (ret)
934 return ret;
935
936 return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000),
937 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
938 dev, MT_TOP_CFG_IP_VERSION_ADDR);
939}
940
941static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev)
942{
943 u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK |
944 MT_MCU_BUS_TIMEOUT_CG_EN_MASK |
945 MT_MCU_BUS_TIMEOUT_EN_MASK;
946 u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) |
947 FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) |
948 FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1);
949
950 mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val);
951
952 mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000);
953
954 mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK |
955 MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK |
956 MT_MCU_BUS_DBG_TIMEOUT_EN_MASK;
957 val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) |
958 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) |
959 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1);
960
961 mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val);
962}
963
964static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type)
965{
966 u32 val;
967
968 if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type))
969 val = 0xf;
970 else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type))
971 val = 0xd;
972 else if (is_7976(dev, 0, adie_type))
973 val = 0x7;
974 else if (is_7975(dev, 1, adie_type))
975 val = 0x8;
976 else if (is_7976(dev, 1, adie_type))
977 val = 0xa;
978 else
979 return -EINVAL;
980
981 mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK,
982 FIELD_PREP(MT_TOP_POS_SKU_MASK, val));
983
984 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val);
985
986 return 0;
987}
988
989static int
990mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type)
991{
992 int ret;
993
994 if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type)))
995 return 0;
996
997 ret = mt7986_wmac_adie_cfg(dev, adie, adie_type);
998 if (ret)
999 return ret;
1000
1001 ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type);
1002 if (ret)
1003 return ret;
1004
1005 if (!adie && (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC))
1006 ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type);
1007
1008 return ret;
1009}
1010
1011static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type)
1012{
1013 int ret;
1014
1015 mt7986_wmac_subsys_setting(dev);
1016
1017 ret = mt7986_wmac_bus_timeout(dev);
1018 if (ret)
1019 return ret;
1020
1021 mt7986_wmac_clock_enable(dev, adie_type);
1022
1023 return 0;
1024}
1025
1026static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev)
1027{
1028 int ret;
1029
1030 ret = mt7986_wmac_wm_enable(dev, false);
1031 if (ret)
1032 return ret;
1033
1034 ret = mt7986_wmac_wfsys_setting(dev);
1035 if (ret)
1036 return ret;
1037
1038 mt7986_wmac_wfsys_set_timeout(dev);
1039
1040 return mt7986_wmac_wm_enable(dev, true);
1041}
1042
1043int mt7986_wmac_enable(struct mt7915_dev *dev)
1044{
1045 int ret;
1046 u32 adie_type;
1047
1048 ret = mt7986_wmac_consys_reset(dev, true);
1049 if (ret)
1050 return ret;
1051
1052 ret = mt7986_wmac_gpio_setup(dev);
1053 if (ret)
1054 return ret;
1055
1056 ret = mt7986_wmac_consys_lockup(dev, false);
1057 if (ret)
1058 return ret;
1059
1060 ret = mt7986_wmac_coninfra_check(dev);
1061 if (ret)
1062 return ret;
1063
1064 ret = mt7986_wmac_coninfra_setup(dev);
1065 if (ret)
1066 return ret;
1067
1068 ret = mt7986_wmac_sku_setup(dev, &adie_type);
1069 if (ret)
1070 return ret;
1071
1072 ret = mt7986_wmac_adie_setup(dev, 0, adie_type);
1073 if (ret)
1074 return ret;
1075
1076 ret = mt7986_wmac_adie_setup(dev, 1, adie_type);
1077 if (ret)
1078 return ret;
1079
1080 ret = mt7986_wmac_subsys_powerup(dev, adie_type);
1081 if (ret)
1082 return ret;
1083
1084 ret = mt7986_wmac_top_wfsys_wakeup(dev, true);
1085 if (ret)
1086 return ret;
1087
1088 ret = mt7986_wmac_wfsys_powerup(dev);
1089 if (ret)
1090 return ret;
1091
1092 return mt7986_wmac_sku_update(dev, adie_type);
1093}
1094
1095void mt7986_wmac_disable(struct mt7915_dev *dev)
1096{
1097 u32 cur;
1098
1099 mt7986_wmac_top_wfsys_wakeup(dev, true);
1100
1101 /* Turn on wfsys2conn bus sleep protect */
1102 mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT,
1103 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1);
1104
1105 /* Check wfsys2conn bus sleep protect */
1106 read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN),
1107 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
1108 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
1109
1110 mt7986_wmac_wfsys_poweron(dev, false);
1111
1112 /* Turn back wpll setting */
1113 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2);
1114 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2);
1115
1116 /* Reset EMI */
1117 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1118 MT_CONN_INFRA_EMI_REQ_MASK, 0x1);
1119 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1120 MT_CONN_INFRA_EMI_REQ_MASK, 0x0);
1121 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1122 MT_CONN_INFRA_INFRA_REQ_MASK, 0x1);
1123 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1124 MT_CONN_INFRA_INFRA_REQ_MASK, 0x0);
1125
1126 mt7986_wmac_top_wfsys_wakeup(dev, false);
1127 mt7986_wmac_consys_lockup(dev, true);
1128 mt7986_wmac_consys_reset(dev, false);
1129}
1130
1131static int mt7986_wmac_init(struct mt7915_dev *dev)
1132{
1133 struct device *pdev = dev->mt76.dev;
1134 struct platform_device *pfdev = to_platform_device(pdev);
1135 struct clk *mcu_clk, *ap_conn_clk;
1136
1137 mcu_clk = devm_clk_get(pdev, "mcu");
1138 if (IS_ERR(mcu_clk))
1139 dev_err(pdev, "mcu clock not found\n");
1140 else if (clk_prepare_enable(mcu_clk))
1141 dev_err(pdev, "mcu clock configuration failed\n");
1142
1143 ap_conn_clk = devm_clk_get(pdev, "ap2conn");
1144 if (IS_ERR(ap_conn_clk))
1145 dev_err(pdev, "ap2conn clock not found\n");
1146 else if (clk_prepare_enable(ap_conn_clk))
1147 dev_err(pdev, "ap2conn clock configuration failed\n");
1148
1149 dev->dcm = devm_platform_ioremap_resource(pfdev, 1);
1150 if (IS_ERR(dev->dcm))
1151 return PTR_ERR(dev->dcm);
1152
1153 dev->sku = devm_platform_ioremap_resource(pfdev, 2);
1154 if (IS_ERR(dev->sku))
1155 return PTR_ERR(dev->sku);
1156
1157 dev->rstc = devm_reset_control_get(pdev, "consys");
1158 if (IS_ERR(dev->rstc))
1159 return PTR_ERR(dev->rstc);
1160
1161 return 0;
1162}
1163
1164static int mt7986_wmac_probe(struct platform_device *pdev)
1165{
1166 void __iomem *mem_base;
1167 struct mt7915_dev *dev;
1168 struct mt76_dev *mdev;
1169 int irq, ret;
1170 u32 chip_id;
1171
1172 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
1173
1174 mem_base = devm_platform_ioremap_resource(pdev, 0);
1175 if (IS_ERR(mem_base)) {
1176 dev_err(&pdev->dev, "Failed to get memory resource\n");
1177 return PTR_ERR(mem_base);
1178 }
1179
1180 dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id);
1181 if (IS_ERR(dev))
1182 return PTR_ERR(dev);
1183
1184 mdev = &dev->mt76;
1185 ret = mt7915_mmio_wed_init(dev, pdev, false, &irq);
1186 if (ret < 0)
1187 goto free_device;
1188
1189 if (!ret) {
1190 irq = platform_get_irq(pdev, 0);
1191 if (irq < 0) {
1192 ret = irq;
1193 goto free_device;
1194 }
1195 }
1196
1197 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler,
1198 IRQF_SHARED, KBUILD_MODNAME, dev);
1199 if (ret)
1200 goto free_device;
1201
1202 ret = mt7986_wmac_init(dev);
1203 if (ret)
1204 goto free_irq;
1205
1206 mt7915_wfsys_reset(dev);
1207
1208 ret = mt7915_register_device(dev);
1209 if (ret)
1210 goto free_irq;
1211
1212 return 0;
1213
1214free_irq:
1215 devm_free_irq(mdev->dev, irq, dev);
1216free_device:
1217 if (mtk_wed_device_active(&mdev->mmio.wed))
1218 mtk_wed_device_detach(&mdev->mmio.wed);
1219 mt76_free_device(mdev);
1220
1221 return ret;
1222}
1223
1224static int mt7986_wmac_remove(struct platform_device *pdev)
1225{
1226 struct mt7915_dev *dev = platform_get_drvdata(pdev);
1227
1228 mt7915_unregister_device(dev);
1229
1230 return 0;
1231}
1232
1233static const struct of_device_id mt7986_wmac_of_match[] = {
1234 { .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 },
1235 {},
1236};
1237
1238struct platform_driver mt7986_wmac_driver = {
1239 .driver = {
1240 .name = "mt7986-wmac",
1241 .of_match_table = mt7986_wmac_of_match,
1242 },
1243 .probe = mt7986_wmac_probe,
1244 .remove = mt7986_wmac_remove,
1245};
1246
1247MODULE_FIRMWARE(MT7986_FIRMWARE_WA);
1248MODULE_FIRMWARE(MT7986_FIRMWARE_WM);
1249MODULE_FIRMWARE(MT7986_FIRMWARE_WM_MT7975);
1250MODULE_FIRMWARE(MT7986_ROM_PATCH);
1251MODULE_FIRMWARE(MT7986_ROM_PATCH_MT7975);