blob: ec729dbe1cd81db1e9200301c3ff79f68193906f [file] [log] [blame]
developer0f312e82022-11-01 12:31:52 +08001// SPDX-License-Identifier: ISC
2/* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Lorenzo Bianconi <lorenzo@kernel.org>
7 * Felix Fietkau <nbd@nbd.name>
8 */
9
10#include "mt7615.h"
11#include "../dma.h"
12#include "mac.h"
13
14static int
15mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
16{
17 static const u8 wmm_queue_map[] = {
18 [IEEE80211_AC_BK] = MT7622_TXQ_AC0,
19 [IEEE80211_AC_BE] = MT7622_TXQ_AC1,
20 [IEEE80211_AC_VI] = MT7622_TXQ_AC2,
21 [IEEE80211_AC_VO] = MT7622_TXQ_AC3,
22 };
23 int ret;
24 int i;
25
26 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],
28 MT7615_TX_RING_SIZE / 2,
29 MT_TX_RING_BASE, 0);
30 if (ret)
31 return ret;
32 }
33
34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT,
35 MT7615_TX_MGMT_RING_SIZE,
36 MT_TX_RING_BASE, 0);
37 if (ret)
38 return ret;
39
40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU,
41 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
42}
43
44static int
45mt7615_init_tx_queues(struct mt7615_dev *dev)
46{
47 int ret;
48
49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL,
50 MT7615_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
51 if (ret)
52 return ret;
53
54 if (!is_mt7615(&dev->mt76))
55 return mt7622_init_tx_queues_multi(dev);
56
57 ret = mt76_connac_init_tx_queues(&dev->mphy, 0, MT7615_TX_RING_SIZE,
58 MT_TX_RING_BASE, 0);
59 if (ret)
60 return ret;
61
62 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU,
63 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
64}
65
66static int mt7615_poll_tx(struct napi_struct *napi, int budget)
67{
68 struct mt7615_dev *dev;
69
70 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
71 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
72 napi_complete(napi);
73 queue_work(dev->mt76.wq, &dev->pm.wake_work);
74 return 0;
75 }
76
77 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
78 if (napi_complete(napi))
79 mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
80
81 mt76_connac_pm_unref(&dev->mphy, &dev->pm);
82
83 return 0;
84}
85
86static int mt7615_poll_rx(struct napi_struct *napi, int budget)
87{
88 struct mt7615_dev *dev;
89 int done;
90
91 dev = container_of(napi->dev, struct mt7615_dev, mt76.napi_dev);
92
93 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
94 napi_complete(napi);
95 queue_work(dev->mt76.wq, &dev->pm.wake_work);
96 return 0;
97 }
98 done = mt76_dma_rx_poll(napi, budget);
99 mt76_connac_pm_unref(&dev->mphy, &dev->pm);
100
101 return done;
102}
103
104int mt7615_wait_pdma_busy(struct mt7615_dev *dev)
105{
106 struct mt76_dev *mdev = &dev->mt76;
107
108 if (!is_mt7663(mdev)) {
109 u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY;
110 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY);
111
112 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {
113 dev_err(mdev->dev, "PDMA engine busy\n");
114 return -EIO;
115 }
116
117 return 0;
118 }
119
120 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
121 MT_PDMA_TX_IDX_BUSY, 0, 1000)) {
122 dev_err(mdev->dev, "PDMA engine tx busy\n");
123 return -EIO;
124 }
125
126 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,
127 MT_PSE_SRC_CNT, 0, 1000)) {
128 dev_err(mdev->dev, "PSE engine busy\n");
129 return -EIO;
130 }
131
132 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
133 MT_PDMA_BUSY_IDX, 0, 1000)) {
134 dev_err(mdev->dev, "PDMA engine busy\n");
135 return -EIO;
136 }
137
138 return 0;
139}
140
141static void mt7622_dma_sched_init(struct mt7615_dev *dev)
142{
143 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);
144 int i;
145
146 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
147 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
148 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
149 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
150
151 for (i = 0; i <= 5; i++)
152 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),
153 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |
154 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
155
156 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);
157 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);
158 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);
159 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);
160
161 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);
162 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);
163}
164
165static void mt7663_dma_sched_init(struct mt7615_dev *dev)
166{
167 int i;
168
169 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
170 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
171 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
172 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
173
174 /* enable refill control group 0, 1, 2, 4, 5 */
175 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);
176 /* enable group 0, 1, 2, 4, 5, 15 */
177 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);
178
179 /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */
180 for (i = 0; i < 5; i++)
181 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),
182 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
183 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
184 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),
185 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
186 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));
187 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),
188 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |
189 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));
190
191 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);
192 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);
193 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);
194 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);
195 /* ALTX0 and ALTX1 QID mapping to group 5 */
196 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);
197 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);
198}
199
200void mt7615_dma_start(struct mt7615_dev *dev)
201{
202 /* start dma engine */
203 mt76_set(dev, MT_WPDMA_GLO_CFG,
204 MT_WPDMA_GLO_CFG_TX_DMA_EN |
205 MT_WPDMA_GLO_CFG_RX_DMA_EN |
206 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
207
208 if (is_mt7622(&dev->mt76))
209 mt7622_dma_sched_init(dev);
210
211 if (is_mt7663(&dev->mt76)) {
212 mt7663_dma_sched_init(dev);
213
214 mt76_wr(dev, MT_MCU2HOST_INT_ENABLE, MT7663_MCU_CMD_ERROR_MASK);
215 }
216
217}
218
219int mt7615_dma_init(struct mt7615_dev *dev)
220{
221 int rx_ring_size = MT7615_RX_RING_SIZE;
222 u32 mask;
223 int ret;
224
225 mt76_dma_attach(&dev->mt76);
226
227 mt76_wr(dev, MT_WPDMA_GLO_CFG,
228 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
229 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
230 MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
231
232 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
233 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
234
235 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
236 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);
237
238 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
239 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);
240
241 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
242 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
243
244 if (is_mt7615(&dev->mt76)) {
245 mt76_set(dev, MT_WPDMA_GLO_CFG,
246 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);
247
248 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
249 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
250 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
251 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
252 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
253 mt76_set(dev, 0x7158, BIT(16));
254 mt76_clear(dev, 0x7000, BIT(23));
255 }
256
257 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
258
259 ret = mt7615_init_tx_queues(dev);
260 if (ret)
261 return ret;
262
263 /* init rx queues */
264 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
265 MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE,
266 MT_RX_RING_BASE);
267 if (ret)
268 return ret;
269
270 if (!is_mt7615(&dev->mt76))
271 rx_ring_size /= 2;
272
273 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
274 rx_ring_size, MT_RX_BUF_SIZE, MT_RX_RING_BASE);
275 if (ret)
276 return ret;
277
278 mt76_wr(dev, MT_DELAY_INT_CFG, 0);
279
280 ret = mt76_init_queues(dev, mt7615_poll_rx);
281 if (ret < 0)
282 return ret;
283
284 netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
285 mt7615_poll_tx, NAPI_POLL_WEIGHT);
286 napi_enable(&dev->mt76.tx_napi);
287
288 mt76_poll(dev, MT_WPDMA_GLO_CFG,
289 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
290 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);
291
292 /* enable interrupts for TX/RX rings */
293
294 mask = MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev);
295 if (is_mt7663(&dev->mt76))
296 mask |= MT7663_INT_MCU_CMD;
297 else
298 mask |= MT_INT_MCU_CMD;
299
300 mt7615_irq_enable(dev, mask);
301
302 mt7615_dma_start(dev);
303
304 return 0;
305}
306
307void mt7615_dma_cleanup(struct mt7615_dev *dev)
308{
309 mt76_clear(dev, MT_WPDMA_GLO_CFG,
310 MT_WPDMA_GLO_CFG_TX_DMA_EN |
311 MT_WPDMA_GLO_CFG_RX_DMA_EN);
312 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
313
314 mt76_dma_cleanup(&dev->mt76);
315}