developer | 474d775 | 2024-03-15 09:08:04 +0800 | [diff] [blame^] | 1 | From b8076a11b6051ed0fe1deb6c94e97bf80a13fbff Mon Sep 17 00:00:00 2001 |
| 2 | From: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 3 | Date: Thu, 14 Mar 2024 17:55:12 +0800 |
| 4 | Subject: [PATCH] wifi: mt76: mt7915: update power on sequence |
| 5 | |
| 6 | Update power on sequence to prevent unexpected behavior. |
| 7 | |
| 8 | Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 9 | |
| 10 | diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h |
| 11 | index 874d5318..6bee0f9a 100644 |
| 12 | --- a/mt7915/mt7915.h |
| 13 | +++ b/mt7915/mt7915.h |
| 14 | @@ -325,6 +325,7 @@ struct mt7915_dev { |
| 15 | |
| 16 | bool wmm_pbc_enable; |
| 17 | struct work_struct wmm_pbc_work; |
| 18 | + u32 adie_type; |
| 19 | }; |
| 20 | |
| 21 | enum { |
| 22 | diff --git a/mt7915/regs.h b/mt7915/regs.h |
| 23 | index 7515b23f..3452a7e9 100644 |
| 24 | --- a/mt7915/regs.h |
| 25 | +++ b/mt7915/regs.h |
| 26 | @@ -775,6 +775,7 @@ enum offs_rev { |
| 27 | #define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050) |
| 28 | #define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054) |
| 29 | #define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010) |
| 30 | +#define MT_TOP_BGFYS_PWR (MT_TOP_RGU_BASE + 0x020) |
| 31 | #define MT_TOP_PWR_EN_MASK BIT(7) |
| 32 | #define MT_TOP_PWR_ACK_MASK BIT(6) |
| 33 | #define MT_TOP_PWR_KEY_MASK GENMASK(31, 16) |
| 34 | @@ -886,6 +887,7 @@ enum offs_rev { |
| 35 | #define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs)) |
| 36 | |
| 37 | #define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120) |
| 38 | +#define MT_ADIE_SLP_CTRL_CK1(_band) MT_ADIE_SLP_CTRL(_band, 0x124) |
| 39 | |
| 40 | /* ADIE */ |
| 41 | #define MT_ADIE_CHIP_ID 0x02c |
| 42 | diff --git a/mt7915/soc.c b/mt7915/soc.c |
| 43 | index b2916b02..210b4f16 100644 |
| 44 | --- a/mt7915/soc.c |
| 45 | +++ b/mt7915/soc.c |
| 46 | @@ -261,6 +261,7 @@ static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable) |
| 47 | MT_INFRACFG_TX_EN_MASK, |
| 48 | FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); |
| 49 | |
| 50 | + usleep_range(1000, 2000); |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | @@ -845,6 +846,10 @@ static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev) |
| 55 | MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706); |
| 56 | |
| 57 | /* prevent subsys from power on/of in a short time interval */ |
| 58 | + mt76_rmw(dev, MT_TOP_BGFYS_PWR, |
| 59 | + MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK, |
| 60 | + (0x42540000)); |
| 61 | + |
| 62 | mt76_rmw(dev, MT_TOP_WFSYS_PWR, |
| 63 | MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK, |
| 64 | MT_TOP_PWR_KEY); |
| 65 | @@ -915,7 +920,7 @@ static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type) |
| 66 | |
| 67 | read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), |
| 68 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 69 | - dev, MT_ADIE_SLP_CTRL_CK0(0)); |
| 70 | + dev, MT_ADIE_SLP_CTRL_CK0(1)); |
| 71 | } |
| 72 | mt76_wmac_spi_unlock(dev); |
| 73 | |
| 74 | @@ -1155,12 +1160,14 @@ int mt7986_wmac_enable(struct mt7915_dev *dev) |
| 75 | if (ret) |
| 76 | return ret; |
| 77 | |
| 78 | + dev->adie_type = adie_type; |
| 79 | + |
| 80 | return mt7986_wmac_sku_update(dev, adie_type); |
| 81 | } |
| 82 | |
| 83 | void mt7986_wmac_disable(struct mt7915_dev *dev) |
| 84 | { |
| 85 | - u32 cur; |
| 86 | + u32 cur, i; |
| 87 | |
| 88 | mt7986_wmac_top_wfsys_wakeup(dev, true); |
| 89 | |
| 90 | @@ -1179,6 +1186,20 @@ void mt7986_wmac_disable(struct mt7915_dev *dev) |
| 91 | mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2); |
| 92 | mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2); |
| 93 | |
| 94 | + /* Disable adie top clock */ |
| 95 | + mt76_wmac_spi_lock(dev); |
| 96 | + for (i = 0; i < 2; i++) { |
| 97 | + if (is_7975(dev, i, dev->adie_type) || is_7976(dev, i, dev->adie_type)) { |
| 98 | + mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK1(i), |
| 99 | + MT_SLP_CTRL_EN_MASK, 0x0); |
| 100 | + |
| 101 | + read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), |
| 102 | + USEC_PER_MSEC, 50 * USEC_PER_MSEC, |
| 103 | + false, dev, MT_ADIE_SLP_CTRL_CK1(i)); |
| 104 | + } |
| 105 | + } |
| 106 | + mt76_wmac_spi_unlock(dev); |
| 107 | + |
| 108 | /* Reset EMI */ |
| 109 | mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, |
| 110 | MT_CONN_INFRA_EMI_REQ_MASK, 0x1); |
| 111 | @@ -1190,6 +1211,28 @@ void mt7986_wmac_disable(struct mt7915_dev *dev) |
| 112 | MT_CONN_INFRA_INFRA_REQ_MASK, 0x0); |
| 113 | |
| 114 | mt7986_wmac_top_wfsys_wakeup(dev, false); |
| 115 | + |
| 116 | + mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, |
| 117 | + MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1); |
| 118 | + |
| 119 | + usleep_range(1000, 1100); |
| 120 | + |
| 121 | + mt76_wmac_spi_lock(dev); |
| 122 | + for (i = 0; i < 2; i++) { |
| 123 | + if (is_7975(dev, i, dev->adie_type) || is_7976(dev, i, dev->adie_type)) { |
| 124 | + mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(i), |
| 125 | + MT_SLP_CTRL_EN_MASK, 0x0); |
| 126 | + |
| 127 | + read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), |
| 128 | + USEC_PER_MSEC, 50 * USEC_PER_MSEC, |
| 129 | + false, dev, MT_ADIE_SLP_CTRL_CK0(i)); |
| 130 | + } |
| 131 | + } |
| 132 | + mt76_wmac_spi_unlock(dev); |
| 133 | + |
| 134 | + mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, |
| 135 | + MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0); |
| 136 | + |
| 137 | mt7986_wmac_consys_lockup(dev, true); |
| 138 | mt7986_wmac_consys_reset(dev, false); |
| 139 | } |
| 140 | -- |
| 141 | 2.18.0 |
| 142 | |