developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright (c) 2022 MediaTek Inc. |
| 4 | * Author: Henry Yen <henry.yen@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/bits.h> |
| 8 | #include <linux/clk.h> |
| 9 | #include <linux/delay.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/io.h> |
| 12 | #include <linux/iopoll.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/nvmem-consumer.h> |
| 16 | #include <linux/of_irq.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_address.h> |
| 19 | #include <linux/of_device.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/reset.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/string.h> |
| 24 | #include <linux/thermal.h> |
| 25 | #include "soc_temp_lvts.h" |
| 26 | |
| 27 | /* |
| 28 | * Definition or macro function |
| 29 | */ |
| 30 | #define STOP_COUNTING_V5 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x00) |
| 31 | #define SET_RG_TSFM_LPDLY_V5 (DEVICE_WRITE | RG_TSFM_CTRL_4 << 8 | 0xA6) |
| 32 | #define SET_COUNTING_WINDOW_20US1_V5 (DEVICE_WRITE | RG_TSFM_CTRL_2 << 8 | 0x00) |
| 33 | #define SET_COUNTING_WINDOW_20US2_V5 (DEVICE_WRITE | RG_TSFM_CTRL_1 << 8 | 0x20) |
| 34 | #define TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V5 \ |
| 35 | (DEVICE_WRITE | RG_TSV2F_CTRL_2 << 8 | 0x8C) |
| 36 | #define TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V5 \ |
| 37 | (DEVICE_WRITE | RG_TSV2F_CTRL_4 << 8 | 0xFC) |
| 38 | #define SET_TS_RSV_V5 (DEVICE_WRITE | RG_TSV2F_CTRL_1 << 8 | 0x8D) |
| 39 | #define SET_TS_EN_V5 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF1) |
| 40 | |
| 41 | #define SET_MANUAL_RCK_V5 (DEVICE_WRITE | RG_TSV2F_CTRL_6 << 8 | 0x00) |
| 42 | #define SELECT_SENSOR_RCK_V5(id) (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | (id)) |
| 43 | #define SET_DEVICE_SINGLE_MODE_V5 (DEVICE_WRITE | RG_TSFM_CTRL_3 << 8 | 0xB8) |
| 44 | #define KICK_OFF_RCK_COUNTING_V5 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x02) |
| 45 | #define SET_SENSOR_NO_RCK_V5(id) \ |
| 46 | (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | 0x10 | (id)) |
| 47 | #define SET_DEVICE_LOW_POWER_SINGLE_MODE_V5 \ |
| 48 | (DEVICE_WRITE | RG_TSFM_CTRL_3 << 8 | 0xB8) |
| 49 | |
| 50 | #define STOP_COUNTING_V4 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x00) |
| 51 | #define SET_RG_TSFM_LPDLY_V4 (DEVICE_WRITE | RG_TSFM_CTRL_4 << 8 | 0xA6) |
| 52 | #define SET_COUNTING_WINDOW_20US1_V4 (DEVICE_WRITE | RG_TSFM_CTRL_2 << 8 | 0x00) |
| 53 | #define SET_COUNTING_WINDOW_20US2_V4 (DEVICE_WRITE | RG_TSFM_CTRL_1 << 8 | 0x20) |
| 54 | #define TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4 \ |
| 55 | (DEVICE_WRITE | RG_TSV2F_CTRL_2 << 8 | 0x84) |
| 56 | #define TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4 \ |
| 57 | (DEVICE_WRITE | RG_TSV2F_CTRL_4 << 8 | 0x7C) |
| 58 | #define SET_TS_RSV_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_1 << 8 | 0x8D) |
| 59 | #define SET_TS_EN_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF4) |
| 60 | #define TOGGLE_RG_TSV2F_VCO_RST1_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xFC) |
| 61 | #define TOGGLE_RG_TSV2F_VCO_RST2_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF4) |
| 62 | |
| 63 | #define SET_LVTS_AUTO_RCK_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_6 << 8 | 0x01) |
| 64 | #define SELECT_SENSOR_RCK_V4(id) (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | (id)) |
| 65 | #define SET_DEVICE_SINGLE_MODE_V4 (DEVICE_WRITE | RG_TSFM_CTRL_3 << 8 | 0x78) |
| 66 | #define KICK_OFF_RCK_COUNTING_V4 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x02) |
| 67 | #define SET_SENSOR_NO_RCK_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | 0x10) |
| 68 | #define SET_DEVICE_LOW_POWER_SINGLE_MODE_V4 \ |
| 69 | (DEVICE_WRITE | RG_TSFM_CTRL_3 << 8 | 0xB8) |
| 70 | |
| 71 | #define ENABLE_FEATURE(feature) (lvts_data->feature_bitmap |= (feature)) |
| 72 | #define DISABLE_FEATURE(feature) (lvts_data->feature_bitmap &= (~(feature))) |
| 73 | #define IS_ENABLE(feature) (lvts_data->feature_bitmap & (feature)) |
| 74 | |
| 75 | #define DISABLE_THERMAL_HW_REBOOT (-274000) |
| 76 | |
| 77 | #define CLOCK_26MHZ_CYCLE_NS (38) |
| 78 | #define BUS_ACCESS_US (2) |
| 79 | #define GOLDEN_TEMP_MAX (62) |
| 80 | #define FEATURE_DEVICE_AUTO_RCK (BIT(0)) |
| 81 | #define FEATURE_CK26M_ACTIVE (BIT(1)) |
| 82 | #define FEATURE_IRQ (BIT(2)) |
| 83 | #define FEATURE_RESET (BIT(3)) |
| 84 | #define CK26M_ACTIVE \ |
| 85 | (((lvts_data->feature_bitmap & FEATURE_CK26M_ACTIVE) ? 1 : 0) << 30) |
| 86 | #define GET_BASE_ADDR(tc_id) \ |
| 87 | (lvts_data->domain[lvts_data->tc[tc_id].domain_index].base + \ |
| 88 | lvts_data->tc[tc_id].addr_offset) |
| 89 | |
| 90 | #define SET_TC_SPEED_IN_US(pu, gd, fd, sd) \ |
| 91 | { \ |
| 92 | .period_unit = (((pu)*1000) / (256 * CLOCK_26MHZ_CYCLE_NS)), \ |
| 93 | .group_interval_delay = ((gd) / (pu)), \ |
| 94 | .filter_interval_delay = ((fd) / (pu)), \ |
| 95 | .sensor_interval_delay = ((sd) / (pu)), \ |
| 96 | } |
| 97 | |
| 98 | #define GET_CAL_DATA_BITMASK(index, h, l) \ |
| 99 | (((index) < lvts_data->num_efuse_addr) ? \ |
| 100 | ((lvts_data->efuse[(index)] & GENMASK(h, l)) >> l) : \ |
| 101 | 0) |
| 102 | |
| 103 | #define GET_CAL_DATA_BIT(index, bit) \ |
| 104 | (((index) < lvts_data->num_efuse_addr) ? \ |
| 105 | ((lvts_data->efuse[index] & BIT(bit)) >> (bit)) : \ |
| 106 | 0) |
| 107 | |
| 108 | #define GET_TC_SENSOR_NUM(tc_id) (lvts_data->tc[tc_id].num_sensor) |
| 109 | |
| 110 | #define ONE_SAMPLE (lvts_data->counting_window_us + 2 * BUS_ACCESS_US) |
| 111 | |
| 112 | #define NUM_OF_SAMPLE(tc_id) \ |
| 113 | ((lvts_data->tc[tc_id].hw_filter < LVTS_FILTER_2) ? \ |
| 114 | 1 : \ |
| 115 | ((lvts_data->tc[tc_id].hw_filter > LVTS_FILTER_16_OF_18) ? \ |
| 116 | 1 : \ |
| 117 | ((lvts_data->tc[tc_id].hw_filter == \ |
| 118 | LVTS_FILTER_16_OF_18) ? \ |
| 119 | 18 : \ |
| 120 | ((lvts_data->tc[tc_id].hw_filter == \ |
| 121 | LVTS_FILTER_8_OF_10) ? \ |
| 122 | 10 : \ |
| 123 | (lvts_data->tc[tc_id].hw_filter * \ |
| 124 | 2))))) |
| 125 | |
| 126 | #define PERIOD_UNIT_US(tc_id) \ |
| 127 | ((lvts_data->tc[tc_id].tc_speed.period_unit * 256 * \ |
| 128 | CLOCK_26MHZ_CYCLE_NS) / \ |
| 129 | 1000) |
| 130 | #define FILTER_INT_US(tc_id) \ |
| 131 | (lvts_data->tc[tc_id].tc_speed.filter_interval_delay * \ |
| 132 | PERIOD_UNIT_US(tc_id)) |
| 133 | #define SENSOR_INT_US(tc_id) \ |
| 134 | (lvts_data->tc[tc_id].tc_speed.sensor_interval_delay * \ |
| 135 | PERIOD_UNIT_US(tc_id)) |
| 136 | #define GROUP_INT_US(tc_id) \ |
| 137 | (lvts_data->tc[tc_id].tc_speed.group_interval_delay * \ |
| 138 | PERIOD_UNIT_US(tc_id)) |
| 139 | |
| 140 | #define SENSOR_LATENCY_US(tc_id) \ |
| 141 | ((NUM_OF_SAMPLE(tc_id) - 1) * FILTER_INT_US(tc_id) + \ |
| 142 | NUM_OF_SAMPLE(tc_id) * ONE_SAMPLE) |
| 143 | |
| 144 | #define GROUP_LATENCY_US(tc_id) \ |
| 145 | (GET_TC_SENSOR_NUM(tc_id) * SENSOR_LATENCY_US(tc_id) + \ |
| 146 | (GET_TC_SENSOR_NUM(tc_id) - 1) * SENSOR_INT_US(tc_id) + \ |
| 147 | GROUP_INT_US(tc_id)) |
| 148 | |
| 149 | /* |
| 150 | * LVTS local common code |
| 151 | */ |
| 152 | static int lvts_raw_to_temp(struct formula_coeff *co, unsigned int msr_raw) |
| 153 | { |
| 154 | /* This function returns degree mC */ |
| 155 | |
| 156 | int temp; |
| 157 | |
| 158 | msr_raw &= 0xffff; |
| 159 | temp = (co->a * ((unsigned long long)msr_raw)) >> 14; |
| 160 | temp = temp + co->golden_temp * 500 + co->b; |
| 161 | |
| 162 | return temp; |
| 163 | } |
| 164 | |
| 165 | static unsigned int lvts_temp_to_raw(struct formula_coeff *co, int temp) |
| 166 | { |
| 167 | unsigned int msr_raw; |
| 168 | |
| 169 | msr_raw = ((long long)((co->golden_temp * 500 + co->b - temp)) << 14) / |
| 170 | (-1 * co->a); |
| 171 | |
| 172 | return msr_raw; |
| 173 | } |
| 174 | |
| 175 | static int lvts_read_all_tc_temperature(struct lvts_data *lvts_data) |
| 176 | { |
| 177 | struct tc_settings *tc = lvts_data->tc; |
| 178 | unsigned int i, j, s_index, msr_raw; |
| 179 | int max_temp = -100000, current_temp; |
| 180 | void __iomem *base; |
| 181 | |
| 182 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 183 | base = GET_BASE_ADDR(i); |
| 184 | for (j = 0; j < tc[i].num_sensor; j++) { |
| 185 | s_index = tc[i].sensor_map[j]; |
| 186 | |
| 187 | msr_raw = readl(LVTSMSR0_0 + base + 0x4 * j) & |
| 188 | MRS_RAW_MASK; |
| 189 | current_temp = |
| 190 | lvts_raw_to_temp(&lvts_data->coeff, msr_raw); |
| 191 | |
| 192 | if (msr_raw == 0) |
| 193 | current_temp = THERMAL_TEMP_INVALID; |
| 194 | |
| 195 | max_temp = max(max_temp, current_temp); |
| 196 | |
| 197 | lvts_data->sen_data[s_index].msr_raw = msr_raw; |
| 198 | lvts_data->sen_data[s_index].temp = current_temp; |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | return max_temp; |
| 203 | } |
| 204 | |
| 205 | static int soc_temp_lvts_read_temp(void *data, int *temperature) |
| 206 | { |
| 207 | struct soc_temp_tz *lvts_tz = (struct soc_temp_tz *)data; |
| 208 | struct lvts_data *lvts_data = lvts_tz->lvts_data; |
| 209 | |
| 210 | if (lvts_tz->id == 0) |
| 211 | *temperature = lvts_read_all_tc_temperature(lvts_data); |
| 212 | else if (lvts_tz->id - 1 < lvts_data->num_sensor) |
| 213 | *temperature = lvts_data->sen_data[lvts_tz->id - 1].temp; |
| 214 | else |
| 215 | return -EINVAL; |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | static const struct thermal_zone_of_device_ops soc_temp_lvts_ops = { |
| 221 | .get_temp = soc_temp_lvts_read_temp, |
| 222 | }; |
| 223 | |
| 224 | static void lvts_write_device(struct lvts_data *lvts_data, unsigned int data, |
| 225 | int tc_id) |
| 226 | { |
| 227 | void __iomem *base; |
| 228 | |
| 229 | base = GET_BASE_ADDR(tc_id); |
| 230 | |
| 231 | writel(data, LVTS_CONFIG_0 + base); |
| 232 | |
| 233 | usleep_range(5, 15); |
| 234 | } |
| 235 | |
| 236 | static unsigned int lvts_read_device(struct lvts_data *lvts_data, |
| 237 | unsigned int reg_idx, int tc_id) |
| 238 | { |
| 239 | struct device *dev = lvts_data->dev; |
| 240 | void __iomem *base; |
| 241 | unsigned int data; |
| 242 | int ret; |
| 243 | |
| 244 | base = GET_BASE_ADDR(tc_id); |
| 245 | writel(READ_DEVICE_REG(reg_idx), LVTS_CONFIG_0 + base); |
| 246 | |
| 247 | ret = readl_poll_timeout(LVTS_CONFIG_0 + base, data, |
| 248 | !(data & DEVICE_ACCESS_STARTUS), 2, 200); |
| 249 | if (ret) |
| 250 | dev_err(dev, |
| 251 | "Error: LVTS %d DEVICE_ACCESS_START didn't ready\n", |
| 252 | tc_id); |
| 253 | |
| 254 | data = readl(LVTSRDATA0_0 + base); |
| 255 | |
| 256 | return data; |
| 257 | } |
| 258 | |
| 259 | static void wait_all_tc_sensing_point_idle(struct lvts_data *lvts_data) |
| 260 | { |
| 261 | struct device *dev = lvts_data->dev; |
| 262 | unsigned int mask, error_code, is_error; |
| 263 | void __iomem *base; |
| 264 | int i, cnt, ret; |
| 265 | |
| 266 | mask = BIT(10) | BIT(7) | BIT(0); |
| 267 | |
| 268 | for (cnt = 0; cnt < 2; cnt++) { |
| 269 | is_error = 0; |
| 270 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 271 | base = GET_BASE_ADDR(i); |
| 272 | ret = readl_poll_timeout(LVTSMSRCTL1_0 + base, |
| 273 | error_code, |
| 274 | !(error_code & mask), 2, 200); |
| 275 | /* |
| 276 | * Error code |
| 277 | * 000: IDLE |
| 278 | * 001: Write transaction |
| 279 | * 010: Waiting for read after Write |
| 280 | * 011: Disable Continue fetching on Device |
| 281 | * 100: Read transaction |
| 282 | * 101: Set Device special Register for Voltage |
| 283 | * threshold |
| 284 | * 111: Set TSMCU number for Fetch |
| 285 | */ |
| 286 | error_code = ((error_code & BIT(10)) >> 8) + |
| 287 | ((error_code & BIT(7)) >> 6) + |
| 288 | (error_code & BIT(0)); |
| 289 | |
| 290 | if (ret) |
| 291 | dev_err(dev, |
| 292 | "Error LVTS %d sensing points aren't idle, error_code %d\n", |
| 293 | i, error_code); |
| 294 | |
| 295 | if (error_code != 0) |
| 296 | is_error = 1; |
| 297 | } |
| 298 | |
| 299 | if (is_error == 0) |
| 300 | break; |
| 301 | } |
| 302 | } |
| 303 | |
| 304 | static void lvts_reset(struct lvts_data *lvts_data) |
| 305 | { |
| 306 | int i; |
| 307 | |
| 308 | for (i = 0; i < lvts_data->num_domain; i++) { |
| 309 | if (lvts_data->domain[i].reset) |
| 310 | reset_control_assert(lvts_data->domain[i].reset); |
| 311 | |
| 312 | if (lvts_data->domain[i].reset) |
| 313 | reset_control_deassert(lvts_data->domain[i].reset); |
| 314 | } |
| 315 | } |
| 316 | |
| 317 | static void device_identification(struct lvts_data *lvts_data) |
| 318 | { |
| 319 | struct device *dev = lvts_data->dev; |
| 320 | unsigned int i, data; |
| 321 | void __iomem *base; |
| 322 | |
| 323 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 324 | base = GET_BASE_ADDR(i); |
| 325 | |
| 326 | writel(ENABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); |
| 327 | |
| 328 | lvts_write_device(lvts_data, RESET_ALL_DEVICES, i); |
| 329 | |
| 330 | lvts_write_device(lvts_data, READ_BACK_DEVICE_ID, i); |
| 331 | |
| 332 | /* Check LVTS device ID */ |
| 333 | data = (readl(LVTS_ID_0 + base) & GENMASK(7, 0)); |
| 334 | if (data != (0x83 + i)) |
| 335 | dev_err(dev, |
| 336 | "LVTS_TC_%d, Device ID should be 0x%x, but 0x%x\n", |
| 337 | i, (0x83 + i), data); |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | static void disable_all_sensing_points(struct lvts_data *lvts_data) |
| 342 | { |
| 343 | unsigned int i; |
| 344 | void __iomem *base; |
| 345 | |
| 346 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 347 | base = GET_BASE_ADDR(i); |
| 348 | writel(DISABLE_SENSING_POINT, LVTSMONCTL0_0 + base); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | static void enable_all_sensing_points(struct lvts_data *lvts_data) |
| 353 | { |
| 354 | struct device *dev = lvts_data->dev; |
| 355 | struct tc_settings *tc = lvts_data->tc; |
| 356 | unsigned int i, num; |
| 357 | void __iomem *base; |
| 358 | |
| 359 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 360 | base = GET_BASE_ADDR(i); |
| 361 | num = tc[i].num_sensor; |
| 362 | |
| 363 | if (num > ALL_SENSING_POINTS) { |
| 364 | dev_err(dev, |
| 365 | "%s, LVTS%d, illegal number of sensors: %d\n", |
| 366 | __func__, i, tc[i].num_sensor); |
| 367 | continue; |
| 368 | } |
| 369 | |
| 370 | writel(ENABLE_SENSING_POINT(num), LVTSMONCTL0_0 + base); |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | static void set_polling_speed(struct lvts_data *lvts_data, int tc_id) |
| 375 | { |
| 376 | struct device *dev = lvts_data->dev; |
| 377 | struct tc_settings *tc = lvts_data->tc; |
| 378 | unsigned int lvts_mon_ctl_1, lvts_mon_ctl_2; |
| 379 | void __iomem *base; |
| 380 | |
| 381 | base = GET_BASE_ADDR(tc_id); |
| 382 | |
| 383 | lvts_mon_ctl_1 = ((tc[tc_id].tc_speed.group_interval_delay << 20) & |
| 384 | GENMASK(29, 20)) | |
| 385 | (tc[tc_id].tc_speed.period_unit & GENMASK(9, 0)); |
| 386 | lvts_mon_ctl_2 = |
| 387 | ((tc[tc_id].tc_speed.filter_interval_delay << 16) & |
| 388 | GENMASK(25, 16)) | |
| 389 | (tc[tc_id].tc_speed.sensor_interval_delay & GENMASK(9, 0)); |
| 390 | /* |
| 391 | * Clock source of LVTS thermal controller is 26MHz. |
| 392 | * Period unit is a base for all interval delays |
| 393 | * All interval delays must multiply it to convert a setting to time. |
| 394 | * |
| 395 | * Filter interval delay: |
| 396 | * A delay between two samples of the same sensor |
| 397 | * |
| 398 | * Sensor interval delay: |
| 399 | * A delay between two samples of differnet sensors |
| 400 | * |
| 401 | * Group interval delay: |
| 402 | * A delay between different rounds. |
| 403 | * |
| 404 | * For example: |
| 405 | * If Period unit = C, filter delay = 1, sensor delay = 2, |
| 406 | * group delay = 1, and two sensors, TS1 and TS2, are in a LVTS |
| 407 | * thermal controller and then |
| 408 | * Period unit = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us |
| 409 | * Filter interval delay = 1 * Period unit = 118.149us |
| 410 | * Sensor interval delay = 2 * Period unit = 236.298us |
| 411 | * Group interval delay = 1 * Period unit = 118.149us |
| 412 | * |
| 413 | * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... |
| 414 | * <--> Filter interval delay |
| 415 | * <--> Sensor interval delay |
| 416 | * <--> Group interval delay |
| 417 | */ |
| 418 | writel(lvts_mon_ctl_1, LVTSMONCTL1_0 + base); |
| 419 | writel(lvts_mon_ctl_2, LVTSMONCTL2_0 + base); |
| 420 | |
| 421 | dev_info(dev, "%s %d, LVTSMONCTL1_0= 0x%x,LVTSMONCTL2_0= 0x%x\n", |
| 422 | __func__, tc_id, readl(LVTSMONCTL1_0 + base), |
| 423 | readl(LVTSMONCTL2_0 + base)); |
| 424 | } |
| 425 | |
| 426 | static void set_hw_filter(struct lvts_data *lvts_data, int tc_id) |
| 427 | { |
| 428 | struct device *dev = lvts_data->dev; |
| 429 | struct tc_settings *tc = lvts_data->tc; |
| 430 | unsigned int option; |
| 431 | void __iomem *base; |
| 432 | |
| 433 | base = GET_BASE_ADDR(tc_id); |
| 434 | option = tc[tc_id].hw_filter & 0x7; |
| 435 | /* hw filter |
| 436 | * 000: Get one sample |
| 437 | * 001: Get 2 samples and average them |
| 438 | * 010: Get 4 samples, drop max and min, then average the rest of 2 |
| 439 | * samples |
| 440 | * 011: Get 6 samples, drop max and min, then average the rest of 4 |
| 441 | * samples |
| 442 | * 100: Get 10 samples, drop max and min, then average the rest of 8 |
| 443 | * samples |
| 444 | * 101: Get 18 samples, drop max and min, then average the rest of 16 |
| 445 | * samples |
| 446 | */ |
| 447 | option = (option << 9) | (option << 6) | (option << 3) | option; |
| 448 | |
| 449 | writel(option, LVTSMSRCTL0_0 + base); |
| 450 | dev_info(dev, "%s %d, LVTSMSRCTL0_0= 0x%x\n", __func__, tc_id, |
| 451 | readl(LVTSMSRCTL0_0 + base)); |
| 452 | } |
| 453 | |
| 454 | static int get_dominator_index(struct lvts_data *lvts_data, int tc_id) |
| 455 | { |
| 456 | struct device *dev = lvts_data->dev; |
| 457 | struct tc_settings *tc = lvts_data->tc; |
| 458 | int d_index; |
| 459 | |
| 460 | if (tc[tc_id].dominator_sensing_point == ALL_SENSING_POINTS) { |
| 461 | d_index = ALL_SENSING_POINTS; |
| 462 | } else if (tc[tc_id].dominator_sensing_point < tc[tc_id].num_sensor) { |
| 463 | d_index = tc[tc_id].dominator_sensing_point; |
| 464 | } else { |
| 465 | dev_err(dev, |
| 466 | "Error: LVTS%d, dominator_sensing_point= %d should smaller than num_sensor= %d\n", |
| 467 | tc_id, tc[tc_id].dominator_sensing_point, |
| 468 | tc[tc_id].num_sensor); |
| 469 | |
| 470 | dev_err(dev, |
| 471 | "Use the sensing point 0 as the dominated sensor\n"); |
| 472 | d_index = SENSING_POINT0; |
| 473 | } |
| 474 | |
| 475 | return d_index; |
| 476 | } |
| 477 | |
| 478 | static void disable_hw_reboot_interrupt(struct lvts_data *lvts_data, int tc_id) |
| 479 | { |
| 480 | unsigned int temp; |
| 481 | void __iomem *base; |
| 482 | |
| 483 | base = GET_BASE_ADDR(tc_id); |
| 484 | |
| 485 | /* LVTS thermal controller has two interrupts for thermal HW reboot |
| 486 | * One is for AP SW and the other is for RGU |
| 487 | * The interrupt of AP SW can turn off by a bit of a register, but |
| 488 | * the other for RGU cannot. |
| 489 | * To prevent rebooting device accidentally, we are going to add |
| 490 | * a huge offset to LVTS and make LVTS always report extremely low |
| 491 | * temperature. |
| 492 | */ |
| 493 | |
| 494 | /* After adding the huge offset 0x3FFF, LVTS alawys adds the |
| 495 | * offset to MSR_RAW. |
| 496 | * When MSR_RAW is larger, SW will convert lower temperature/ |
| 497 | */ |
| 498 | temp = readl(LVTSPROTCTL_0 + base); |
| 499 | writel(temp | 0x3FFF, LVTSPROTCTL_0 + base); |
| 500 | |
| 501 | /* Disable the interrupt of AP SW */ |
| 502 | temp = readl(LVTSMONINT_0 + base); |
| 503 | writel(temp & ~(STAGE3_INT_EN), LVTSMONINT_0 + base); |
| 504 | } |
| 505 | |
| 506 | static void enable_hw_reboot_interrupt(struct lvts_data *lvts_data, int tc_id) |
| 507 | { |
| 508 | unsigned int temp; |
| 509 | void __iomem *base; |
| 510 | |
| 511 | base = GET_BASE_ADDR(tc_id); |
| 512 | |
| 513 | /* Enable the interrupt of AP SW */ |
| 514 | temp = readl(LVTSMONINT_0 + base); |
| 515 | writel(temp | STAGE3_INT_EN, LVTSMONINT_0 + base); |
| 516 | /* Clear the offset */ |
| 517 | temp = readl(LVTSPROTCTL_0 + base); |
| 518 | writel(temp & ~PROTOFFSET, LVTSPROTCTL_0 + base); |
| 519 | } |
| 520 | |
| 521 | static void set_tc_hw_reboot_threshold(struct lvts_data *lvts_data, |
| 522 | int trip_point, int tc_id) |
| 523 | { |
| 524 | struct device *dev = lvts_data->dev; |
| 525 | unsigned int msr_raw, temp, config, d_index; |
| 526 | void __iomem *base; |
| 527 | |
| 528 | base = GET_BASE_ADDR(tc_id); |
| 529 | d_index = get_dominator_index(lvts_data, tc_id); |
| 530 | |
| 531 | dev_info(dev, "%s: LVTS%d, the dominator sensing point= %d\n", __func__, |
| 532 | tc_id, d_index); |
| 533 | |
| 534 | disable_hw_reboot_interrupt(lvts_data, tc_id); |
| 535 | |
| 536 | temp = readl(LVTSPROTCTL_0 + base); |
| 537 | if (d_index == ALL_SENSING_POINTS) { |
| 538 | /* Maximum of 4 sensing points */ |
| 539 | config = (0x1 << 16); |
| 540 | writel(config | temp, LVTSPROTCTL_0 + base); |
| 541 | } else { |
| 542 | /* Select protection sensor */ |
| 543 | config = ((d_index << 2) + 0x2) << 16; |
| 544 | writel(config | temp, LVTSPROTCTL_0 + base); |
| 545 | } |
| 546 | |
| 547 | msr_raw = lvts_temp_to_raw(&lvts_data->coeff, trip_point); |
| 548 | writel(msr_raw, LVTSPROTTC_0 + base); |
| 549 | |
| 550 | enable_hw_reboot_interrupt(lvts_data, tc_id); |
| 551 | } |
| 552 | |
| 553 | static void set_all_tc_hw_reboot(struct lvts_data *lvts_data) |
| 554 | { |
| 555 | struct tc_settings *tc = lvts_data->tc; |
| 556 | int i, trip_point; |
| 557 | |
| 558 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 559 | trip_point = tc[i].hw_reboot_trip_point; |
| 560 | |
| 561 | if (tc[i].num_sensor == 0) |
| 562 | continue; |
| 563 | |
| 564 | if (trip_point == DISABLE_THERMAL_HW_REBOOT) |
| 565 | continue; |
| 566 | |
| 567 | set_tc_hw_reboot_threshold(lvts_data, trip_point, i); |
| 568 | } |
| 569 | } |
| 570 | |
| 571 | static int lvts_init(struct lvts_data *lvts_data) |
| 572 | { |
| 573 | struct platform_ops *ops = &lvts_data->ops; |
| 574 | struct device *dev = lvts_data->dev; |
| 575 | int ret; |
| 576 | |
| 577 | ret = clk_prepare_enable(lvts_data->clk); |
| 578 | if (ret) { |
| 579 | dev_err(dev, |
| 580 | "Error: Failed to enable lvts controller clock: %d\n", |
| 581 | ret); |
| 582 | return ret; |
| 583 | } |
| 584 | |
| 585 | if (lvts_data->feature_bitmap & FEATURE_RESET) |
| 586 | lvts_reset(lvts_data); |
| 587 | |
| 588 | device_identification(lvts_data); |
| 589 | if (ops->device_enable_and_init) |
| 590 | ops->device_enable_and_init(lvts_data); |
| 591 | |
| 592 | if (IS_ENABLE(FEATURE_DEVICE_AUTO_RCK)) { |
| 593 | if (ops->device_enable_auto_rck) |
| 594 | ops->device_enable_auto_rck(lvts_data); |
| 595 | } else { |
| 596 | if (ops->device_read_count_rc_n) |
| 597 | ops->device_read_count_rc_n(lvts_data); |
| 598 | } |
| 599 | |
| 600 | if (ops->set_cal_data) |
| 601 | ops->set_cal_data(lvts_data); |
| 602 | |
| 603 | disable_all_sensing_points(lvts_data); |
| 604 | wait_all_tc_sensing_point_idle(lvts_data); |
| 605 | if (ops->init_controller) |
| 606 | ops->init_controller(lvts_data); |
| 607 | enable_all_sensing_points(lvts_data); |
| 608 | |
| 609 | set_all_tc_hw_reboot(lvts_data); |
| 610 | |
| 611 | return 0; |
| 612 | } |
| 613 | |
| 614 | static int prepare_calibration_data(struct lvts_data *lvts_data) |
| 615 | { |
| 616 | struct device *dev = lvts_data->dev; |
| 617 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 618 | struct platform_ops *ops = &lvts_data->ops; |
| 619 | int i, offset, size; |
| 620 | char buffer[512]; |
| 621 | |
| 622 | cal_data->count_r = |
| 623 | devm_kcalloc(dev, lvts_data->num_sensor, |
| 624 | sizeof(*cal_data->count_r), GFP_KERNEL); |
| 625 | if (!cal_data->count_r) |
| 626 | return -ENOMEM; |
| 627 | |
| 628 | cal_data->count_rc = |
| 629 | devm_kcalloc(dev, lvts_data->num_sensor, |
| 630 | sizeof(*cal_data->count_rc), GFP_KERNEL); |
| 631 | if (!cal_data->count_rc) |
| 632 | return -ENOMEM; |
| 633 | |
| 634 | if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse) |
| 635 | ops->efuse_to_cal_data(lvts_data); |
| 636 | |
| 637 | if (cal_data->golden_temp == 0 || |
| 638 | cal_data->golden_temp > GOLDEN_TEMP_MAX) |
| 639 | cal_data->use_fake_efuse = 1; |
| 640 | |
| 641 | if (cal_data->use_fake_efuse) { |
| 642 | /* It means all efuse data are equal to 0 */ |
| 643 | dev_err(dev, |
| 644 | "[lvts_cal] This sample is not calibrated, fake !!\n"); |
| 645 | |
| 646 | cal_data->golden_temp = cal_data->default_golden_temp; |
| 647 | for (i = 0; i < lvts_data->num_sensor; i++) { |
| 648 | cal_data->count_r[i] = cal_data->default_count_r; |
| 649 | cal_data->count_rc[i] = cal_data->default_count_rc; |
| 650 | } |
| 651 | } |
| 652 | |
| 653 | lvts_data->coeff.golden_temp = cal_data->golden_temp; |
| 654 | |
| 655 | dev_info(dev, "[lvts_cal] golden_temp = %d\n", cal_data->golden_temp); |
| 656 | |
| 657 | size = sizeof(buffer); |
| 658 | offset = snprintf(buffer, size, "[lvts_cal] num:g_count:g_count_rc "); |
| 659 | for (i = 0; i < lvts_data->num_sensor; i++) |
| 660 | offset += |
| 661 | snprintf(buffer + offset, size - offset, "%d:%d:%d ", i, |
| 662 | cal_data->count_r[i], cal_data->count_rc[i]); |
| 663 | |
| 664 | buffer[offset] = '\0'; |
| 665 | dev_info(dev, "%s\n", buffer); |
| 666 | |
| 667 | return 0; |
| 668 | } |
| 669 | |
| 670 | static int get_calibration_data(struct lvts_data *lvts_data) |
| 671 | { |
| 672 | struct device *dev = lvts_data->dev; |
| 673 | char cell_name[8]; |
| 674 | struct nvmem_cell *cell; |
| 675 | u32 *buf; |
| 676 | size_t len; |
| 677 | int i, j, index = 0; |
| 678 | |
| 679 | lvts_data->efuse = devm_kcalloc(dev, lvts_data->num_efuse_addr, |
| 680 | sizeof(*lvts_data->efuse), GFP_KERNEL); |
| 681 | if (!lvts_data->efuse) |
| 682 | return -ENOMEM; |
| 683 | |
| 684 | for (i = 0; i < lvts_data->num_efuse_block; i++) { |
| 685 | snprintf(cell_name, sizeof(cell_name), "e_data%d", i + 1); |
| 686 | cell = nvmem_cell_get(dev, cell_name); |
| 687 | if (IS_ERR(cell)) { |
| 688 | dev_err(dev, "Error: Failed to get nvmem cell %s\n", |
| 689 | cell_name); |
| 690 | return PTR_ERR(cell); |
| 691 | } |
| 692 | |
| 693 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 694 | nvmem_cell_put(cell); |
| 695 | |
| 696 | if (IS_ERR(buf)) |
| 697 | return PTR_ERR(buf); |
| 698 | |
| 699 | for (j = 0; j < (len / sizeof(u32)); j++) { |
| 700 | if (index >= lvts_data->num_efuse_addr) { |
| 701 | dev_err(dev, |
| 702 | "Array efuse is going to overflow"); |
| 703 | kfree(buf); |
| 704 | return -EINVAL; |
| 705 | } |
| 706 | |
| 707 | lvts_data->efuse[index] = buf[j]; |
| 708 | index++; |
| 709 | } |
| 710 | |
| 711 | kfree(buf); |
| 712 | } |
| 713 | |
| 714 | return 0; |
| 715 | } |
| 716 | |
| 717 | static int of_update_lvts_data(struct lvts_data *lvts_data, |
| 718 | struct platform_device *pdev) |
| 719 | { |
| 720 | struct device *dev = lvts_data->dev; |
| 721 | struct power_domain *domain; |
| 722 | struct resource *res; |
| 723 | unsigned int i; |
| 724 | int ret; |
| 725 | |
| 726 | lvts_data->clk = devm_clk_get(dev, "lvts_clk"); |
| 727 | if (IS_ERR(lvts_data->clk)) |
| 728 | return PTR_ERR(lvts_data->clk); |
| 729 | |
| 730 | domain = devm_kcalloc(dev, lvts_data->num_domain, sizeof(*domain), |
| 731 | GFP_KERNEL); |
| 732 | if (!domain) |
| 733 | return -ENOMEM; |
| 734 | |
| 735 | for (i = 0; i < lvts_data->num_domain; i++) { |
| 736 | /* Get base address */ |
| 737 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
| 738 | if (!res) { |
| 739 | dev_err(dev, "No IO resource, index %d\n", i); |
| 740 | return -ENXIO; |
| 741 | } |
| 742 | |
| 743 | domain[i].base = devm_ioremap_resource(dev, res); |
| 744 | if (IS_ERR(domain[i].base)) { |
| 745 | dev_err(dev, "Failed to remap io, index %d\n", i); |
| 746 | return PTR_ERR(domain[i].base); |
| 747 | } |
| 748 | |
| 749 | /* Get interrupt number */ |
| 750 | if (lvts_data->feature_bitmap & FEATURE_IRQ) { |
| 751 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); |
| 752 | if (!res) { |
| 753 | dev_err(dev, "No irq resource, index %d\n", i); |
| 754 | return -EINVAL; |
| 755 | } |
| 756 | domain[i].irq_num = res->start; |
| 757 | } |
| 758 | |
| 759 | /* Get reset control */ |
| 760 | if (lvts_data->feature_bitmap & FEATURE_RESET) { |
| 761 | domain[i].reset = |
| 762 | devm_reset_control_get_by_index(dev, i); |
| 763 | if (IS_ERR(domain[i].reset)) { |
| 764 | dev_err(dev, "Failed to get, index %d\n", i); |
| 765 | return PTR_ERR(domain[i].reset); |
| 766 | } |
| 767 | } |
| 768 | } |
| 769 | |
| 770 | lvts_data->domain = domain; |
| 771 | |
| 772 | lvts_data->sen_data = |
| 773 | devm_kcalloc(dev, lvts_data->num_sensor, |
| 774 | sizeof(*lvts_data->sen_data), GFP_KERNEL); |
| 775 | if (!lvts_data->sen_data) |
| 776 | return -ENOMEM; |
| 777 | |
| 778 | ret = get_calibration_data(lvts_data); |
| 779 | if (ret) |
| 780 | lvts_data->cal_data.use_fake_efuse = 1; |
| 781 | ret = prepare_calibration_data(lvts_data); |
| 782 | if (ret) |
| 783 | return ret; |
| 784 | |
| 785 | return 0; |
| 786 | } |
| 787 | |
| 788 | static void lvts_device_close(struct lvts_data *lvts_data) |
| 789 | { |
| 790 | unsigned int i; |
| 791 | void __iomem *base; |
| 792 | |
| 793 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 794 | base = GET_BASE_ADDR(i); |
| 795 | lvts_write_device(lvts_data, RESET_ALL_DEVICES, i); |
| 796 | writel(DISABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); |
| 797 | } |
| 798 | } |
| 799 | |
| 800 | static void lvts_close(struct lvts_data *lvts_data) |
| 801 | { |
| 802 | disable_all_sensing_points(lvts_data); |
| 803 | wait_all_tc_sensing_point_idle(lvts_data); |
| 804 | lvts_device_close(lvts_data); |
| 805 | clk_disable_unprepare(lvts_data->clk); |
| 806 | } |
| 807 | |
| 808 | static void tc_irq_handler(struct lvts_data *lvts_data, int tc_id) |
| 809 | { |
| 810 | struct device *dev = lvts_data->dev; |
| 811 | unsigned int ret = 0; |
| 812 | void __iomem *base; |
| 813 | |
| 814 | base = GET_BASE_ADDR(tc_id); |
| 815 | |
| 816 | ret = readl(LVTSMONINTSTS_0 + base); |
| 817 | /* Write back to clear interrupt status */ |
| 818 | writel(ret, LVTSMONINTSTS_0 + base); |
| 819 | |
| 820 | dev_info( |
| 821 | dev, |
| 822 | "[Thermal IRQ] LVTS thermal controller %d, LVTSMONINTSTS=0x%08x\n", |
| 823 | tc_id, ret); |
| 824 | |
| 825 | if (ret & THERMAL_PROTECTION_STAGE_3) |
| 826 | dev_info( |
| 827 | dev, |
| 828 | "[Thermal IRQ]: Thermal protection stage 3 interrupt triggered\n"); |
| 829 | } |
| 830 | |
| 831 | static irqreturn_t irq_handler(int irq, void *dev_id) |
| 832 | { |
| 833 | struct lvts_data *lvts_data = (struct lvts_data *)dev_id; |
| 834 | struct device *dev = lvts_data->dev; |
| 835 | struct tc_settings *tc = lvts_data->tc; |
| 836 | unsigned int i, *irq_bitmap; |
| 837 | void __iomem *base; |
| 838 | |
| 839 | irq_bitmap = |
| 840 | kcalloc(lvts_data->num_domain, sizeof(*irq_bitmap), GFP_ATOMIC); |
| 841 | |
| 842 | if (!irq_bitmap) |
| 843 | return IRQ_NONE; |
| 844 | |
| 845 | for (i = 0; i < lvts_data->num_domain; i++) { |
| 846 | base = lvts_data->domain[i].base; |
| 847 | irq_bitmap[i] = readl(THERMINTST + base); |
| 848 | dev_info(dev, "%s : THERMINTST = 0x%x\n", __func__, |
| 849 | irq_bitmap[i]); |
| 850 | } |
| 851 | |
| 852 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 853 | if ((irq_bitmap[tc[i].domain_index] & tc[i].irq_bit) == 0) |
| 854 | tc_irq_handler(lvts_data, i); |
| 855 | } |
| 856 | |
| 857 | kfree(irq_bitmap); |
| 858 | |
| 859 | return IRQ_HANDLED; |
| 860 | } |
| 861 | |
| 862 | static int lvts_register_irq_handler(struct lvts_data *lvts_data) |
| 863 | { |
| 864 | struct device *dev = lvts_data->dev; |
| 865 | unsigned int i; |
| 866 | int ret; |
| 867 | |
| 868 | for (i = 0; i < lvts_data->num_domain; i++) { |
| 869 | ret = devm_request_irq(dev, lvts_data->domain[i].irq_num, |
| 870 | irq_handler, IRQF_TRIGGER_HIGH, |
| 871 | "mtk_lvts", lvts_data); |
| 872 | |
| 873 | if (ret) { |
| 874 | dev_err(dev, |
| 875 | "Failed to register LVTS IRQ, ret %d, domain %d irq_num %d\n", |
| 876 | ret, i, lvts_data->domain[i].irq_num); |
| 877 | lvts_close(lvts_data); |
| 878 | return ret; |
| 879 | } |
| 880 | } |
| 881 | |
| 882 | return 0; |
| 883 | } |
| 884 | |
| 885 | static int lvts_register_thermal_zones(struct lvts_data *lvts_data) |
| 886 | { |
| 887 | struct device *dev = lvts_data->dev; |
| 888 | struct thermal_zone_device *tzdev; |
| 889 | struct soc_temp_tz *lvts_tz; |
| 890 | int i, ret; |
| 891 | |
| 892 | for (i = 0; i < lvts_data->num_sensor + 1; i++) { |
| 893 | lvts_tz = devm_kzalloc(dev, sizeof(*lvts_tz), GFP_KERNEL); |
| 894 | if (!lvts_tz) { |
| 895 | lvts_close(lvts_data); |
| 896 | return -ENOMEM; |
| 897 | } |
| 898 | |
| 899 | lvts_tz->id = i; |
| 900 | lvts_tz->lvts_data = lvts_data; |
| 901 | |
| 902 | tzdev = devm_thermal_zone_of_sensor_register( |
| 903 | dev, lvts_tz->id, lvts_tz, &soc_temp_lvts_ops); |
| 904 | |
| 905 | if (IS_ERR(tzdev)) { |
| 906 | if (lvts_tz->id != 0) |
| 907 | return 0; |
| 908 | |
| 909 | ret = PTR_ERR(tzdev); |
| 910 | lvts_close(lvts_data); |
| 911 | return ret; |
| 912 | } |
| 913 | } |
| 914 | |
| 915 | return 0; |
| 916 | } |
| 917 | |
| 918 | static int lvts_probe(struct platform_device *pdev) |
| 919 | { |
| 920 | struct device *dev = &pdev->dev; |
| 921 | struct lvts_data *lvts_data; |
| 922 | int ret; |
| 923 | |
| 924 | lvts_data = (struct lvts_data *)of_device_get_match_data(dev); |
| 925 | |
| 926 | if (!lvts_data) { |
| 927 | dev_err(dev, "Error: Failed to get lvts platform data\n"); |
| 928 | return -ENODATA; |
| 929 | } |
| 930 | |
| 931 | lvts_data->dev = &pdev->dev; |
| 932 | |
| 933 | ret = of_update_lvts_data(lvts_data, pdev); |
| 934 | if (ret) |
| 935 | return ret; |
| 936 | |
| 937 | platform_set_drvdata(pdev, lvts_data); |
| 938 | |
| 939 | ret = lvts_init(lvts_data); |
| 940 | if (ret) |
| 941 | return ret; |
| 942 | |
| 943 | if (lvts_data->feature_bitmap & FEATURE_IRQ) { |
| 944 | ret = lvts_register_irq_handler(lvts_data); |
| 945 | if (ret) |
| 946 | return ret; |
| 947 | } |
| 948 | |
| 949 | ret = lvts_register_thermal_zones(lvts_data); |
| 950 | if (ret) |
| 951 | return ret; |
| 952 | |
| 953 | return 0; |
| 954 | } |
| 955 | |
| 956 | static int lvts_remove(struct platform_device *pdev) |
| 957 | { |
| 958 | struct lvts_data *lvts_data; |
| 959 | |
| 960 | lvts_data = (struct lvts_data *)platform_get_drvdata(pdev); |
| 961 | |
| 962 | lvts_close(lvts_data); |
| 963 | |
| 964 | return 0; |
| 965 | } |
| 966 | |
| 967 | static int lvts_suspend(struct platform_device *pdev, pm_message_t state) |
| 968 | { |
| 969 | struct lvts_data *lvts_data; |
| 970 | |
| 971 | lvts_data = (struct lvts_data *)platform_get_drvdata(pdev); |
| 972 | |
| 973 | lvts_close(lvts_data); |
| 974 | |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | static int lvts_resume(struct platform_device *pdev) |
| 979 | { |
| 980 | int ret; |
| 981 | struct lvts_data *lvts_data; |
| 982 | |
| 983 | lvts_data = (struct lvts_data *)platform_get_drvdata(pdev); |
| 984 | |
| 985 | ret = lvts_init(lvts_data); |
| 986 | if (ret) |
| 987 | return ret; |
| 988 | |
| 989 | return 0; |
| 990 | } |
| 991 | |
| 992 | /* |
| 993 | * LVTS v4 common code |
| 994 | */ |
| 995 | |
| 996 | static void device_enable_and_init_v4(struct lvts_data *lvts_data) |
| 997 | { |
| 998 | unsigned int i; |
| 999 | |
| 1000 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 1001 | lvts_write_device(lvts_data, STOP_COUNTING_V4, i); |
| 1002 | lvts_write_device(lvts_data, SET_RG_TSFM_LPDLY_V4, i); |
| 1003 | lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US1_V4, i); |
| 1004 | lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US2_V4, i); |
| 1005 | lvts_write_device(lvts_data, TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4, |
| 1006 | i); |
| 1007 | lvts_write_device(lvts_data, TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4, |
| 1008 | i); |
| 1009 | lvts_write_device(lvts_data, SET_TS_RSV_V4, i); |
| 1010 | lvts_write_device(lvts_data, SET_TS_EN_V4, i); |
| 1011 | lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST1_V4, i); |
| 1012 | lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST2_V4, i); |
| 1013 | } |
| 1014 | |
| 1015 | lvts_data->counting_window_us = 20; |
| 1016 | } |
| 1017 | |
| 1018 | static void device_enable_auto_rck_v4(struct lvts_data *lvts_data) |
| 1019 | { |
| 1020 | unsigned int i; |
| 1021 | |
| 1022 | for (i = 0; i < lvts_data->num_tc; i++) |
| 1023 | lvts_write_device(lvts_data, SET_LVTS_AUTO_RCK_V4, i); |
| 1024 | } |
| 1025 | |
| 1026 | static int device_read_count_rc_n_v4(struct lvts_data *lvts_data) |
| 1027 | { |
| 1028 | /* Resistor-Capacitor Calibration */ |
| 1029 | /* count_RC_N: count RC now */ |
| 1030 | struct device *dev = lvts_data->dev; |
| 1031 | struct tc_settings *tc = lvts_data->tc; |
| 1032 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 1033 | unsigned int offset, size, s_index, data; |
| 1034 | void __iomem *base; |
| 1035 | int ret, i, j; |
| 1036 | char buffer[512]; |
| 1037 | |
| 1038 | cal_data->count_rc_now = |
| 1039 | devm_kcalloc(dev, lvts_data->num_sensor, |
| 1040 | sizeof(*cal_data->count_rc_now), GFP_KERNEL); |
| 1041 | if (!cal_data->count_rc_now) |
| 1042 | return -ENOMEM; |
| 1043 | |
| 1044 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 1045 | base = GET_BASE_ADDR(i); |
| 1046 | for (j = 0; j < tc[i].num_sensor; j++) { |
| 1047 | s_index = tc[i].sensor_map[j]; |
| 1048 | |
| 1049 | lvts_write_device(lvts_data, SELECT_SENSOR_RCK_V4(j), |
| 1050 | i); |
| 1051 | lvts_write_device(lvts_data, SET_DEVICE_SINGLE_MODE_V4, |
| 1052 | i); |
| 1053 | usleep_range(10, 20); |
| 1054 | |
| 1055 | lvts_write_device(lvts_data, KICK_OFF_RCK_COUNTING_V4, |
| 1056 | i); |
| 1057 | usleep_range(30, 40); |
| 1058 | |
| 1059 | ret = readl_poll_timeout( |
| 1060 | LVTS_CONFIG_0 + base, data, |
| 1061 | !(data & DEVICE_SENSING_STATUS), 2, 200); |
| 1062 | |
| 1063 | data = lvts_read_device(lvts_data, 0x00, i); |
| 1064 | |
| 1065 | cal_data->count_rc_now[s_index] = |
| 1066 | (data & GENMASK(23, 0)); |
| 1067 | } |
| 1068 | |
| 1069 | /* Recover Setting for Normal Access on |
| 1070 | * temperature fetch |
| 1071 | */ |
| 1072 | lvts_write_device(lvts_data, SET_SENSOR_NO_RCK_V4, i); |
| 1073 | lvts_write_device(lvts_data, |
| 1074 | SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); |
| 1075 | } |
| 1076 | |
| 1077 | size = sizeof(buffer); |
| 1078 | offset = snprintf(buffer, size, "[COUNT_RC_NOW] "); |
| 1079 | for (i = 0; i < lvts_data->num_sensor; i++) |
| 1080 | offset += snprintf(buffer + offset, size - offset, "%d:%d ", i, |
| 1081 | cal_data->count_rc_now[i]); |
| 1082 | |
| 1083 | buffer[offset] = '\0'; |
| 1084 | dev_info(dev, "%s\n", buffer); |
| 1085 | |
| 1086 | return 0; |
| 1087 | } |
| 1088 | |
| 1089 | static void set_calibration_data_v4(struct lvts_data *lvts_data) |
| 1090 | { |
| 1091 | struct tc_settings *tc = lvts_data->tc; |
| 1092 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 1093 | unsigned int i, j, s_index, e_data; |
| 1094 | void __iomem *base; |
| 1095 | |
| 1096 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 1097 | base = GET_BASE_ADDR(i); |
| 1098 | |
| 1099 | for (j = 0; j < tc[i].num_sensor; j++) { |
| 1100 | s_index = tc[i].sensor_map[j]; |
| 1101 | if (IS_ENABLE(FEATURE_DEVICE_AUTO_RCK)) |
| 1102 | e_data = cal_data->count_r[s_index]; |
| 1103 | else |
| 1104 | e_data = (((unsigned long long)cal_data |
| 1105 | ->count_rc_now[s_index]) * |
| 1106 | cal_data->count_r[s_index]) >> |
| 1107 | 14; |
| 1108 | |
| 1109 | writel(e_data, LVTSEDATA00_0 + base + 0x4 * j); |
| 1110 | } |
| 1111 | } |
| 1112 | } |
| 1113 | |
| 1114 | static void init_controller_v4(struct lvts_data *lvts_data) |
| 1115 | { |
| 1116 | struct device *dev = lvts_data->dev; |
| 1117 | unsigned int i; |
| 1118 | void __iomem *base; |
| 1119 | |
| 1120 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 1121 | base = GET_BASE_ADDR(i); |
| 1122 | |
| 1123 | lvts_write_device(lvts_data, |
| 1124 | SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); |
| 1125 | |
| 1126 | writel(SET_SENSOR_INDEX, LVTSTSSEL_0 + base); |
| 1127 | writel(SET_CALC_SCALE_RULES, LVTSCALSCALE_0 + base); |
| 1128 | |
| 1129 | set_polling_speed(lvts_data, i); |
| 1130 | set_hw_filter(lvts_data, i); |
| 1131 | |
| 1132 | dev_info(dev, |
| 1133 | "lvts%d: read all %d sensors in %d us, one in %d us\n", |
| 1134 | i, GET_TC_SENSOR_NUM(i), GROUP_LATENCY_US(i), |
| 1135 | SENSOR_LATENCY_US(i)); |
| 1136 | } |
| 1137 | } |
| 1138 | |
| 1139 | /* |
| 1140 | * LVTS v5 common code |
| 1141 | */ |
| 1142 | static void device_enable_and_init_v5(struct lvts_data *lvts_data) |
| 1143 | { |
| 1144 | unsigned int i; |
| 1145 | |
| 1146 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 1147 | lvts_write_device(lvts_data, STOP_COUNTING_V5, i); |
| 1148 | lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US2_V5, i); |
| 1149 | lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US1_V5, i); |
| 1150 | lvts_write_device(lvts_data, SET_RG_TSFM_LPDLY_V5, i); |
| 1151 | lvts_write_device(lvts_data, TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V5, |
| 1152 | i); |
| 1153 | lvts_write_device(lvts_data, TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V5, |
| 1154 | i); |
| 1155 | lvts_write_device(lvts_data, SET_TS_RSV_V5, i); |
| 1156 | lvts_write_device(lvts_data, SET_TS_EN_V5, i); |
| 1157 | } |
| 1158 | |
| 1159 | lvts_data->counting_window_us = 20; |
| 1160 | } |
| 1161 | |
| 1162 | static int device_read_count_rc_n_v5(struct lvts_data *lvts_data) |
| 1163 | { |
| 1164 | /* Resistor-Capacitor Calibration */ |
| 1165 | /* count_RC_N: count RC now */ |
| 1166 | struct device *dev = lvts_data->dev; |
| 1167 | struct tc_settings *tc = lvts_data->tc; |
| 1168 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 1169 | unsigned int offset, size, s_index, data; |
| 1170 | void __iomem *base; |
| 1171 | int ret, i, j; |
| 1172 | char buffer[512]; |
| 1173 | |
| 1174 | cal_data->count_rc_now = |
| 1175 | devm_kcalloc(dev, lvts_data->num_sensor, |
| 1176 | sizeof(*cal_data->count_rc_now), GFP_KERNEL); |
| 1177 | if (!cal_data->count_rc_now) |
| 1178 | return -ENOMEM; |
| 1179 | |
| 1180 | for (i = 0; i < lvts_data->num_tc; i++) { |
| 1181 | base = GET_BASE_ADDR(i); |
| 1182 | lvts_write_device(lvts_data, SET_MANUAL_RCK_V5, i); |
| 1183 | |
| 1184 | for (j = 0; j < tc[i].num_sensor; j++) { |
| 1185 | s_index = tc[i].sensor_map[j]; |
| 1186 | |
| 1187 | lvts_write_device(lvts_data, SELECT_SENSOR_RCK_V5(j), |
| 1188 | i); |
| 1189 | lvts_write_device(lvts_data, SET_DEVICE_SINGLE_MODE_V5, |
| 1190 | i); |
| 1191 | lvts_write_device(lvts_data, |
| 1192 | SET_COUNTING_WINDOW_20US2_V5, i); |
| 1193 | lvts_write_device(lvts_data, |
| 1194 | SET_COUNTING_WINDOW_20US1_V5, i); |
| 1195 | lvts_write_device(lvts_data, KICK_OFF_RCK_COUNTING_V5, |
| 1196 | i); |
| 1197 | udelay(40); |
| 1198 | |
| 1199 | ret = readl_poll_timeout( |
| 1200 | LVTS_CONFIG_0 + base, data, |
| 1201 | !(data & DEVICE_SENSING_STATUS), 2, 200); |
| 1202 | if (ret) |
| 1203 | dev_err(dev, |
| 1204 | "Error: LVTS %d DEVICE_SENSING_STATUS didn't ready\n", |
| 1205 | i); |
| 1206 | |
| 1207 | data = lvts_read_device(lvts_data, 0x00, i); |
| 1208 | |
| 1209 | cal_data->count_rc_now[s_index] = |
| 1210 | (data & GENMASK(23, 0)); |
| 1211 | |
| 1212 | /* Recover Setting for Normal Access on |
| 1213 | * temperature fetch |
| 1214 | */ |
| 1215 | lvts_write_device(lvts_data, SET_SENSOR_NO_RCK_V5(j), |
| 1216 | i); |
| 1217 | lvts_write_device(lvts_data, |
| 1218 | SET_DEVICE_LOW_POWER_SINGLE_MODE_V5, |
| 1219 | i); |
| 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | size = sizeof(buffer); |
| 1224 | offset = snprintf(buffer, size, "[COUNT_RC_NOW] "); |
| 1225 | for (i = 0; i < lvts_data->num_sensor; i++) |
| 1226 | offset += snprintf(buffer + offset, size - offset, "%d:%d ", i, |
| 1227 | cal_data->count_rc_now[i]); |
| 1228 | |
| 1229 | buffer[offset] = '\0'; |
| 1230 | dev_info(dev, "%s\n", buffer); |
| 1231 | |
| 1232 | return 0; |
| 1233 | } |
| 1234 | |
| 1235 | /* |
| 1236 | * LVTS MT6873 |
| 1237 | */ |
| 1238 | |
| 1239 | #define MT6873_NUM_LVTS (ARRAY_SIZE(mt6873_tc_settings)) |
| 1240 | |
| 1241 | enum mt6873_lvts_domain { |
| 1242 | MT6873_AP_DOMAIN, |
| 1243 | MT6873_MCU_DOMAIN, |
| 1244 | MT6873_NUM_DOMAIN |
| 1245 | }; |
| 1246 | |
| 1247 | enum mt6873_lvts_sensor_enum { |
| 1248 | MT6873_TS1_0, |
| 1249 | MT6873_TS1_1, |
| 1250 | MT6873_TS2_0, |
| 1251 | MT6873_TS2_1, |
| 1252 | MT6873_TS3_0, |
| 1253 | MT6873_TS3_1, |
| 1254 | MT6873_TS3_2, |
| 1255 | MT6873_TS3_3, |
| 1256 | MT6873_TS4_0, |
| 1257 | MT6873_TS4_1, |
| 1258 | MT6873_TS5_0, |
| 1259 | MT6873_TS5_1, |
| 1260 | MT6873_TS6_0, |
| 1261 | MT6873_TS6_1, |
| 1262 | MT6873_TS7_0, |
| 1263 | MT6873_TS7_1, |
| 1264 | MT6873_TS7_2, |
| 1265 | MT6873_NUM_TS |
| 1266 | }; |
| 1267 | |
| 1268 | static void mt6873_efuse_to_cal_data(struct lvts_data *lvts_data) |
| 1269 | { |
| 1270 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 1271 | |
| 1272 | cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, 31, 24); |
| 1273 | cal_data->count_r[MT6873_TS1_0] = GET_CAL_DATA_BITMASK(1, 23, 0); |
| 1274 | cal_data->count_r[MT6873_TS1_1] = GET_CAL_DATA_BITMASK(2, 23, 0); |
| 1275 | cal_data->count_r[MT6873_TS2_0] = GET_CAL_DATA_BITMASK(3, 23, 0); |
| 1276 | cal_data->count_r[MT6873_TS2_1] = GET_CAL_DATA_BITMASK(4, 23, 0); |
| 1277 | cal_data->count_r[MT6873_TS3_0] = GET_CAL_DATA_BITMASK(5, 23, 0); |
| 1278 | cal_data->count_r[MT6873_TS3_1] = GET_CAL_DATA_BITMASK(6, 23, 0); |
| 1279 | cal_data->count_r[MT6873_TS3_2] = GET_CAL_DATA_BITMASK(7, 23, 0); |
| 1280 | cal_data->count_r[MT6873_TS3_3] = GET_CAL_DATA_BITMASK(8, 23, 0); |
| 1281 | cal_data->count_r[MT6873_TS4_0] = GET_CAL_DATA_BITMASK(9, 23, 0); |
| 1282 | cal_data->count_r[MT6873_TS4_1] = GET_CAL_DATA_BITMASK(10, 23, 0); |
| 1283 | cal_data->count_r[MT6873_TS5_0] = GET_CAL_DATA_BITMASK(11, 23, 0); |
| 1284 | cal_data->count_r[MT6873_TS5_1] = GET_CAL_DATA_BITMASK(12, 23, 0); |
| 1285 | cal_data->count_r[MT6873_TS6_0] = GET_CAL_DATA_BITMASK(13, 23, 0); |
| 1286 | cal_data->count_r[MT6873_TS6_1] = GET_CAL_DATA_BITMASK(14, 23, 0); |
| 1287 | cal_data->count_r[MT6873_TS7_0] = GET_CAL_DATA_BITMASK(15, 23, 0); |
| 1288 | cal_data->count_r[MT6873_TS7_1] = GET_CAL_DATA_BITMASK(16, 23, 0); |
| 1289 | cal_data->count_r[MT6873_TS7_2] = GET_CAL_DATA_BITMASK(17, 23, 0); |
| 1290 | |
| 1291 | cal_data->count_rc[MT6873_TS1_0] = GET_CAL_DATA_BITMASK(21, 23, 0); |
| 1292 | |
| 1293 | cal_data->count_rc[MT6873_TS2_0] = |
| 1294 | (GET_CAL_DATA_BITMASK(1, 31, 24) << 16) + |
| 1295 | (GET_CAL_DATA_BITMASK(2, 31, 24) << 8) + |
| 1296 | GET_CAL_DATA_BITMASK(3, 31, 24); |
| 1297 | |
| 1298 | cal_data->count_rc[MT6873_TS3_0] = |
| 1299 | (GET_CAL_DATA_BITMASK(4, 31, 24) << 16) + |
| 1300 | (GET_CAL_DATA_BITMASK(5, 31, 24) << 8) + |
| 1301 | GET_CAL_DATA_BITMASK(6, 31, 24); |
| 1302 | |
| 1303 | cal_data->count_rc[MT6873_TS4_0] = |
| 1304 | (GET_CAL_DATA_BITMASK(7, 31, 24) << 16) + |
| 1305 | (GET_CAL_DATA_BITMASK(8, 31, 24) << 8) + |
| 1306 | GET_CAL_DATA_BITMASK(9, 31, 24); |
| 1307 | |
| 1308 | cal_data->count_rc[MT6873_TS5_0] = |
| 1309 | (GET_CAL_DATA_BITMASK(10, 31, 24) << 16) + |
| 1310 | (GET_CAL_DATA_BITMASK(11, 31, 24) << 8) + |
| 1311 | GET_CAL_DATA_BITMASK(12, 31, 24); |
| 1312 | |
| 1313 | cal_data->count_rc[MT6873_TS6_0] = |
| 1314 | (GET_CAL_DATA_BITMASK(13, 31, 24) << 16) + |
| 1315 | (GET_CAL_DATA_BITMASK(14, 31, 24) << 8) + |
| 1316 | GET_CAL_DATA_BITMASK(15, 31, 24); |
| 1317 | |
| 1318 | cal_data->count_rc[MT6873_TS7_0] = |
| 1319 | (GET_CAL_DATA_BITMASK(16, 31, 24) << 16) + |
| 1320 | (GET_CAL_DATA_BITMASK(17, 31, 24) << 8) + |
| 1321 | GET_CAL_DATA_BITMASK(18, 31, 24); |
| 1322 | } |
| 1323 | |
| 1324 | static struct tc_settings mt6873_tc_settings[] = { |
| 1325 | [0] = { |
| 1326 | .domain_index = MT6873_MCU_DOMAIN, |
| 1327 | .addr_offset = 0x0, |
| 1328 | .num_sensor = 2, |
| 1329 | .sensor_map = {MT6873_TS1_0, MT6873_TS1_1}, |
| 1330 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1331 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1332 | .dominator_sensing_point = SENSING_POINT1, |
| 1333 | .hw_reboot_trip_point = 117000, |
| 1334 | .irq_bit = BIT(3), |
| 1335 | }, |
| 1336 | [1] = { |
| 1337 | .domain_index = MT6873_MCU_DOMAIN, |
| 1338 | .addr_offset = 0x100, |
| 1339 | .num_sensor = 2, |
| 1340 | .sensor_map = {MT6873_TS2_0, MT6873_TS2_1}, |
| 1341 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1342 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1343 | .dominator_sensing_point = SENSING_POINT0, |
| 1344 | .hw_reboot_trip_point = 117000, |
| 1345 | .irq_bit = BIT(4), |
| 1346 | }, |
| 1347 | [2] = { |
| 1348 | .domain_index = MT6873_MCU_DOMAIN, |
| 1349 | .addr_offset = 0x200, |
| 1350 | .num_sensor = 4, |
| 1351 | .sensor_map = {MT6873_TS3_0, MT6873_TS3_1, MT6873_TS3_2, |
| 1352 | MT6873_TS3_3}, |
| 1353 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1354 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1355 | .dominator_sensing_point = SENSING_POINT0, |
| 1356 | .hw_reboot_trip_point = 117000, |
| 1357 | .irq_bit = BIT(5), |
| 1358 | }, |
| 1359 | [3] = { |
| 1360 | .domain_index = MT6873_AP_DOMAIN, |
| 1361 | .addr_offset = 0x0, |
| 1362 | .num_sensor = 2, |
| 1363 | .sensor_map = {MT6873_TS4_0, MT6873_TS4_1}, |
| 1364 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1365 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1366 | .dominator_sensing_point = SENSING_POINT0, |
| 1367 | .hw_reboot_trip_point = 117000, |
| 1368 | .irq_bit = BIT(3), |
| 1369 | }, |
| 1370 | [4] = { |
| 1371 | .domain_index = MT6873_AP_DOMAIN, |
| 1372 | .addr_offset = 0x100, |
| 1373 | .num_sensor = 2, |
| 1374 | .sensor_map = {MT6873_TS5_0, MT6873_TS5_1}, |
| 1375 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1376 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1377 | .dominator_sensing_point = SENSING_POINT1, |
| 1378 | .hw_reboot_trip_point = 117000, |
| 1379 | .irq_bit = BIT(4), |
| 1380 | }, |
| 1381 | [5] = { |
| 1382 | .domain_index = MT6873_AP_DOMAIN, |
| 1383 | .addr_offset = 0x200, |
| 1384 | .num_sensor = 2, |
| 1385 | .sensor_map = {MT6873_TS6_0, MT6873_TS6_1}, |
| 1386 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1387 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1388 | .dominator_sensing_point = SENSING_POINT1, |
| 1389 | .hw_reboot_trip_point = 117000, |
| 1390 | .irq_bit = BIT(5), |
| 1391 | }, |
| 1392 | [6] = { |
| 1393 | .domain_index = MT6873_AP_DOMAIN, |
| 1394 | .addr_offset = 0x300, |
| 1395 | .num_sensor = 3, |
| 1396 | .sensor_map = {MT6873_TS7_0, MT6873_TS7_1, MT6873_TS7_2}, |
| 1397 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1398 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1399 | .dominator_sensing_point = SENSING_POINT2, |
| 1400 | .hw_reboot_trip_point = 117000, |
| 1401 | .irq_bit = BIT(6), |
| 1402 | } |
| 1403 | }; |
| 1404 | |
| 1405 | static struct lvts_data mt6873_lvts_data = { |
| 1406 | .num_domain = MT6873_NUM_DOMAIN, |
| 1407 | .num_tc = MT6873_NUM_LVTS, |
| 1408 | .tc = mt6873_tc_settings, |
| 1409 | .num_sensor = MT6873_NUM_TS, |
| 1410 | .ops = { |
| 1411 | .efuse_to_cal_data = mt6873_efuse_to_cal_data, |
| 1412 | .device_enable_and_init = device_enable_and_init_v4, |
| 1413 | .device_enable_auto_rck = device_enable_auto_rck_v4, |
| 1414 | .device_read_count_rc_n = device_read_count_rc_n_v4, |
| 1415 | .set_cal_data = set_calibration_data_v4, |
| 1416 | .init_controller = init_controller_v4, |
| 1417 | }, |
| 1418 | .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, |
| 1419 | .num_efuse_addr = 22, |
| 1420 | .num_efuse_block = 1, |
| 1421 | .cal_data = { |
| 1422 | .default_golden_temp = 50, |
| 1423 | .default_count_r = 35000, |
| 1424 | .default_count_rc = 2750, |
| 1425 | }, |
| 1426 | .coeff = { |
| 1427 | .a = -250460, |
| 1428 | .b = 250460, |
| 1429 | }, |
| 1430 | }; |
| 1431 | |
| 1432 | /* |
| 1433 | * LVTS MT7988 |
| 1434 | */ |
| 1435 | |
| 1436 | #define MT7988_NUM_LVTS (ARRAY_SIZE(mt7988_tc_settings)) |
| 1437 | |
| 1438 | enum mt7988_lvts_domain { MT7988_AP_DOMAIN, MT7988_NUM_DOMAIN }; |
| 1439 | |
| 1440 | enum mt7988_lvts_sensor_enum { |
| 1441 | MT7988_TS2_0, |
| 1442 | MT7988_TS2_1, |
| 1443 | MT7988_TS2_2, |
| 1444 | MT7988_TS2_3, |
| 1445 | MT7988_TS3_0, |
| 1446 | MT7988_TS3_1, |
| 1447 | MT7988_TS3_2, |
| 1448 | MT7988_TS3_3, |
| 1449 | MT7988_NUM_TS |
| 1450 | }; |
| 1451 | |
| 1452 | static void mt7988_efuse_to_cal_data(struct lvts_data *lvts_data) |
| 1453 | { |
| 1454 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 1455 | |
| 1456 | cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, 31, 24); |
| 1457 | |
| 1458 | cal_data->count_r[MT7988_TS2_0] = GET_CAL_DATA_BITMASK(0, 23, 0); |
| 1459 | cal_data->count_r[MT7988_TS2_1] = GET_CAL_DATA_BITMASK(1, 23, 0); |
| 1460 | cal_data->count_r[MT7988_TS2_2] = GET_CAL_DATA_BITMASK(2, 23, 0); |
| 1461 | cal_data->count_r[MT7988_TS2_3] = GET_CAL_DATA_BITMASK(3, 23, 0); |
| 1462 | cal_data->count_rc[MT7988_TS2_0] = GET_CAL_DATA_BITMASK(4, 23, 0); |
| 1463 | |
| 1464 | cal_data->count_r[MT7988_TS3_0] = GET_CAL_DATA_BITMASK(5, 23, 0); |
| 1465 | cal_data->count_r[MT7988_TS3_1] = GET_CAL_DATA_BITMASK(6, 23, 0); |
| 1466 | cal_data->count_r[MT7988_TS3_2] = GET_CAL_DATA_BITMASK(7, 23, 0); |
| 1467 | cal_data->count_r[MT7988_TS3_3] = GET_CAL_DATA_BITMASK(8, 23, 0); |
| 1468 | cal_data->count_rc[MT7988_TS3_0] = GET_CAL_DATA_BITMASK(9, 23, 0); |
| 1469 | } |
| 1470 | |
| 1471 | static struct tc_settings mt7988_tc_settings[] = { |
| 1472 | [0] = { |
| 1473 | .domain_index = MT7988_AP_DOMAIN, |
| 1474 | .addr_offset = 0x0, |
| 1475 | .num_sensor = 4, |
| 1476 | .sensor_map = {MT7988_TS2_0, MT7988_TS2_1, MT7988_TS2_2, |
| 1477 | MT7988_TS2_3}, |
| 1478 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1479 | .hw_filter = LVTS_FILTER_16_OF_18, |
| 1480 | .dominator_sensing_point = SENSING_POINT0, |
| 1481 | .hw_reboot_trip_point = 117000, |
| 1482 | .irq_bit = BIT(4), |
| 1483 | }, |
| 1484 | [1] = { |
| 1485 | .domain_index = MT7988_AP_DOMAIN, |
| 1486 | .addr_offset = 0x100, |
| 1487 | .num_sensor = 4, |
| 1488 | .sensor_map = {MT7988_TS3_0, MT7988_TS3_1, MT7988_TS3_2, |
| 1489 | MT7988_TS3_3}, |
| 1490 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1491 | .hw_filter = LVTS_FILTER_16_OF_18, |
| 1492 | .dominator_sensing_point = SENSING_POINT0, |
| 1493 | .hw_reboot_trip_point = 117000, |
| 1494 | .irq_bit = BIT(5), |
| 1495 | } |
| 1496 | |
| 1497 | }; |
| 1498 | |
| 1499 | static struct lvts_data mt7988_lvts_data = { |
| 1500 | .num_domain = MT7988_NUM_DOMAIN, |
| 1501 | .num_tc = MT7988_NUM_LVTS, |
| 1502 | .tc = mt7988_tc_settings, |
| 1503 | .num_sensor = MT7988_NUM_TS, |
| 1504 | .ops = { |
| 1505 | .efuse_to_cal_data = mt7988_efuse_to_cal_data, |
| 1506 | .device_enable_and_init = device_enable_and_init_v5, |
| 1507 | .device_enable_auto_rck = device_enable_auto_rck_v4, |
| 1508 | .device_read_count_rc_n = device_read_count_rc_n_v5, |
| 1509 | .set_cal_data = set_calibration_data_v4, |
| 1510 | .init_controller = init_controller_v4, |
| 1511 | }, |
| 1512 | .feature_bitmap = 0, |
| 1513 | .num_efuse_addr = 10, |
| 1514 | .num_efuse_block = 1, |
| 1515 | .cal_data = { |
| 1516 | .default_golden_temp = 60, |
| 1517 | .default_count_r = 19380, |
| 1518 | .default_count_rc = 5330, |
| 1519 | }, |
| 1520 | .coeff = { |
| 1521 | .a = -204650, |
| 1522 | .b = 204650, |
| 1523 | }, |
| 1524 | }; |
| 1525 | |
| 1526 | /* |
| 1527 | * LVTS MT8195 |
| 1528 | */ |
| 1529 | |
| 1530 | #define MT8195_NUM_LVTS (ARRAY_SIZE(mt8195_tc_settings)) |
| 1531 | |
| 1532 | enum mt8195_lvts_domain { |
| 1533 | MT8195_AP_DOMAIN, |
| 1534 | MT8195_MCU_DOMAIN, |
| 1535 | MT8195_NUM_DOMAIN |
| 1536 | }; |
| 1537 | |
| 1538 | enum mt8195_lvts_sensor_enum { |
| 1539 | MT8195_TS1_0, |
| 1540 | MT8195_TS1_1, |
| 1541 | MT8195_TS2_0, |
| 1542 | MT8195_TS2_1, |
| 1543 | MT8195_TS3_0, |
| 1544 | MT8195_TS3_1, |
| 1545 | MT8195_TS3_2, |
| 1546 | MT8195_TS3_3, |
| 1547 | MT8195_TS4_0, |
| 1548 | MT8195_TS4_1, |
| 1549 | MT8195_TS5_0, |
| 1550 | MT8195_TS5_1, |
| 1551 | MT8195_TS6_0, |
| 1552 | MT8195_TS6_1, |
| 1553 | MT8195_TS6_2, |
| 1554 | MT8195_TS7_0, |
| 1555 | MT8195_TS7_1, |
| 1556 | MT8195_NUM_TS |
| 1557 | }; |
| 1558 | |
| 1559 | static void mt8195_efuse_to_cal_data(struct lvts_data *lvts_data) |
| 1560 | { |
| 1561 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 1562 | |
| 1563 | cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, 31, 24); |
| 1564 | cal_data->count_r[MT8195_TS1_0] = GET_CAL_DATA_BITMASK(1, 23, 0); |
| 1565 | cal_data->count_r[MT8195_TS1_1] = |
| 1566 | (GET_CAL_DATA_BITMASK(2, 15, 0) << 8) + |
| 1567 | GET_CAL_DATA_BITMASK(1, 31, 24); |
| 1568 | cal_data->count_r[MT8195_TS2_0] = GET_CAL_DATA_BITMASK(3, 31, 8); |
| 1569 | cal_data->count_r[MT8195_TS2_1] = GET_CAL_DATA_BITMASK(4, 23, 0); |
| 1570 | cal_data->count_r[MT8195_TS3_0] = |
| 1571 | (GET_CAL_DATA_BITMASK(6, 7, 0) << 16) + |
| 1572 | GET_CAL_DATA_BITMASK(5, 31, 16); |
| 1573 | cal_data->count_r[MT8195_TS3_1] = GET_CAL_DATA_BITMASK(6, 31, 8); |
| 1574 | cal_data->count_r[MT8195_TS3_2] = GET_CAL_DATA_BITMASK(7, 23, 0); |
| 1575 | cal_data->count_r[MT8195_TS3_3] = |
| 1576 | (GET_CAL_DATA_BITMASK(8, 15, 0) << 8) + |
| 1577 | GET_CAL_DATA_BITMASK(7, 31, 24); |
| 1578 | cal_data->count_r[MT8195_TS4_0] = GET_CAL_DATA_BITMASK(9, 31, 8); |
| 1579 | cal_data->count_r[MT8195_TS4_1] = GET_CAL_DATA_BITMASK(10, 23, 0); |
| 1580 | cal_data->count_r[MT8195_TS5_0] = |
| 1581 | (GET_CAL_DATA_BITMASK(12, 7, 0) << 16) + |
| 1582 | GET_CAL_DATA_BITMASK(11, 31, 16); |
| 1583 | cal_data->count_r[MT8195_TS5_1] = GET_CAL_DATA_BITMASK(12, 31, 8); |
| 1584 | cal_data->count_r[MT8195_TS6_0] = |
| 1585 | (GET_CAL_DATA_BITMASK(14, 15, 0) << 8) + |
| 1586 | GET_CAL_DATA_BITMASK(13, 31, 24); |
| 1587 | cal_data->count_r[MT8195_TS6_1] = |
| 1588 | (GET_CAL_DATA_BITMASK(15, 7, 0) << 16) + |
| 1589 | GET_CAL_DATA_BITMASK(14, 31, 16); |
| 1590 | cal_data->count_r[MT8195_TS6_2] = GET_CAL_DATA_BITMASK(15, 31, 8); |
| 1591 | cal_data->count_r[MT8195_TS7_0] = |
| 1592 | (GET_CAL_DATA_BITMASK(17, 15, 0) << 8) + |
| 1593 | GET_CAL_DATA_BITMASK(16, 31, 24); |
| 1594 | cal_data->count_r[MT8195_TS7_1] = |
| 1595 | (GET_CAL_DATA_BITMASK(18, 7, 0) << 16) + |
| 1596 | GET_CAL_DATA_BITMASK(17, 31, 16); |
| 1597 | cal_data->count_rc[MT8195_TS1_0] = |
| 1598 | (GET_CAL_DATA_BITMASK(3, 7, 0) << 16) + |
| 1599 | GET_CAL_DATA_BITMASK(2, 31, 16); |
| 1600 | cal_data->count_rc[MT8195_TS2_0] = |
| 1601 | (GET_CAL_DATA_BITMASK(5, 15, 0) << 8) + |
| 1602 | GET_CAL_DATA_BITMASK(4, 31, 24); |
| 1603 | cal_data->count_rc[MT8195_TS3_0] = |
| 1604 | (GET_CAL_DATA_BITMASK(9, 7, 0) << 16) + |
| 1605 | GET_CAL_DATA_BITMASK(8, 31, 16); |
| 1606 | cal_data->count_rc[MT8195_TS4_0] = |
| 1607 | (GET_CAL_DATA_BITMASK(11, 15, 0) << 8) + |
| 1608 | GET_CAL_DATA_BITMASK(10, 31, 24); |
| 1609 | cal_data->count_rc[MT8195_TS5_0] = GET_CAL_DATA_BITMASK(13, 23, 0); |
| 1610 | cal_data->count_rc[MT8195_TS6_0] = GET_CAL_DATA_BITMASK(16, 23, 0); |
| 1611 | cal_data->count_rc[MT8195_TS7_0] = GET_CAL_DATA_BITMASK(18, 31, 8); |
| 1612 | } |
| 1613 | |
| 1614 | static struct tc_settings mt8195_tc_settings[] = { |
| 1615 | [0] = { |
| 1616 | .domain_index = MT8195_MCU_DOMAIN, |
| 1617 | .addr_offset = 0x0, |
| 1618 | .num_sensor = 2, |
| 1619 | .sensor_map = {MT8195_TS1_0, MT8195_TS1_1}, |
| 1620 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1621 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1622 | .dominator_sensing_point = SENSING_POINT1, |
| 1623 | .hw_reboot_trip_point = 117000, |
| 1624 | .irq_bit = BIT(3), |
| 1625 | }, |
| 1626 | [1] = { |
| 1627 | .domain_index = MT8195_MCU_DOMAIN, |
| 1628 | .addr_offset = 0x100, |
| 1629 | .num_sensor = 2, |
| 1630 | .sensor_map = {MT8195_TS2_0, MT8195_TS2_1}, |
| 1631 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1632 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1633 | .dominator_sensing_point = SENSING_POINT0, |
| 1634 | .hw_reboot_trip_point = 117000, |
| 1635 | .irq_bit = BIT(4), |
| 1636 | }, |
| 1637 | [2] = { |
| 1638 | .domain_index = MT8195_MCU_DOMAIN, |
| 1639 | .addr_offset = 0x200, |
| 1640 | .num_sensor = 4, |
| 1641 | .sensor_map = {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, |
| 1642 | MT8195_TS3_3}, |
| 1643 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1644 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1645 | .dominator_sensing_point = SENSING_POINT0, |
| 1646 | .hw_reboot_trip_point = 117000, |
| 1647 | .irq_bit = BIT(5), |
| 1648 | }, |
| 1649 | [3] = { |
| 1650 | .domain_index = MT8195_AP_DOMAIN, |
| 1651 | .addr_offset = 0x0, |
| 1652 | .num_sensor = 2, |
| 1653 | .sensor_map = {MT8195_TS4_0, MT8195_TS4_1}, |
| 1654 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1655 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1656 | .dominator_sensing_point = SENSING_POINT0, |
| 1657 | .hw_reboot_trip_point = 117000, |
| 1658 | .irq_bit = BIT(3), |
| 1659 | }, |
| 1660 | [4] = { |
| 1661 | .domain_index = MT8195_AP_DOMAIN, |
| 1662 | .addr_offset = 0x100, |
| 1663 | .num_sensor = 2, |
| 1664 | .sensor_map = {MT8195_TS5_0, MT8195_TS5_1}, |
| 1665 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1666 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1667 | .dominator_sensing_point = SENSING_POINT1, |
| 1668 | .hw_reboot_trip_point = 117000, |
| 1669 | .irq_bit = BIT(4), |
| 1670 | }, |
| 1671 | [5] = { |
| 1672 | .domain_index = MT8195_AP_DOMAIN, |
| 1673 | .addr_offset = 0x200, |
| 1674 | .num_sensor = 3, |
| 1675 | .sensor_map = {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2}, |
| 1676 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1677 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1678 | .dominator_sensing_point = SENSING_POINT1, |
| 1679 | .hw_reboot_trip_point = 117000, |
| 1680 | .irq_bit = BIT(5), |
| 1681 | }, |
| 1682 | [6] = { |
| 1683 | .domain_index = MT8195_AP_DOMAIN, |
| 1684 | .addr_offset = 0x300, |
| 1685 | .num_sensor = 2, |
| 1686 | .sensor_map = {MT8195_TS7_0, MT8195_TS7_1}, |
| 1687 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1688 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1689 | .dominator_sensing_point = SENSING_POINT0, |
| 1690 | .hw_reboot_trip_point = 117000, |
| 1691 | .irq_bit = BIT(6), |
| 1692 | } |
| 1693 | }; |
| 1694 | |
| 1695 | static struct lvts_data mt8195_lvts_data = { |
| 1696 | .num_domain = MT8195_NUM_DOMAIN, |
| 1697 | .num_tc = MT8195_NUM_LVTS, |
| 1698 | .tc = mt8195_tc_settings, |
| 1699 | .num_sensor = MT8195_NUM_TS, |
| 1700 | .ops = { |
| 1701 | .efuse_to_cal_data = mt8195_efuse_to_cal_data, |
| 1702 | .device_enable_and_init = device_enable_and_init_v4, |
| 1703 | .device_enable_auto_rck = device_enable_auto_rck_v4, |
| 1704 | .device_read_count_rc_n = device_read_count_rc_n_v4, |
| 1705 | .set_cal_data = set_calibration_data_v4, |
| 1706 | .init_controller = init_controller_v4, |
| 1707 | }, |
| 1708 | .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, |
| 1709 | .num_efuse_addr = 22, |
| 1710 | .num_efuse_block = 2, |
| 1711 | .cal_data = { |
| 1712 | .default_golden_temp = 50, |
| 1713 | .default_count_r = 35000, |
| 1714 | .default_count_rc = 2750, |
| 1715 | }, |
| 1716 | .coeff = { |
| 1717 | .a = -250460, |
| 1718 | .b = 250460, |
| 1719 | }, |
| 1720 | }; |
| 1721 | |
| 1722 | /* |
| 1723 | * LVTS MT8139 |
| 1724 | */ |
| 1725 | |
| 1726 | #define MT8139_NUM_LVTS (ARRAY_SIZE(mt8139_tc_settings)) |
| 1727 | |
| 1728 | enum mt8139_lvts_domain { |
| 1729 | MT8139_AP_DOMAIN, |
| 1730 | MT8139_MCU_DOMAIN, |
| 1731 | MT8139_NUM_DOMAIN |
| 1732 | }; |
| 1733 | |
| 1734 | enum mt8139_lvts_sensor_enum { |
| 1735 | MT8139_TS1_0, |
| 1736 | MT8139_TS1_1, |
| 1737 | MT8139_TS1_2, |
| 1738 | MT8139_TS1_3, |
| 1739 | MT8139_TS2_0, |
| 1740 | MT8139_TS2_1, |
| 1741 | MT8139_TS2_2, |
| 1742 | MT8139_TS2_3, |
| 1743 | MT8139_TS3_0, |
| 1744 | MT8139_TS3_1, |
| 1745 | MT8139_TS3_2, |
| 1746 | MT8139_TS3_3, |
| 1747 | MT8139_NUM_TS |
| 1748 | }; |
| 1749 | |
| 1750 | static void mt8139_efuse_to_cal_data(struct lvts_data *lvts_data) |
| 1751 | { |
| 1752 | struct sensor_cal_data *cal_data = &lvts_data->cal_data; |
| 1753 | |
| 1754 | cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, 7, 0); |
| 1755 | cal_data->count_r[MT8139_TS1_0] = GET_CAL_DATA_BITMASK(0, 31, 8); |
| 1756 | cal_data->count_r[MT8139_TS1_1] = GET_CAL_DATA_BITMASK(1, 23, 0); |
| 1757 | cal_data->count_r[MT8139_TS1_2] = |
| 1758 | (GET_CAL_DATA_BITMASK(2, 15, 0) << 8) + |
| 1759 | GET_CAL_DATA_BITMASK(1, 31, 24); |
| 1760 | cal_data->count_r[MT8139_TS1_3] = |
| 1761 | (GET_CAL_DATA_BITMASK(3, 7, 0) << 16) + |
| 1762 | GET_CAL_DATA_BITMASK(2, 31, 16); |
| 1763 | cal_data->count_rc[MT8139_TS1_0] = GET_CAL_DATA_BITMASK(3, 31, 8); |
| 1764 | |
| 1765 | cal_data->count_r[MT8139_TS2_0] = GET_CAL_DATA_BITMASK(4, 23, 0); |
| 1766 | cal_data->count_r[MT8139_TS2_1] = |
| 1767 | (GET_CAL_DATA_BITMASK(5, 15, 0) << 8) + |
| 1768 | GET_CAL_DATA_BITMASK(4, 31, 24); |
| 1769 | cal_data->count_r[MT8139_TS2_2] = |
| 1770 | (GET_CAL_DATA_BITMASK(6, 7, 0) << 16) + |
| 1771 | GET_CAL_DATA_BITMASK(5, 31, 16); |
| 1772 | cal_data->count_r[MT8139_TS2_3] = GET_CAL_DATA_BITMASK(6, 31, 8); |
| 1773 | cal_data->count_rc[MT8139_TS2_0] = GET_CAL_DATA_BITMASK(7, 23, 0); |
| 1774 | |
| 1775 | cal_data->count_r[MT8139_TS3_0] = |
| 1776 | (GET_CAL_DATA_BITMASK(8, 15, 0) << 8) + |
| 1777 | GET_CAL_DATA_BITMASK(7, 31, 24); |
| 1778 | cal_data->count_r[MT8139_TS3_1] = |
| 1779 | (GET_CAL_DATA_BITMASK(9, 7, 0) << 16) + |
| 1780 | GET_CAL_DATA_BITMASK(8, 31, 16); |
| 1781 | cal_data->count_r[MT8139_TS3_2] = GET_CAL_DATA_BITMASK(9, 31, 8); |
| 1782 | cal_data->count_r[MT8139_TS3_3] = GET_CAL_DATA_BITMASK(10, 23, 0); |
| 1783 | cal_data->count_rc[MT8139_TS3_0] = |
| 1784 | (GET_CAL_DATA_BITMASK(11, 15, 0) << 8) + |
| 1785 | GET_CAL_DATA_BITMASK(10, 31, 24); |
| 1786 | } |
| 1787 | |
| 1788 | static struct tc_settings mt8139_tc_settings[] = { |
| 1789 | [0] = { |
| 1790 | .domain_index = MT8139_MCU_DOMAIN, |
| 1791 | .addr_offset = 0x0, |
| 1792 | .num_sensor = 4, |
| 1793 | .sensor_map = {MT8139_TS1_0, MT8139_TS1_1, MT8139_TS1_2, |
| 1794 | MT8139_TS1_3}, |
| 1795 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1796 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1797 | .dominator_sensing_point = SENSING_POINT1, |
| 1798 | .hw_reboot_trip_point = 117000, |
| 1799 | .irq_bit = BIT(3), |
| 1800 | }, |
| 1801 | [1] = { |
| 1802 | .domain_index = MT8139_AP_DOMAIN, |
| 1803 | .addr_offset = 0x0, |
| 1804 | .num_sensor = 4, |
| 1805 | .sensor_map = {MT8139_TS2_0, MT8139_TS2_1, MT8139_TS2_2, |
| 1806 | MT8139_TS2_3}, |
| 1807 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1808 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1809 | .dominator_sensing_point = SENSING_POINT0, |
| 1810 | .hw_reboot_trip_point = 117000, |
| 1811 | .irq_bit = BIT(4), |
| 1812 | }, |
| 1813 | [2] = { |
| 1814 | .domain_index = MT8139_AP_DOMAIN, |
| 1815 | .addr_offset = 0x100, |
| 1816 | .num_sensor = 4, |
| 1817 | .sensor_map = {MT8139_TS3_0, MT8139_TS3_1, MT8139_TS3_2, |
| 1818 | MT8139_TS3_3}, |
| 1819 | .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), |
| 1820 | .hw_filter = LVTS_FILTER_2_OF_4, |
| 1821 | .dominator_sensing_point = SENSING_POINT0, |
| 1822 | .hw_reboot_trip_point = 117000, |
| 1823 | .irq_bit = BIT(5), |
| 1824 | } |
| 1825 | |
| 1826 | }; |
| 1827 | |
| 1828 | static struct lvts_data mt8139_lvts_data = { |
| 1829 | .num_domain = MT8139_NUM_DOMAIN, |
| 1830 | .num_tc = MT8139_NUM_LVTS, |
| 1831 | .tc = mt8139_tc_settings, |
| 1832 | .num_sensor = MT8139_NUM_TS, |
| 1833 | .ops = { |
| 1834 | .efuse_to_cal_data = mt8139_efuse_to_cal_data, |
| 1835 | .device_enable_and_init = device_enable_and_init_v4, |
| 1836 | .device_enable_auto_rck = device_enable_auto_rck_v4, |
| 1837 | .device_read_count_rc_n = device_read_count_rc_n_v4, |
| 1838 | .set_cal_data = set_calibration_data_v4, |
| 1839 | .init_controller = init_controller_v4, |
| 1840 | }, |
| 1841 | .feature_bitmap = 0, |
| 1842 | .num_efuse_addr = 48, |
| 1843 | .num_efuse_block = 1, |
| 1844 | .cal_data = { |
| 1845 | .default_golden_temp = 50, |
| 1846 | .default_count_r = 35000, |
| 1847 | .default_count_rc = 2750, |
| 1848 | }, |
| 1849 | .coeff = { |
| 1850 | .a = -250460, |
| 1851 | .b = 250460, |
| 1852 | }, |
| 1853 | }; |
| 1854 | |
| 1855 | /* |
| 1856 | * Support chips |
| 1857 | */ |
| 1858 | static const struct of_device_id lvts_of_match[] = { |
| 1859 | { |
| 1860 | .compatible = "mediatek,mt6873-lvts", |
| 1861 | .data = (void *)&mt6873_lvts_data, |
| 1862 | }, |
| 1863 | { |
| 1864 | .compatible = "mediatek,mt8195-lvts", |
| 1865 | .data = (void *)&mt8195_lvts_data, |
| 1866 | }, |
| 1867 | { |
| 1868 | .compatible = "mediatek,mt8139-lvts", |
| 1869 | .data = (void *)&mt8139_lvts_data, |
| 1870 | }, |
| 1871 | { |
| 1872 | .compatible = "mediatek,mt7988-lvts", |
| 1873 | .data = (void *)&mt7988_lvts_data, |
| 1874 | }, |
| 1875 | {}, |
| 1876 | }; |
| 1877 | MODULE_DEVICE_TABLE(of, lvts_of_match); |
| 1878 | |
| 1879 | static struct platform_driver soc_temp_lvts = { |
| 1880 | .probe = lvts_probe, |
| 1881 | .remove = lvts_remove, |
| 1882 | .suspend = lvts_suspend, |
| 1883 | .resume = lvts_resume, |
| 1884 | .driver = { |
| 1885 | .name = "mtk-soc-temp-lvts", |
| 1886 | .of_match_table = lvts_of_match, |
| 1887 | }, |
| 1888 | }; |
| 1889 | |
| 1890 | module_platform_driver(soc_temp_lvts); |
| 1891 | MODULE_AUTHOR("Yu-Chia Chang <ethan.chang@mediatek.com>"); |
| 1892 | MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>"); |
| 1893 | MODULE_AUTHOR("Henry Yen <henry.yen@mediatek.com>"); |
| 1894 | MODULE_DESCRIPTION("Mediatek soc temperature driver"); |
| 1895 | MODULE_LICENSE("GPL v2"); |