| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* Copyright 2016 MediaTek Inc. |
| 2 | * Author: Nelson Chang <nelson.chang@mediatek.com> |
| 3 | * Author: Carlos Huang <carlos.huang@mediatek.com> |
| 4 | * Author: Harry Huang <harry.huang@mediatek.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | #ifndef RAETH_REG_H |
| 16 | #define RAETH_REG_H |
| 17 | |
| 18 | #include <linux/mii.h> /* for struct mii_if_info in ra2882ethreg.h */ |
| 19 | #include <linux/version.h> /* check linux version */ |
| 20 | #include <linux/interrupt.h> /* for "struct tasklet_struct" */ |
| 21 | #include <linux/ip.h> |
| 22 | #include <linux/ipv6.h> |
| 23 | #include <linux/workqueue.h> |
| 24 | #include <linux/netdevice.h> |
| 25 | #include <linux/if_vlan.h> |
| 26 | |
| 27 | #include "raether.h" |
| 28 | |
| 29 | #define MAX_PACKET_SIZE 1514 |
| 30 | #define MIN_PACKET_SIZE 60 |
| 31 | #if defined(CONFIG_MACH_MT7623) || defined(CONFIG_SOC_MT7621) |
| 32 | #define MAX_PTXD_LEN 0x3fff /* 16k */ |
| 33 | #define MAX_QTXD_LEN 0x3fff /* 16k */ |
| 34 | #else |
| 35 | #define MAX_PTXD_LEN 0x3fff /* 16k */ |
| 36 | #define MAX_QTXD_LEN 0xffff |
| 37 | #endif |
| 38 | |
| 39 | #define phys_to_bus(a) (a) |
| 40 | |
| 41 | extern void __iomem *ethdma_sysctl_base; |
| 42 | extern void __iomem *ethdma_frame_engine_base; |
| 43 | |
| 44 | /* bits range: for example BITS(16,23) = 0xFF0000 |
| 45 | * ==> (BIT(m)-1) = 0x0000FFFF ~(BIT(m)-1) => 0xFFFF0000 |
| 46 | * ==> (BIT(n+1)-1) = 0x00FFFFFF |
| 47 | */ |
| 48 | #define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n))) |
| 49 | |
| 50 | #define ETHER_ADDR_LEN 6 |
| 51 | |
| 52 | /* Phy Vender ID list */ |
| 53 | |
| 54 | #define EV_ICPLUS_PHY_ID0 0x0243 |
| 55 | #define EV_ICPLUS_PHY_ID1 0x0D90 |
| 56 | #define EV_MARVELL_PHY_ID0 0x0141 |
| 57 | #define EV_MARVELL_PHY_ID1 0x0CC2 |
| 58 | #define EV_VTSS_PHY_ID0 0x0007 |
| 59 | #define EV_VTSS_PHY_ID1 0x0421 |
| 60 | |
| 61 | #define ETHSYS_BASE 0x1b000000 |
| 62 | #define SGMII_CONFIG_0 BIT(9) /*SGMII path enable of GMAC1*/ |
| 63 | #define SGMII_CONFIG_1 BIT(8) /*SGMII path enable of GMAC1*/ |
| 64 | |
| developer | 268dde2 | 2021-05-05 16:55:21 +0800 | [diff] [blame] | 65 | #define SGMII_REG_BASE0 (0x10060000) |
| 66 | #define SGMII_REG_PHYA_BASE0 (0x10060100) |
| 67 | #define SGMII_REG_BASE1 (0x10070000) |
| 68 | #define SGMII_REG_PHYA_BASE1 (0x10070100) |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 69 | #define ETHSYS_MAC_BASE (0x1b110000) |
| 70 | |
| 71 | #if defined(CONFIG_MACH_LEOPARD) |
| 72 | #define FE_RSTCTL 0x1B000034 |
| 73 | #define INFRA_BASE 0x1000070C |
| 74 | #define GEPHY_CTRL0 0x10000710 |
| 75 | #define GPIO_GO_BASE GEPHY_CTRL0 |
| 76 | #define GPIO_MODE_BASE 0x10217300 |
| 77 | #else |
| 78 | #define INFRA_BASE 0 |
| 79 | #define FE_RSTCTL 0 |
| 80 | #define GPIO_GO_BASE 0x10211800 |
| 81 | #define GPIO_MODE_BASE 0x10211300 |
| 82 | #endif |
| 83 | |
| 84 | /* ETHDMASYS base address |
| 85 | * for I2S/PCM/GDMA/HSDMA/FE/GMAC |
| 86 | */ |
| 87 | #define ETHDMASYS_BASE ethdma_sysctl_base |
| 88 | #define ETHDMASYS_FRAME_ENGINE_BASE ethdma_frame_engine_base |
| 89 | |
| 90 | #define ETHDMASYS_SYSCTL_BASE ETHDMASYS_BASE |
| 91 | #define ETHDMASYS_PPE_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x0C00) |
| 92 | #define ETHDMASYS_ETH_MAC_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x10000) |
| 93 | #if defined(CONFIG_MACH_MT7623) || defined(CONFIG_SOC_MT7621) |
| 94 | #define ETHDMASYS_ETH_SW_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x10000) |
| 95 | #else |
| 96 | #define ETHDMASYS_ETH_SW_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x18000) |
| 97 | #endif |
| 98 | |
| 99 | #define RALINK_FRAME_ENGINE_BASE ETHDMASYS_FRAME_ENGINE_BASE |
| 100 | #define RALINK_PPE_BASE ETHDMASYS_PPE_BASE |
| 101 | #define RALINK_SYSCTL_BASE ETHDMASYS_SYSCTL_BASE |
| 102 | #define RALINK_ETH_MAC_BASE ETHDMASYS_ETH_MAC_BASE |
| 103 | #define RALINK_ETH_SW_BASE ETHDMASYS_ETH_SW_BASE |
| 104 | |
| 105 | #define RSTCTL_FE_RST BIT(6) |
| 106 | #define RALINK_FE_RST RSTCTL_FE_RST |
| 107 | |
| 108 | #define RSTCTL_ETH_RST BIT(23) |
| 109 | #define RALINK_ETH_RST RSTCTL_ETH_RST |
| 110 | |
| 111 | /* FE_INT_STATUS */ |
| 112 | #define RX_COHERENT BIT(31) |
| 113 | #define RX_DLY_INT BIT(30) |
| 114 | #define TX_COHERENT BIT(29) |
| 115 | #define TX_DLY_INT BIT(28) |
| 116 | #define RING3_RX_DLY_INT BIT(27) |
| 117 | #define RING2_RX_DLY_INT BIT(26) |
| 118 | #define RING1_RX_DLY_INT BIT(25) |
| 119 | #define RING0_RX_DLY_INT BIT(30) |
| 120 | |
| 121 | #define RSS_RX_INT0 (RX_DONE_INT0 | RX_DONE_INT1 | \ |
| 122 | RING0_RX_DLY_INT | RING1_RX_DLY_INT) |
| 123 | |
| 124 | #define RSS_RX_RING0 (RX_DONE_INT0 | RING0_RX_DLY_INT) |
| 125 | #define RSS_RX_RING1 (RX_DONE_INT1 | RING1_RX_DLY_INT) |
| 126 | #define RSS_RX_RING2 (RX_DONE_INT2 | RING2_RX_DLY_INT) |
| 127 | #define RSS_RX_RING3 (RX_DONE_INT3 | RING3_RX_DLY_INT) |
| 128 | |
| 129 | #define RSS_RX_INT1 (RX_DONE_INT2 | RX_DONE_INT3 | \ |
| 130 | RING2_RX_DLY_INT | RING3_RX_DLY_INT) |
| 131 | |
| 132 | #define RSS_RX_DLY_INT0 (RING0_RX_DLY_INT | RING1_RX_DLY_INT) |
| 133 | #define RSS_RX_DLY_INT1 (RING2_RX_DLY_INT | RING3_RX_DLY_INT) |
| 134 | |
| 135 | #define RSS_RX_DLY_INT (RING0_RX_DLY_INT | RING1_RX_DLY_INT | \ |
| 136 | RING2_RX_DLY_INT | RING3_RX_DLY_INT) |
| 137 | |
| 138 | #define RXD_ERROR BIT(24) |
| 139 | #define ALT_RPLC_INT3 BIT(23) |
| 140 | #define ALT_RPLC_INT2 BIT(22) |
| 141 | #define ALT_RPLC_INT1 BIT(21) |
| 142 | |
| 143 | #define RX_DONE_INT3 BIT(19) |
| 144 | #define RX_DONE_INT2 BIT(18) |
| 145 | #define RX_DONE_INT1 BIT(17) |
| 146 | #define RX_DONE_INT0 BIT(16) |
| 147 | |
| 148 | #define TX_DONE_INT3 BIT(3) |
| 149 | #define TX_DONE_INT2 BIT(2) |
| 150 | #define TX_DONE_INT1 BIT(1) |
| 151 | #define TX_DONE_INT0 BIT(0) |
| 152 | |
| 153 | #define RLS_COHERENT BIT(29) |
| 154 | #define RLS_DLY_INT BIT(28) |
| 155 | #define RLS_DONE_INT BIT(0) |
| 156 | |
| 157 | #define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \ |
| 158 | TX_DONE_INT1 | TX_DONE_INT0 | \ |
| 159 | RX_DONE_INT0 | RX_DONE_INT1 | \ |
| 160 | RX_DONE_INT2 | RX_DONE_INT3) |
| 161 | |
| 162 | #define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | \ |
| 163 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3) |
| 164 | #define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT) |
| 165 | #define RX_INT_ALL (RX_DONE_INT0 | RX_DONE_INT1 | \ |
| 166 | RX_DONE_INT2 | RX_DONE_INT3 | \ |
| 167 | RING0_RX_DLY_INT | RING1_RX_DLY_INT | \ |
| 168 | RING2_RX_DLY_INT | RING3_RX_DLY_INT | RX_DLY_INT) |
| 169 | #define TX_INT_ALL (TX_DONE_INT0 | TX_DLY_INT) |
| 170 | |
| 171 | #define NUM_QDMA_PAGE 512 |
| 172 | #define QDMA_PAGE_SIZE 2048 |
| 173 | |
| 174 | /* SW_INT_STATUS */ |
| 175 | #define ESW_PHY_POLLING (RALINK_ETH_MAC_BASE + 0x0000) |
| 176 | #define MAC1_WOL (RALINK_ETH_SW_BASE + 0x0110) |
| 177 | #define WOL_INT_CLR BIT(17) |
| 178 | #define WOL_INT_EN BIT(1) |
| 179 | #define WOL_EN BIT(0) |
| 180 | |
| 181 | #define P5_LINK_CH BIT(5) |
| 182 | #define P4_LINK_CH BIT(4) |
| 183 | #define P3_LINK_CH BIT(3) |
| 184 | #define P2_LINK_CH BIT(2) |
| 185 | #define P1_LINK_CH BIT(1) |
| 186 | #define P0_LINK_CH BIT(0) |
| 187 | |
| 188 | #define RX_BUF_ALLOC_SIZE 2000 |
| 189 | #define FASTPATH_HEADROOM 64 |
| 190 | |
| 191 | #define ETHER_BUFFER_ALIGN 32 /* /// Align on a cache line */ |
| 192 | |
| 193 | #define ETHER_ALIGNED_RX_SKB_ADDR(addr) \ |
| 194 | ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \ |
| 195 | ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr)) |
| 196 | |
| 197 | struct PSEUDO_ADAPTER { |
| 198 | struct net_device *raeth_dev; |
| 199 | struct net_device *pseudo_dev; |
| 200 | struct net_device_stats stat; |
| 201 | struct mii_if_info mii_info; |
| 202 | }; |
| 203 | |
| 204 | #define MAX_PSEUDO_ENTRY 1 |
| 205 | |
| 206 | /* Register Categories Definition */ |
| 207 | #if 0 |
| 208 | #define FE_PSE_OFFSET 0x0000 |
| 209 | #define CDMA_OFFSET 0x0400 |
| 210 | #define GDM1_OFFSET 0x0500 |
| 211 | #define ADMA_OFFSET 0x0800 |
| 212 | #define CDMQ_OFFSET 0x1400 |
| 213 | #define GDM2_OFFSET 0x1500 |
| 214 | #define CDM_OFFSET 0x1600 |
| 215 | #define QDMA_OFFSET 0x1800 |
| 216 | #define RSS_OFFSET 0x3000 |
| 217 | #define EDMA0_OFFSET 0x3800 |
| 218 | #define EDMA1_OFFSET 0x3C00 |
| 219 | #else |
| 220 | #define FE_PSE_OFFSET 0x0000 |
| 221 | #define CDMA_OFFSET 0x0400 |
| 222 | #define GDM1_OFFSET 0x0500 |
| 223 | #define ADMA_OFFSET 0x4000 |
| 224 | #define CDMQ_OFFSET 0x1400 |
| 225 | #define GDM2_OFFSET 0x1500 |
| 226 | #define CDM_OFFSET 0x1600 |
| 227 | #define QDMA_OFFSET 0x4400 |
| 228 | #define RSS_OFFSET 0x2800 |
| 229 | #define EDMA0_OFFSET 0x3800 |
| 230 | #define EDMA1_OFFSET 0x3C00 |
| 231 | #endif |
| 232 | |
| 233 | /* Register Map Detail */ |
| 234 | /* FE/PSE */ |
| 235 | #define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14) |
| 236 | #define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C) |
| 237 | #define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58) |
| 238 | #define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x00) |
| 239 | #define FE_RST_GL (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x04) |
| 240 | #define FE_INT_STATUS2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x08) |
| 241 | #define FOE_TS_T (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x10) |
| 242 | #define FE_INT_ENABLE2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0c) |
| 243 | #define FE_INT_GRP (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x20) |
| 244 | #define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x40) |
| 245 | #define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x44) |
| 246 | #define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x48) |
| 247 | #define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x4C) |
| 248 | #define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x50) |
| 249 | #define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x54) |
| 250 | #define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x58) |
| 251 | #define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x5C) |
| 252 | |
| 253 | #define MAC1_LINK BIT(24) |
| 254 | #define MAC2_LINK BIT(25) |
| 255 | #define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x100) |
| 256 | #define FE_GLO_MISC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x124) |
| 257 | #define PSE_IQ_REV1 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x140) |
| 258 | #define PSE_IQ_REV2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x144) |
| 259 | #define PSE_IQ_REV3 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x148) |
| 260 | #define PSE_IQ_REV4 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x14C) |
| 261 | #define PSE_IQ_REV5 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x150) |
| 262 | #define PSE_IQ_REV6 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x154) |
| 263 | #define PSE_IQ_REV7 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x158) |
| 264 | #define PSE_IQ_REV8 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x15C) |
| 265 | #define PSE_OQ_TH1 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x160) |
| 266 | #define PSE_OQ_TH2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x164) |
| 267 | #define PSE_OQ_TH3 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x168) |
| 268 | #define PSE_OQ_TH4 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x16C) |
| 269 | #define PSE_OQ_TH5 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x170) |
| 270 | #define PSE_OQ_TH6 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x174) |
| 271 | #define PSE_OQ_TH7 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x178) |
| 272 | #define PSE_OQ_TH8 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x17C) |
| 273 | #define FE_PSE_FREE (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x240) |
| 274 | #define FE_DROP_FQ (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x244) |
| 275 | #define FE_DROP_FC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x248) |
| 276 | #define FE_DROP_PPE (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x24c) |
| 277 | /* GDM1 */ |
| 278 | #define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x00) |
| 279 | #define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x04) |
| 280 | #define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x08) |
| 281 | #define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x0C) |
| 282 | #define GDMA1_SCH_CFG GDMA1_SHPR_CFG |
| 283 | /* CDMA */ |
| 284 | #define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x000) |
| 285 | #define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x000) |
| 286 | #define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x004) |
| 287 | #define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x300) |
| 288 | #define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x304) |
| 289 | #define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x308) |
| 290 | #define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x30C) |
| 291 | #define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x320) |
| 292 | #define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x324) |
| 293 | #define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x328) |
| 294 | #define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x32C) |
| 295 | #define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x330) |
| 296 | #define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x334) |
| 297 | #define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x338) |
| 298 | #define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x33C) |
| 299 | /* ADMA */ |
| 300 | #define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x000) |
| 301 | #define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x004) |
| 302 | #define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x008) |
| 303 | #define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x00C) |
| 304 | #define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x010) |
| 305 | #define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x014) |
| 306 | #define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x018) |
| 307 | #define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x01C) |
| 308 | #define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x020) |
| 309 | #define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x024) |
| 310 | #define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x028) |
| 311 | #define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x02C) |
| 312 | #define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x030) |
| 313 | #define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x034) |
| 314 | #define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x038) |
| 315 | #define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x03C) |
| 316 | #define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x100) |
| 317 | #define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x104) |
| 318 | #define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x108) |
| 319 | #define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x10C) |
| 320 | #define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x110) |
| 321 | #define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x114) |
| 322 | #define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x118) |
| 323 | #define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x11C) |
| 324 | #define RX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x120) |
| 325 | #define RX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x124) |
| 326 | #define RX_CALC_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x128) |
| 327 | #define RX_DRX_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x12C) |
| 328 | #define RX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x130) |
| 329 | #define RX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x134) |
| 330 | #define RX_CALC_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x138) |
| 331 | #define RX_DRX_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x13C) |
| 332 | #define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x200) |
| 333 | #define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x204) |
| 334 | #define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x208) |
| 335 | #define PDMA_RST_CFG (PDMA_RST_IDX) |
| 336 | #define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x20C) |
| 337 | #define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x210) |
| 338 | #define INT_STATUS (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x220) |
| 339 | #define FE_INT_STATUS (INT_STATUS) |
| 340 | #define INT_MASK (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x228) |
| 341 | #define FE_INT_ENABLE (INT_MASK) |
| 342 | #define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x280) |
| 343 | #define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x284) |
| 344 | #define PDMA_INT_GRP1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x250) |
| 345 | #define PDMA_INT_GRP2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x254) |
| 346 | #define PDMA_INT_GRP3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x22c) |
| 347 | /* GDM2 */ |
| 348 | #define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x00) |
| 349 | #define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x04) |
| 350 | #define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x08) |
| 351 | #define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x0C) |
| 352 | #define GDMA2_SCH_CFG GDMA2_SHPR_CFG |
| 353 | /* QDMA */ |
| 354 | #define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x000) |
| 355 | #define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x004) |
| 356 | #define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x008) |
| 357 | #define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x00C) |
| 358 | #define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x010) |
| 359 | #define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x014) |
| 360 | #define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x018) |
| 361 | #define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x01C) |
| 362 | #define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x020) |
| 363 | #define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x024) |
| 364 | #define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x028) |
| 365 | #define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C) |
| 366 | #define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x030) |
| 367 | #define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x034) |
| 368 | #define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x038) |
| 369 | #define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x03C) |
| 370 | #define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x040) |
| 371 | #define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x044) |
| 372 | #define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x048) |
| 373 | #define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x04C) |
| 374 | #define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x050) |
| 375 | #define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x054) |
| 376 | #define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x058) |
| 377 | #define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x05C) |
| 378 | #define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x060) |
| 379 | #define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x064) |
| 380 | #define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x068) |
| 381 | #define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x06C) |
| 382 | #define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x070) |
| 383 | #define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x074) |
| 384 | #define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x078) |
| 385 | #define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x07C) |
| 386 | #define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x080) |
| 387 | #define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x084) |
| 388 | #define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x088) |
| 389 | #define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x08C) |
| 390 | #define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x090) |
| 391 | #define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x094) |
| 392 | #define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x098) |
| 393 | #define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x09C) |
| 394 | #define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0A0) |
| 395 | #define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0A4) |
| 396 | #define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0A8) |
| 397 | #define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0AC) |
| 398 | #define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0B0) |
| 399 | #define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0B4) |
| 400 | #define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0B8) |
| 401 | #define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0BC) |
| 402 | #define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0C0) |
| 403 | #define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0C4) |
| 404 | #define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0C8) |
| 405 | #define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0CC) |
| 406 | #define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0D0) |
| 407 | #define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0D4) |
| 408 | #define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0D8) |
| 409 | #define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0DC) |
| 410 | #define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0E0) |
| 411 | #define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0E4) |
| 412 | #define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0E8) |
| 413 | #define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0EC) |
| 414 | #define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0F0) |
| 415 | #define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0F4) |
| 416 | #define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0F8) |
| 417 | #define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0FC) |
| 418 | #define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x100) |
| 419 | #define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x104) |
| 420 | #define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x108) |
| 421 | #define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x10C) |
| 422 | #define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x110) |
| 423 | #define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x114) |
| 424 | #define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x118) |
| 425 | #define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x11C) |
| 426 | #define VQTX_TB_BASE_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x180) |
| 427 | #define VQTX_TB_BASE_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x184) |
| 428 | #define VQTX_TB_BASE_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x188) |
| 429 | #define VQTX_TB_BASE_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x18C) |
| 430 | #define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x200) |
| 431 | #define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x204) |
| 432 | #define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x208) |
| 433 | #define QDMA_RST_CFG (QDMA_RST_IDX) |
| 434 | #define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x20C) |
| 435 | #define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x210) |
| 436 | #define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x214) |
| 437 | #define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x218) |
| 438 | #define QFE_INT_STATUS (QDMA_INT_STS) |
| 439 | #define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x21C) |
| 440 | #define QFE_INT_ENABLE (QDMA_INT_MASK) |
| 441 | #define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x220) |
| 442 | #define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x224) |
| 443 | #define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x228) |
| 444 | #define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x22C) |
| 445 | #define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x230) |
| 446 | #define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x234) |
| 447 | #define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x238) |
| 448 | #define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x240) |
| 449 | #define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x244) |
| 450 | #define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x248) |
| 451 | #define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x24C) |
| 452 | #define QTX_MIB_IF (RALINK_FRAME_ENGINE_BASE + 0x1abc) |
| 453 | #define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x300) |
| 454 | #define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x304) |
| 455 | #define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x308) |
| 456 | #define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x310) |
| 457 | #define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x314) |
| 458 | #define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x318) |
| 459 | #define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x320) |
| 460 | #define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x324) |
| 461 | #define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x328) |
| 462 | #define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x32C) |
| 463 | #define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x350) |
| 464 | #define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x354) |
| 465 | #define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x358) |
| 466 | #define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x35C) |
| 467 | #define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x360) |
| 468 | #define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x364) |
| 469 | #define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x368) |
| 470 | #define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x36C) |
| 471 | #define QDMA_INT_GRP1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x220) |
| 472 | #define QDMA_INT_GRP2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x224) |
| 473 | |
| 474 | #define DELAY_INT_INIT 0x8f0f8f0f |
| 475 | #define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT) |
| 476 | #define RSS_INT_DLY_INT_2RING (RING0_RX_DLY_INT | RING1_RX_DLY_INT) |
| 477 | #define RSS_INT_DLY_INT (RING0_RX_DLY_INT | RING1_RX_DLY_INT | \ |
| 478 | RING2_RX_DLY_INT | RING3_RX_DLY_INT | TX_DLY_INT) |
| 479 | |
| 480 | /* LRO global control */ |
| 481 | /* Bits [15:0]:LRO_ALT_RFSH_TIMER, Bits [20:16]:LRO_ALT_TICK_TIMER */ |
| 482 | #define LRO_ALT_REFRESH_TIMER (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x001C) |
| 483 | |
| 484 | /* LRO auto-learn table info */ |
| 485 | #define PDMA_FE_ALT_CF8 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0300) |
| 486 | #define PDMA_FE_ALT_SGL_CFC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0304) |
| 487 | #define PDMA_FE_ALT_SEQ_CFC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0308) |
| 488 | |
| 489 | /* LRO controls */ |
| 490 | #define ADMA_LRO_CTRL_OFFSET (ADMA_OFFSET + 0x180) |
| 491 | /*Bit [0]:LRO_EN, Bit [1]:LRO_IPv6_EN, Bit [2]:MULTIPLE_NON_LRO_RX_RING_EN, |
| 492 | * Bit [3]:MULTIPLE_RXD_PREFETCH_EN, Bit [4]:RXD_PREFETCH_EN, |
| 493 | * Bit [5]:LRO_DLY_INT_EN, Bit [6]:LRO_CRSN_BNW, Bit [7]:L3_CKS_UPD_EN, |
| 494 | * Bit [20]:first_ineligible_pkt_redirect_en, Bit [21]:cr_lro_alt_score_mode, |
| 495 | * Bit [22]:cr_lro_alt_rplc_mode, Bit [23]:cr_lro_l4_ctrl_psh_en, |
| 496 | * Bits [28:26]:LRO_RING_RELINGUISH_REQ, Bits [31:29]:LRO_RING_RELINGUISH_DONE |
| 497 | */ |
| 498 | #define ADMA_LRO_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 499 | ADMA_LRO_CTRL_OFFSET + 0x00) |
| 500 | /* Bits [31:0]:LRO_CPU_REASON */ |
| 501 | #define ADMA_LRO_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 502 | ADMA_LRO_CTRL_OFFSET + 0x04) |
| 503 | /* Bits [31:0]:AUTO_LEARN_LRO_ELIGIBLE_THRESHOLD */ |
| 504 | #define ADMA_LRO_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 505 | ADMA_LRO_CTRL_OFFSET + 0x08) |
| 506 | /*Bits [7:0]:LRO_MAX_AGGREGATED_CNT, |
| 507 | * Bits [11:8]:LRO_VLAN_EN, Bits [13:12]:LRO_VLAN_VID_CMP_DEPTH, |
| 508 | * Bit [14]:ADMA_FW_RSTN_REQ, Bit [15]:ADMA_MODE, Bits [31:16]:LRO_MIN_RXD_SDL0 |
| 509 | */ |
| 510 | #define ADMA_LRO_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 511 | ADMA_LRO_CTRL_OFFSET + 0x0C) |
| 512 | |
| 513 | /* LRO RX delay interrupt configurations */ |
| 514 | #define LRO_RX1_DLY_INT (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x0270) |
| 515 | #define LRO_RX2_DLY_INT (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x0274) |
| 516 | #define LRO_RX3_DLY_INT (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x0278) |
| 517 | |
| 518 | /* LRO auto-learn configurations */ |
| 519 | #define PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET (ADMA_OFFSET + 0x190) |
| 520 | #define PDMA_LRO_ATL_OVERFLOW_ADJ (RALINK_FRAME_ENGINE_BASE + \ |
| 521 | PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET) |
| 522 | #define LRO_ALT_SCORE_DELTA (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x024c) |
| 523 | |
| 524 | /* LRO agg timer configurations */ |
| 525 | #define LRO_MAX_AGG_TIME (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x025c) |
| 526 | |
| 527 | /* LRO configurations of RX ring #0 */ |
| 528 | #define LRO_RXRING0_OFFSET (ADMA_OFFSET + 0x300) |
| 529 | #define LRO_RX_RING0_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 530 | LRO_RXRING0_OFFSET + 0x04) |
| 531 | #define LRO_RX_RING0_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 532 | LRO_RXRING0_OFFSET + 0x08) |
| 533 | #define LRO_RX_RING0_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 534 | LRO_RXRING0_OFFSET + 0x0C) |
| 535 | #define LRO_RX_RING0_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 536 | LRO_RXRING0_OFFSET + 0x10) |
| 537 | #define LRO_RX_RING0_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 538 | LRO_RXRING0_OFFSET + 0x28) |
| 539 | /* Bit [8]:RING0_VLD, Bit [9]:RING0_MYIP_VLD */ |
| 540 | #define LRO_RX_RING0_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 541 | LRO_RXRING0_OFFSET + 0x2C) |
| 542 | #define LRO_RX_RING0_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 543 | LRO_RXRING0_OFFSET + 0x30) |
| 544 | /* LRO configurations of RX ring #1 */ |
| 545 | #define LRO_RXRING1_OFFSET (ADMA_OFFSET + 0x340) |
| 546 | #define LRO_RX_RING1_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \ |
| 547 | LRO_RXRING1_OFFSET + 0x00) |
| 548 | #define LRO_RX_RING1_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 549 | LRO_RXRING1_OFFSET + 0x04) |
| 550 | #define LRO_RX_RING1_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 551 | LRO_RXRING1_OFFSET + 0x08) |
| 552 | #define LRO_RX_RING1_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 553 | LRO_RXRING1_OFFSET + 0x0C) |
| 554 | #define LRO_RX_RING1_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 555 | LRO_RXRING1_OFFSET + 0x10) |
| 556 | #define LRO_RX_RING1_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 557 | LRO_RXRING1_OFFSET + 0x14) |
| 558 | #define LRO_RX_RING1_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 559 | LRO_RXRING1_OFFSET + 0x18) |
| 560 | #define LRO_RX_RING1_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 561 | LRO_RXRING1_OFFSET + 0x1C) |
| 562 | #define LRO_RX_RING1_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 563 | LRO_RXRING1_OFFSET + 0x20) |
| 564 | #define LRO_RX_RING1_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 565 | LRO_RXRING1_OFFSET + 0x24) |
| 566 | #define LRO_RX_RING1_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 567 | LRO_RXRING1_OFFSET + 0x28) |
| 568 | #define LRO_RX_RING1_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 569 | LRO_RXRING1_OFFSET + 0x2C) |
| 570 | #define LRO_RX_RING1_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 571 | LRO_RXRING1_OFFSET + 0x30) |
| 572 | #define LRO_RXRING2_OFFSET (ADMA_OFFSET + 0x380) |
| 573 | #define LRO_RX_RING2_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \ |
| 574 | LRO_RXRING2_OFFSET + 0x00) |
| 575 | #define LRO_RX_RING2_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 576 | LRO_RXRING2_OFFSET + 0x04) |
| 577 | #define LRO_RX_RING2_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 578 | LRO_RXRING2_OFFSET + 0x08) |
| 579 | #define LRO_RX_RING2_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 580 | LRO_RXRING2_OFFSET + 0x0C) |
| 581 | #define LRO_RX_RING2_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 582 | LRO_RXRING2_OFFSET + 0x10) |
| 583 | #define LRO_RX_RING2_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 584 | LRO_RXRING2_OFFSET + 0x14) |
| 585 | #define LRO_RX_RING2_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 586 | LRO_RXRING2_OFFSET + 0x18) |
| 587 | #define LRO_RX_RING2_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 588 | LRO_RXRING2_OFFSET + 0x1C) |
| 589 | #define LRO_RX_RING2_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 590 | LRO_RXRING2_OFFSET + 0x20) |
| 591 | #define LRO_RX_RING2_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 592 | LRO_RXRING2_OFFSET + 0x24) |
| 593 | #define LRO_RX_RING2_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 594 | LRO_RXRING2_OFFSET + 0x28) |
| 595 | #define LRO_RX_RING2_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 596 | LRO_RXRING2_OFFSET + 0x2C) |
| 597 | #define LRO_RX_RING2_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 598 | LRO_RXRING2_OFFSET + 0x30) |
| 599 | #define LRO_RXRING3_OFFSET (ADMA_OFFSET + 0x3C0) |
| 600 | #define LRO_RX_RING3_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \ |
| 601 | LRO_RXRING3_OFFSET + 0x00) |
| 602 | #define LRO_RX_RING3_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 603 | LRO_RXRING3_OFFSET + 0x04) |
| 604 | #define LRO_RX_RING3_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 605 | LRO_RXRING3_OFFSET + 0x08) |
| 606 | #define LRO_RX_RING3_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 607 | LRO_RXRING3_OFFSET + 0x0C) |
| 608 | #define LRO_RX_RING3_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 609 | LRO_RXRING3_OFFSET + 0x10) |
| 610 | #define LRO_RX_RING3_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 611 | LRO_RXRING3_OFFSET + 0x14) |
| 612 | #define LRO_RX_RING3_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 613 | LRO_RXRING3_OFFSET + 0x18) |
| 614 | #define LRO_RX_RING3_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 615 | LRO_RXRING3_OFFSET + 0x1C) |
| 616 | #define LRO_RX_RING3_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 617 | LRO_RXRING3_OFFSET + 0x20) |
| 618 | #define LRO_RX_RING3_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \ |
| 619 | LRO_RXRING3_OFFSET + 0x24) |
| 620 | #define LRO_RX_RING3_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \ |
| 621 | LRO_RXRING3_OFFSET + 0x28) |
| 622 | #define LRO_RX_RING3_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \ |
| 623 | LRO_RXRING3_OFFSET + 0x2C) |
| 624 | #define LRO_RX_RING3_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \ |
| 625 | LRO_RXRING3_OFFSET + 0x30) |
| 626 | |
| 627 | #define ADMA_DBG_OFFSET (ADMA_OFFSET + 0x230) |
| 628 | #define ADMA_TX_DBG0 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x00) |
| 629 | #define ADMA_TX_DBG1 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x04) |
| 630 | #define ADMA_RX_DBG0 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x08) |
| 631 | #define ADMA_RX_DBG1 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x0C) |
| 632 | |
| 633 | /********RSS CR ************/ |
| 634 | #define ADMA_RSS_GLO_CFG (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x00) |
| 635 | #define ADMA_RSS_INDR_TABLE_DW0 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x50) |
| 636 | #define ADMA_RSS_INDR_TABLE_DW1 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x54) |
| 637 | #define ADMA_RSS_INDR_TABLE_DW2 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x58) |
| 638 | #define ADMA_RSS_INDR_TABLE_DW3 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x5C) |
| 639 | #define ADMA_RSS_INDR_TABLE_DW4 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x60) |
| 640 | #define ADMA_RSS_INDR_TABLE_DW5 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x64) |
| 641 | #define ADMA_RSS_INDR_TABLE_DW6 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x68) |
| 642 | #define ADMA_RSS_INDR_TABLE_DW7 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x6C) |
| 643 | |
| 644 | #define ADMA_RSS_HASH_KEY_DW0 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x20) |
| 645 | #define ADMA_RSS_HASH_KEY_DW1 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x24) |
| 646 | #define ADMA_RSS_HASH_KEY_DW2 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x28) |
| 647 | #define ADMA_RSS_HASH_KEY_DW3 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x2C) |
| 648 | #define ADMA_RSS_HASH_KEY_DW4 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x30) |
| 649 | #define ADMA_RSS_HASH_KEY_DW5 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x34) |
| 650 | #define ADMA_RSS_HASH_KEY_DW6 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x38) |
| 651 | #define ADMA_RSS_HASH_KEY_DW7 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x3C) |
| 652 | #define ADMA_RSS_HASH_KEY_DW8 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x40) |
| 653 | #define ADMA_RSS_HASH_KEY_DW9 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x44) |
| 654 | /* LRO RX ring mode */ |
| 655 | #define PDMA_RX_NORMAL_MODE (0x0) |
| 656 | #define PDMA_RX_PSE_MODE (0x1) |
| 657 | #define PDMA_RX_FORCE_PORT (0x2) |
| 658 | #define PDMA_RX_AUTO_LEARN (0x3) |
| 659 | |
| 660 | #define ADMA_RX_RING0 (0) |
| 661 | #define ADMA_RX_RING1 (1) |
| 662 | #define ADMA_RX_RING2 (2) |
| 663 | #define ADMA_RX_RING3 (3) |
| 664 | |
| 665 | #define ADMA_RX_LEN0_MASK (0x3fff) |
| 666 | #define ADMA_RX_LEN1_MASK (0x3) |
| 667 | |
| 668 | #define SET_ADMA_RX_LEN0(x) ((x) & ADMA_RX_LEN0_MASK) |
| 669 | #define SET_ADMA_RX_LEN1(x) ((x) & ADMA_RX_LEN1_MASK) |
| 670 | |
| 671 | #define QDMA_PAGE (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x1F0) |
| 672 | |
| 673 | /*SFQ use*/ |
| 674 | #define VQTX_TB_BASE0 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0180) |
| 675 | #define VQTX_TB_BASE1 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0184) |
| 676 | #define VQTX_TB_BASE2 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0188) |
| 677 | #define VQTX_TB_BASE3 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x018C) |
| 678 | #define VQTX_GLO (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0280) |
| 679 | #define VQTX_INVLD_PTR (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x028C) |
| 680 | #define VQTX_NUM (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0290) |
| 681 | #define VQTX_SCH (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0298) |
| 682 | #define VQTX_HASH_CFG (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02A0) |
| 683 | #define VQTX_HASH_SD (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02A4) |
| 684 | #define VQTX_VLD_CFG (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02B0) |
| 685 | #define VQTX_MIB_IF (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02BC) |
| 686 | #define VQTX_MIB_PCNT (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C0) |
| 687 | #define VQTX_MIB_BCNT0 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C4) |
| 688 | #define VQTX_MIB_BCNT1 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C8) |
| 689 | #define VQTX_0_BIND_QID (PQ0 << 0) |
| 690 | #define VQTX_1_BIND_QID (PQ1 << 8) |
| 691 | #define VQTX_2_BIND_QID (PQ2 << 16) |
| 692 | #define VQTX_3_BIND_QID (PQ3 << 24) |
| 693 | #define VQTX_4_BIND_QID (PQ4 << 0) |
| 694 | #define VQTX_5_BIND_QID (PQ5 << 8) |
| 695 | #define VQTX_6_BIND_QID (PQ6 << 16) |
| 696 | #define VQTX_7_BIND_QID (PQ7 << 24) |
| 697 | #define VQTX_TB_BASE4 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0190) |
| 698 | #define VQTX_TB_BASE5 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0194) |
| 699 | #define VQTX_TB_BASE6 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0198) |
| 700 | #define VQTX_TB_BASE7 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x019C) |
| 701 | #define VQTX_0_3_BIND_QID (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0xBC0) |
| 702 | #define VQTX_4_7_BIND_QID (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0xBC4) |
| 703 | #define PQ0 0 |
| 704 | #define PQ1 1 |
| 705 | #define PQ2 15 |
| 706 | #define PQ3 16 |
| 707 | #define PQ4 30 |
| 708 | #define PQ5 31 |
| 709 | #define PQ6 43 |
| 710 | #define PQ7 63 |
| 711 | |
| 712 | #if defined(CONFIG_MACH_MT7623) |
| 713 | #define VQ_NUM0 256 |
| 714 | #define VQ_NUM1 256 |
| 715 | #define VQ_NUM2 256 |
| 716 | #define VQ_NUM3 256 |
| 717 | #define VQ_NUM4 0 |
| 718 | #define VQ_NUM5 0 |
| 719 | #define VQ_NUM6 0 |
| 720 | #define VQ_NUM7 0 |
| 721 | #define VQTX_NUM_0 (4 << 0) |
| 722 | #define VQTX_NUM_1 (4 << 4) |
| 723 | #define VQTX_NUM_2 (4 << 8) |
| 724 | #define VQTX_NUM_3 (4 << 12) |
| 725 | #define VQTX_NUM_4 0 |
| 726 | #define VQTX_NUM_5 0 |
| 727 | #define VQTX_NUM_6 0 |
| 728 | #define VQTX_NUM_7 0 |
| 729 | #else |
| 730 | #define VQ_NUM0 128 |
| 731 | #define VQ_NUM1 128 |
| 732 | #define VQ_NUM2 128 |
| 733 | #define VQ_NUM3 128 |
| 734 | #define VQ_NUM4 128 |
| 735 | #define VQ_NUM5 128 |
| 736 | #define VQ_NUM6 128 |
| 737 | #define VQ_NUM7 128 |
| 738 | #define VQTX_NUM_0 (3 << 0) |
| 739 | #define VQTX_NUM_1 (3 << 4) |
| 740 | #define VQTX_NUM_2 (3 << 8) |
| 741 | #define VQTX_NUM_3 (3 << 12) |
| 742 | #define VQTX_NUM_4 (3 << 16) |
| 743 | #define VQTX_NUM_5 (3 << 20) |
| 744 | #define VQTX_NUM_6 (3 << 24) |
| 745 | #define VQTX_NUM_7 (3 << 28) |
| 746 | #endif |
| 747 | |
| 748 | #define VQTX_MIB_EN BIT(17) |
| 749 | |
| 750 | /*HW IO-COHERNET BASE address*/ |
| 751 | #if defined(CONFIG_MACH_LEOPARD) |
| 752 | #define HW_IOC_BASE 0x1B000080 |
| 753 | #define IOC_OFFSET 4 |
| 754 | #else |
| 755 | #define HW_IOC_BASE 0x1B000400 |
| 756 | #define IOC_OFFSET 8 |
| 757 | #endif |
| 758 | |
| 759 | /*========================================= |
| 760 | * SFQ Table Format define |
| 761 | *========================================= |
| 762 | */ |
| 763 | struct SFQ_INFO1_T { |
| 764 | unsigned int VQHPTR; |
| 765 | }; |
| 766 | |
| 767 | struct SFQ_INFO2_T { |
| 768 | unsigned int VQTPTR; |
| 769 | }; |
| 770 | |
| 771 | struct SFQ_INFO3_T { |
| 772 | unsigned int QUE_DEPTH:16; |
| 773 | unsigned int DEFICIT_CNT:16; |
| 774 | }; |
| 775 | |
| 776 | struct SFQ_INFO4_T { |
| 777 | unsigned int RESV; |
| 778 | }; |
| 779 | |
| 780 | struct SFQ_INFO5_T { |
| 781 | unsigned int PKT_CNT; |
| 782 | }; |
| 783 | |
| 784 | struct SFQ_INFO6_T { |
| 785 | unsigned int BYTE_CNT; |
| 786 | }; |
| 787 | |
| 788 | struct SFQ_INFO7_T { |
| 789 | unsigned int BYTE_CNT; |
| 790 | }; |
| 791 | |
| 792 | struct SFQ_INFO8_T { |
| 793 | unsigned int RESV; |
| 794 | }; |
| 795 | |
| 796 | struct SFQ_table { |
| 797 | struct SFQ_INFO1_T sfq_info1; |
| 798 | struct SFQ_INFO2_T sfq_info2; |
| 799 | struct SFQ_INFO3_T sfq_info3; |
| 800 | struct SFQ_INFO4_T sfq_info4; |
| 801 | struct SFQ_INFO5_T sfq_info5; |
| 802 | struct SFQ_INFO6_T sfq_info6; |
| 803 | struct SFQ_INFO7_T sfq_info7; |
| 804 | struct SFQ_INFO8_T sfq_info8; |
| 805 | }; |
| 806 | |
| 807 | #if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING) |
| 808 | #define FE_GDM_RXID1_OFFSET (0x0130) |
| 809 | #define FE_GDM_RXID1 (RALINK_FRAME_ENGINE_BASE + FE_GDM_RXID1_OFFSET) |
| 810 | #define GDM_VLAN_PRI7_RXID_SEL BITS(30, 31) |
| 811 | #define GDM_VLAN_PRI6_RXID_SEL BITS(28, 29) |
| 812 | #define GDM_VLAN_PRI5_RXID_SEL BITS(26, 27) |
| 813 | #define GDM_VLAN_PRI4_RXID_SEL BITS(24, 25) |
| 814 | #define GDM_VLAN_PRI3_RXID_SEL BITS(22, 23) |
| 815 | #define GDM_VLAN_PRI2_RXID_SEL BITS(20, 21) |
| 816 | #define GDM_VLAN_PRI1_RXID_SEL BITS(18, 19) |
| 817 | #define GDM_VLAN_PRI0_RXID_SEL BITS(16, 17) |
| 818 | #define GDM_TCP_ACK_RXID_SEL BITS(4, 5) |
| 819 | #define GDM_TCP_ACK_WZPC BIT(3) |
| 820 | #define GDM_RXID_PRI_SEL BITS(0, 2) |
| 821 | |
| 822 | #define FE_GDM_RXID2_OFFSET (0x0134) |
| 823 | #define FE_GDM_RXID2 (RALINK_FRAME_ENGINE_BASE + FE_GDM_RXID2_OFFSET) |
| 824 | #define GDM_STAG7_RXID_SEL BITS(30, 31) |
| 825 | #define GDM_STAG6_RXID_SEL BITS(28, 29) |
| 826 | #define GDM_STAG5_RXID_SEL BITS(26, 27) |
| 827 | #define GDM_STAG4_RXID_SEL BITS(24, 25) |
| 828 | #define GDM_STAG3_RXID_SEL BITS(22, 23) |
| 829 | #define GDM_STAG2_RXID_SEL BITS(20, 21) |
| 830 | #define GDM_STAG1_RXID_SEL BITS(18, 19) |
| 831 | #define GDM_STAG0_RXID_SEL BITS(16, 17) |
| 832 | #define GDM_PID2_RXID_SEL BITS(2, 3) |
| 833 | #define GDM_PID1_RXID_SEL BITS(0, 1) |
| 834 | |
| 835 | #define GDM_PRI_PID (0) |
| 836 | #define GDM_PRI_VLAN_PID (1) |
| 837 | #define GDM_PRI_ACK_PID (2) |
| 838 | #define GDM_PRI_VLAN_ACK_PID (3) |
| 839 | #define GDM_PRI_ACK_VLAN_PID (4) |
| 840 | |
| 841 | #define SET_GDM_VLAN_PRI_RXID_SEL(x, y) \ |
| 842 | { \ |
| 843 | unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ |
| 844 | reg_val &= ~(0x03 << (((x) << 1) + 16)); \ |
| 845 | reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \ |
| 846 | sys_reg_write(FE_GDM_RXID1, reg_val); \ |
| 847 | } |
| 848 | |
| 849 | #define SET_GDM_TCP_ACK_RXID_SEL(x) \ |
| 850 | { \ |
| 851 | unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ |
| 852 | reg_val &= ~(GDM_TCP_ACK_RXID_SEL); \ |
| 853 | reg_val |= ((x) & 0x3) << 4; \ |
| 854 | sys_reg_write(FE_GDM_RXID1, reg_val); \ |
| 855 | } |
| 856 | |
| 857 | #define SET_GDM_TCP_ACK_WZPC(x) \ |
| 858 | { \ |
| 859 | unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ |
| 860 | reg_val &= ~(GDM_TCP_ACK_WZPC); \ |
| 861 | reg_val |= ((x) & 0x1) << 3; \ |
| 862 | sys_reg_write(FE_GDM_RXID1, reg_val); \ |
| 863 | } |
| 864 | |
| 865 | #define SET_GDM_RXID_PRI_SEL(x) \ |
| 866 | { \ |
| 867 | unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ |
| 868 | reg_val &= ~(GDM_RXID_PRI_SEL); \ |
| 869 | reg_val |= (x) & 0x7; \ |
| 870 | sys_reg_write(FE_GDM_RXID1, reg_val); \ |
| 871 | } |
| 872 | |
| 873 | #define GDM_STAG_RXID_SEL(x, y) \ |
| 874 | { \ |
| 875 | unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \ |
| 876 | reg_val &= ~(0x03 << (((x) << 1) + 16)); \ |
| 877 | reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \ |
| 878 | sys_reg_write(FE_GDM_RXID2, reg_val); \ |
| 879 | } |
| 880 | |
| 881 | #define SET_GDM_PID2_RXID_SEL(x) \ |
| 882 | { \ |
| 883 | unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \ |
| 884 | reg_val &= ~(GDM_PID2_RXID_SEL); \ |
| 885 | reg_val |= ((x) & 0x3) << 2; \ |
| 886 | sys_reg_write(FE_GDM_RXID2, reg_val); \ |
| 887 | } |
| 888 | |
| 889 | #define SET_GDM_PID1_RXID_SEL(x) \ |
| 890 | { \ |
| 891 | unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \ |
| 892 | reg_val &= ~(GDM_PID1_RXID_SEL); \ |
| 893 | reg_val |= ((x) & 0x3); \ |
| 894 | sys_reg_write(FE_GDM_RXID2, reg_val); \ |
| 895 | } |
| 896 | |
| 897 | #endif /* CONFIG_RAETH_MULTIPLE_RX_RING */ |
| 898 | /* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */ |
| 899 | #define PORT0_PKCOUNT (0xb01100e8) |
| 900 | #define PORT1_PKCOUNT (0xb01100ec) |
| 901 | #define PORT2_PKCOUNT (0xb01100f0) |
| 902 | #define PORT3_PKCOUNT (0xb01100f4) |
| 903 | #define PORT4_PKCOUNT (0xb01100f8) |
| 904 | #define PORT5_PKCOUNT (0xb01100fc) |
| 905 | |
| 906 | #define sys_reg_read(phys) (__raw_readl((void __iomem *)phys)) |
| 907 | #define sys_reg_write(phys, val) (__raw_writel(val, (void __iomem *)phys)) |
| 908 | |
| 909 | /* ====================================== */ |
| 910 | #define GDM1_DISPAD BIT(18) |
| 911 | #define GDM1_DISCRC BIT(17) |
| 912 | |
| 913 | /* GDMA1 uni-cast frames destination port */ |
| 914 | #define GDM1_ICS_EN (0x1 << 22) |
| 915 | #define GDM1_TCS_EN (0x1 << 21) |
| 916 | #define GDM1_UCS_EN (0x1 << 20) |
| 917 | #define GDM1_JMB_EN (0x1 << 19) |
| 918 | #define GDM1_STRPCRC (0x1 << 16) |
| 919 | #define GDM1_UFRC_P_CPU (0 << 12) |
| 920 | |
| 921 | /* GDMA1 broad-cast MAC address frames */ |
| 922 | #define GDM1_BFRC_P_CPU (0 << 8) |
| 923 | |
| 924 | /* GDMA1 multi-cast MAC address frames */ |
| 925 | #define GDM1_MFRC_P_CPU (0 << 4) |
| 926 | |
| 927 | /* GDMA1 other MAC address frames destination port */ |
| 928 | #define GDM1_OFRC_P_CPU (0 << 0) |
| 929 | |
| 930 | /* checksum generator registers are removed */ |
| 931 | #define ICS_GEN_EN (0 << 2) |
| 932 | #define UCS_GEN_EN (0 << 1) |
| 933 | #define TCS_GEN_EN (0 << 0) |
| 934 | |
| 935 | /* MDIO_CFG bit */ |
| 936 | #define MDIO_CFG_GP1_FC_TX BIT(11) |
| 937 | #define MDIO_CFG_GP1_FC_RX BIT(10) |
| 938 | |
| 939 | /* ====================================== */ |
| 940 | /* ====================================== */ |
| 941 | #define GP1_LNK_DWN BIT(9) |
| 942 | #define GP1_AN_FAIL BIT(8) |
| 943 | /* ====================================== */ |
| 944 | /* ====================================== */ |
| 945 | #define PSE_RESET BIT(0) |
| 946 | /* ====================================== */ |
| 947 | #define PST_DRX_IDX3 BIT(19) |
| 948 | #define PST_DRX_IDX2 BIT(18) |
| 949 | #define PST_DRX_IDX1 BIT(17) |
| 950 | #define PST_DRX_IDX0 BIT(16) |
| 951 | #define PST_DTX_IDX3 BIT(3) |
| 952 | #define PST_DTX_IDX2 BIT(2) |
| 953 | #define PST_DTX_IDX1 BIT(1) |
| 954 | #define PST_DTX_IDX0 BIT(0) |
| 955 | |
| 956 | #define RX_2B_OFFSET BIT(31) |
| 957 | #define CSR_CLKGATE_BYP BIT(30) |
| 958 | #define MULTI_EN BIT(10) |
| 959 | #define DESC_32B_EN BIT(8) |
| 960 | #define TX_WB_DDONE BIT(6) |
| 961 | #define RX_DMA_BUSY BIT(3) |
| 962 | #define TX_DMA_BUSY BIT(1) |
| 963 | #define RX_DMA_EN BIT(2) |
| 964 | #define TX_DMA_EN BIT(0) |
| 965 | |
| 966 | #define PDMA_BT_SIZE_4DWORDS (0 << 4) |
| 967 | #define PDMA_BT_SIZE_8DWORDS BIT(4) |
| 968 | #define PDMA_BT_SIZE_16DWORDS (2 << 4) |
| 969 | #define PDMA_BT_SIZE_32DWORDS (3 << 4) |
| 970 | #define PDMA_DESC_32B_E (1 << 8) |
| 971 | |
| 972 | #define ADMA_RX_BT_SIZE_4DWORDS (0 << 11) |
| 973 | #define ADMA_RX_BT_SIZE_8DWORDS BIT(11) |
| 974 | #define ADMA_RX_BT_SIZE_16DWORDS (2 << 11) |
| 975 | #define ADMA_RX_BT_SIZE_32DWORDS (3 << 11) |
| 976 | |
| 977 | /* Register bits. |
| 978 | */ |
| 979 | |
| 980 | #define MACCFG_RXEN BIT(2) |
| 981 | #define MACCFG_TXEN BIT(3) |
| 982 | #define MACCFG_PROMISC BIT(18) |
| 983 | #define MACCFG_RXMCAST BIT(19) |
| 984 | #define MACCFG_FDUPLEX BIT(20) |
| 985 | #define MACCFG_PORTSEL BIT(27) |
| 986 | #define MACCFG_HBEATDIS BIT(28) |
| 987 | |
| 988 | #define DMACTL_SR BIT(1) /* Start/Stop Receive */ |
| 989 | #define DMACTL_ST BIT(13) /* Start/Stop Transmission Command */ |
| 990 | |
| 991 | #define DMACFG_SWR BIT(0) /* Software Reset */ |
| 992 | #define DMACFG_BURST32 (32 << 8) |
| 993 | |
| 994 | #define DMASTAT_TS 0x00700000 /* Transmit Process State */ |
| 995 | #define DMASTAT_RS 0x000e0000 /* Receive Process State */ |
| 996 | |
| 997 | #define MACCFG_INIT 0 /* (MACCFG_FDUPLEX) // | MACCFG_PORTSEL) */ |
| 998 | |
| 999 | /* Descriptor bits. |
| 1000 | */ |
| 1001 | #define R_OWN 0x80000000 /* Own Bit */ |
| 1002 | #define RD_RER 0x02000000 /* Receive End Of Ring */ |
| 1003 | #define RD_LS 0x00000100 /* Last Descriptor */ |
| 1004 | #define RD_ES 0x00008000 /* Error Summary */ |
| 1005 | #define RD_CHAIN 0x01000000 /* Chained */ |
| 1006 | |
| 1007 | /* Word 0 */ |
| 1008 | #define T_OWN 0x80000000 /* Own Bit */ |
| 1009 | #define TD_ES 0x00008000 /* Error Summary */ |
| 1010 | |
| 1011 | /* Word 1 */ |
| 1012 | #define TD_LS 0x40000000 /* Last Segment */ |
| 1013 | #define TD_FS 0x20000000 /* First Segment */ |
| 1014 | #define TD_TER 0x08000000 /* Transmit End Of Ring */ |
| 1015 | #define TD_CHAIN 0x01000000 /* Chained */ |
| 1016 | |
| 1017 | #define TD_SET 0x08000000 /* Setup Packet */ |
| 1018 | |
| 1019 | #define POLL_DEMAND 1 |
| 1020 | |
| 1021 | #define RSTCTL (0x34) |
| 1022 | #define RSTCTL_RSTENET1 BIT(19) |
| 1023 | #define RSTCTL_RSTENET2 BIT(20) |
| 1024 | |
| 1025 | #define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000 |
| 1026 | #define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000 |
| 1027 | #define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01 |
| 1028 | #define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01 |
| 1029 | |
| 1030 | /* Define Whole FE Reset Register */ |
| 1031 | #define RSTCTRL (RALINK_SYSCTL_BASE + 0x34) |
| 1032 | #define RT2880_AGPIOCFG_REG (RALINK_SYSCTL_BASE + 0x3C) |
| 1033 | |
| 1034 | /*========================================= |
| 1035 | * PDMA RX Descriptor Format define |
| 1036 | *========================================= |
| 1037 | */ |
| 1038 | |
| 1039 | struct PDMA_RXD_INFO1_T { |
| 1040 | unsigned int PDP0; |
| 1041 | }; |
| 1042 | |
| 1043 | struct PDMA_RXD_INFO2_T { |
| 1044 | unsigned int PLEN1:2; |
| 1045 | unsigned int LRO_AGG_CNT:8; |
| 1046 | unsigned int REV:3; |
| 1047 | unsigned int FOE_ENTRY_32:1; |
| 1048 | unsigned int REV1:1; |
| 1049 | unsigned int TAG:1; |
| 1050 | unsigned int PLEN0:14; |
| 1051 | unsigned int LS0:1; |
| 1052 | unsigned int DDONE_bit:1; |
| 1053 | }; |
| 1054 | |
| 1055 | struct PDMA_RXD_INFO3_T { |
| 1056 | unsigned int VID:16; |
| 1057 | unsigned int TPID:16; |
| 1058 | }; |
| 1059 | |
| 1060 | struct PDMA_RXD_INFO4_T { |
| 1061 | unsigned int FOE_ENTRY:14; |
| 1062 | unsigned int CRSN:5; |
| 1063 | unsigned int SP:4; |
| 1064 | unsigned int L4F:1; |
| 1065 | unsigned int L4VLD:1; |
| 1066 | unsigned int TACK:1; |
| 1067 | unsigned int IP4F:1; |
| 1068 | unsigned int IP4:1; |
| 1069 | unsigned int IP6:1; |
| 1070 | unsigned int UN_USE1:3; |
| 1071 | }; |
| 1072 | |
| 1073 | struct PDMA_rxdesc { |
| 1074 | struct PDMA_RXD_INFO1_T rxd_info1; |
| 1075 | struct PDMA_RXD_INFO2_T rxd_info2; |
| 1076 | struct PDMA_RXD_INFO3_T rxd_info3; |
| 1077 | struct PDMA_RXD_INFO4_T rxd_info4; |
| 1078 | #ifdef CONFIG_32B_DESC |
| 1079 | unsigned int rxd_info5; |
| 1080 | unsigned int rxd_info6; |
| 1081 | unsigned int rxd_info7; |
| 1082 | unsigned int rxd_info8; |
| 1083 | #endif |
| 1084 | }; |
| 1085 | |
| 1086 | /*========================================= |
| 1087 | * PDMA TX Descriptor Format define |
| 1088 | *========================================= |
| 1089 | */ |
| 1090 | struct PDMA_TXD_INFO1_T { |
| 1091 | unsigned int SDP0; |
| 1092 | }; |
| 1093 | |
| 1094 | struct PDMA_TXD_INFO2_T { |
| 1095 | unsigned int SDL1:14; |
| 1096 | unsigned int LS1_bit:1; |
| 1097 | unsigned int BURST_bit:1; |
| 1098 | unsigned int SDL0:14; |
| 1099 | unsigned int LS0_bit:1; |
| 1100 | unsigned int DDONE_bit:1; |
| 1101 | }; |
| 1102 | |
| 1103 | struct PDMA_TXD_INFO3_T { |
| 1104 | unsigned int SDP1; |
| 1105 | }; |
| 1106 | |
| 1107 | struct PDMA_TXD_INFO4_T { |
| 1108 | unsigned int VLAN_TAG:17; /* INSV(1)+VPRI(3)+CFI(1)+VID(12) */ |
| 1109 | unsigned int RESV:2; |
| 1110 | unsigned int UDF:5; |
| 1111 | unsigned int FPORT:4; |
| 1112 | unsigned int TSO:1; |
| 1113 | unsigned int TUI_CO:3; |
| 1114 | }; |
| 1115 | |
| 1116 | struct PDMA_txdesc { |
| 1117 | struct PDMA_TXD_INFO1_T txd_info1; |
| 1118 | struct PDMA_TXD_INFO2_T txd_info2; |
| 1119 | struct PDMA_TXD_INFO3_T txd_info3; |
| 1120 | struct PDMA_TXD_INFO4_T txd_info4; |
| 1121 | #ifdef CONFIG_32B_DESC |
| 1122 | unsigned int txd_info5; |
| 1123 | unsigned int txd_info6; |
| 1124 | unsigned int txd_info7; |
| 1125 | unsigned int txd_info8; |
| 1126 | #endif |
| 1127 | }; |
| 1128 | |
| 1129 | /*========================================= |
| 1130 | * QDMA TX Descriptor Format define |
| 1131 | *========================================= |
| 1132 | */ |
| 1133 | struct QDMA_TXD_INFO1_T { |
| 1134 | unsigned int SDP; |
| 1135 | }; |
| 1136 | |
| 1137 | struct QDMA_TXD_INFO2_T { |
| 1138 | unsigned int NDP; |
| 1139 | }; |
| 1140 | |
| 1141 | struct QDMA_TXD_INFO3_T { |
| 1142 | unsigned int RSV0:6; |
| 1143 | unsigned int RSV1:2; |
| 1144 | unsigned int SDL:16; |
| 1145 | unsigned int RSV2:6; |
| 1146 | unsigned int LS:1; |
| 1147 | unsigned int DDONE:1; |
| 1148 | }; |
| 1149 | |
| 1150 | struct QDMA_TXD_INFO4_T { |
| 1151 | unsigned int RSV0:6; |
| 1152 | unsigned int RSV1:2; |
| 1153 | unsigned int FPORT:4; |
| 1154 | unsigned int RSV2:2; |
| 1155 | unsigned int RSV3:2; |
| 1156 | unsigned int QID:7; |
| 1157 | unsigned int RSV4:1; |
| 1158 | unsigned int RSV5:6; |
| 1159 | unsigned int SWC:1; |
| 1160 | unsigned int BURST:1; |
| 1161 | }; |
| 1162 | |
| 1163 | struct QDMA_TXD_INFO5_T { |
| 1164 | unsigned int PROT:3; |
| 1165 | unsigned int RSV0:2; |
| 1166 | unsigned int IPOFST:7; |
| 1167 | unsigned int RSV1:2; |
| 1168 | unsigned int VQID:10; |
| 1169 | unsigned int RSV2:2; |
| 1170 | unsigned int VQID0:1; |
| 1171 | unsigned int RSV3:1; |
| 1172 | unsigned int TUI_CO:3; |
| 1173 | unsigned int TSO:1; |
| 1174 | }; |
| 1175 | |
| 1176 | struct QDMA_TXD_INFO6_T { |
| 1177 | unsigned int VLAN_TAG_1:16; |
| 1178 | unsigned int INSV_1:1; |
| 1179 | unsigned int RSV0:14; |
| 1180 | unsigned int INSV_0:1; |
| 1181 | }; |
| 1182 | |
| 1183 | struct QDMA_TXD_INFO7_T { |
| 1184 | unsigned int VLAN_TAG_0:16; |
| 1185 | unsigned int VPID_0:16; |
| 1186 | }; |
| 1187 | |
| 1188 | struct QDMA_TXD_INFO8_T { |
| 1189 | unsigned int RSV; |
| 1190 | }; |
| 1191 | |
| 1192 | struct QDMA_txdesc { |
| 1193 | struct QDMA_TXD_INFO1_T txd_info1; |
| 1194 | struct QDMA_TXD_INFO2_T txd_info2; |
| 1195 | struct QDMA_TXD_INFO3_T txd_info3; |
| 1196 | struct QDMA_TXD_INFO4_T txd_info4; |
| 1197 | struct QDMA_TXD_INFO5_T txd_info5; |
| 1198 | struct QDMA_TXD_INFO6_T txd_info6; |
| 1199 | struct QDMA_TXD_INFO7_T txd_info7; |
| 1200 | struct QDMA_TXD_INFO8_T txd_info8; |
| 1201 | }; |
| 1202 | |
| 1203 | #define QTXD_LEN (sizeof(struct QDMA_txdesc)) |
| 1204 | #define PHY_ENABLE_AUTO_NEGO 0x1000 |
| 1205 | #define PHY_RESTART_AUTO_NEGO 0x0200 |
| 1206 | |
| 1207 | /* PHY_STAT_REG = 1; */ |
| 1208 | #define PHY_AUTO_NEGO_COMP 0x0020 |
| 1209 | #define PHY_LINK_STATUS 0x0004 |
| 1210 | |
| 1211 | /* PHY_AUTO_NEGO_REG = 4; */ |
| 1212 | #define PHY_CAP_10_HALF 0x0020 |
| 1213 | #define PHY_CAP_10_FULL 0x0040 |
| 1214 | #define PHY_CAP_100_HALF 0x0080 |
| 1215 | #define PHY_CAP_100_FULL 0x0100 |
| 1216 | |
| 1217 | /* proc definition */ |
| 1218 | |
| 1219 | #define PROCREG_CONTROL_FILE "/var/run/procreg_control" |
| 1220 | #if 0 |
| 1221 | #if defined(CONFIG_MACH_MT7623) |
| 1222 | #define PROCREG_DIR "mt7623" |
| 1223 | #elif defined(CONFIG_MACH_LEOPARD) |
| 1224 | #define PROCREG_DIR "leopard" |
| 1225 | #elif defined(CONFIG_PINCTRL_MT7622) |
| 1226 | #define PROCREG_DIR "mt7622" |
| 1227 | #elif defined(CONFIG_SOC_MT7621) |
| 1228 | #define PROCREG_DIR "mt7621" |
| 1229 | #endif |
| 1230 | #endif |
| 1231 | #define PROCREG_DIR "panther" |
| 1232 | #define PROCREG_SKBFREE "skb_free" |
| 1233 | #define PROCREG_TXRING "tx_ring" |
| 1234 | #define PROCREG_RXRING "rx_ring" |
| 1235 | #define PROCREG_RXRING1 "rx_ring1" |
| 1236 | #define PROCREG_RXRING2 "rx_ring2" |
| 1237 | #define PROCREG_RXRING3 "rx_ring3" |
| 1238 | #define PROCREG_NUM_OF_TXD "num_of_txd" |
| 1239 | #define PROCREG_TSO_LEN "tso_len" |
| 1240 | #define PROCREG_LRO_STATS "lro_stats" |
| 1241 | #define PROCREG_HW_LRO_STATS "hw_lro_stats" |
| 1242 | #define PROCREG_HW_LRO_AUTO_TLB "hw_lro_auto_tlb" |
| 1243 | #define PROCREG_HW_IO_COHERENT "hw_iocoherent" |
| 1244 | #define PROCREG_GMAC "gmac" |
| 1245 | #define PROCREG_GMAC2 "gmac2" |
| 1246 | #define PROCREG_CP0 "cp0" |
| 1247 | #define PROCREG_RAQOS "qos" |
| 1248 | #define PROCREG_READ_VAL "regread_value" |
| 1249 | #define PROCREG_WRITE_VAL "regwrite_value" |
| 1250 | #define PROCREG_ADDR "reg_addr" |
| 1251 | #define PROCREG_CTL "procreg_control" |
| 1252 | #define PROCREG_RXDONE_INTR "rxdone_intr_count" |
| 1253 | #define PROCREG_ESW_INTR "esw_intr_count" |
| 1254 | #define PROCREG_ESW_CNT "esw_cnt" |
| 1255 | #define PROCREG_ETH_CNT "eth_cnt" |
| 1256 | #define PROCREG_SNMP "snmp" |
| 1257 | #define PROCREG_SET_LAN_IP "set_lan_ip" |
| 1258 | #if defined(TASKLET_WORKQUEUE_SW) |
| 1259 | #define PROCREG_SCHE "schedule" |
| 1260 | #endif |
| 1261 | #define PROCREG_QDMA "qdma" |
| 1262 | #define PROCREG_INT_DBG "int_dbg" |
| 1263 | struct rt2880_reg_op_data { |
| 1264 | char name[64]; |
| 1265 | unsigned int reg_addr; |
| 1266 | unsigned int op; |
| 1267 | unsigned int reg_value; |
| 1268 | }; |
| 1269 | |
| 1270 | struct lro_counters { |
| 1271 | u32 lro_aggregated; |
| 1272 | u32 lro_flushed; |
| 1273 | u32 lro_no_desc; |
| 1274 | }; |
| 1275 | |
| 1276 | struct lro_para_struct { |
| 1277 | unsigned int lan_ip1; |
| 1278 | }; |
| 1279 | |
| 1280 | struct parse_result { |
| 1281 | /* layer2 header */ |
| 1282 | u8 dmac[6]; |
| 1283 | u8 smac[6]; |
| 1284 | |
| 1285 | /* vlan header */ |
| 1286 | u16 vlan_tag; |
| 1287 | u16 vlan1_gap; |
| 1288 | u16 vlan1; |
| 1289 | u16 vlan2_gap; |
| 1290 | u16 vlan2; |
| 1291 | u16 vlan_layer; |
| 1292 | |
| 1293 | /* pppoe header */ |
| 1294 | u32 pppoe_gap; |
| 1295 | u16 ppp_tag; |
| 1296 | u16 pppoe_sid; |
| 1297 | |
| 1298 | /* layer3 header */ |
| 1299 | u16 eth_type; |
| 1300 | struct iphdr iph; |
| 1301 | struct ipv6hdr ip6h; |
| 1302 | |
| 1303 | /* layer4 header */ |
| 1304 | struct tcphdr th; |
| 1305 | struct udphdr uh; |
| 1306 | |
| 1307 | u32 pkt_type; |
| 1308 | u8 is_mcast; |
| 1309 | }; |
| 1310 | |
| 1311 | #define DMA_GLO_CFG PDMA_GLO_CFG |
| 1312 | |
| 1313 | #if defined(CONFIG_RAETH_QDMATX_QDMARX) |
| 1314 | #define GDMA1_FWD_PORT 0x5555 |
| 1315 | #define GDMA2_FWD_PORT 0x5555 |
| 1316 | #elif defined(CONFIG_RAETH_PDMATX_QDMARX) |
| 1317 | #define GDMA1_FWD_PORT 0x5555 |
| 1318 | #define GDMA2_FWD_PORT 0x5555 |
| 1319 | #else |
| 1320 | #define GDMA1_FWD_PORT 0x0000 |
| 1321 | #define GDMA2_FWD_PORT 0x0000 |
| 1322 | #endif |
| 1323 | |
| 1324 | #if defined(CONFIG_RAETH_QDMATX_QDMARX) |
| 1325 | #define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0 |
| 1326 | #define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1 |
| 1327 | #elif defined(CONFIG_RAETH_PDMATX_QDMARX) |
| 1328 | #define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0 |
| 1329 | #define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1 |
| 1330 | #else |
| 1331 | #define RAETH_RX_CALC_IDX0 RX_CALC_IDX0 |
| 1332 | #define RAETH_RX_CALC_IDX1 RX_CALC_IDX1 |
| 1333 | #endif |
| 1334 | #define RAETH_RX_CALC_IDX2 RX_CALC_IDX2 |
| 1335 | #define RAETH_RX_CALC_IDX3 RX_CALC_IDX3 |
| 1336 | #define RAETH_FE_INT_STATUS FE_INT_STATUS |
| 1337 | #define RAETH_FE_INT_ALL FE_INT_ALL |
| 1338 | #define RAETH_FE_INT_ENABLE FE_INT_ENABLE |
| 1339 | #define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT |
| 1340 | #define RAETH_FE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | \ |
| 1341 | TX_DONE_INT0 | TX_DONE_INT1 | \ |
| 1342 | TX_DONE_INT2 | TX_DONE_INT3) |
| 1343 | #define QFE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | \ |
| 1344 | TX_DONE_INT0 | TX_DONE_INT1 | \ |
| 1345 | TX_DONE_INT2 | TX_DONE_INT3) |
| 1346 | #define RAETH_TX_DLY_INT TX_DLY_INT |
| 1347 | #define RAETH_TX_DONE_INT0 TX_DONE_INT0 |
| 1348 | #define RAETH_DLY_INT_CFG DLY_INT_CFG |
| 1349 | |
| 1350 | /* io-coherent for ethdmasys */ |
| 1351 | #define IOC_ETH_PDMA BIT(0) |
| 1352 | #define IOC_ETH_QDMA BIT(1) |
| 1353 | |
| 1354 | #endif /* RAETH_REG_H */ |