| developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From 9ec485a8a2002d6625b8b43158887ecac572ce76 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:34 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [uncategorized][999-2900-dts-mt7622-enable-new-mtk-snand-for-ubi.patch] |
| 6 | |
| 7 | --- |
| 8 | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 14 ++++++++++++++ |
| 9 | 1 file changed, 14 insertions(+) |
| 10 | |
| 11 | diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
| 12 | index 988c31403..d7f147414 100644 |
| 13 | --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
| 14 | +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
| 15 | @@ -568,6 +568,20 @@ |
| 16 | status = "disabled"; |
| 17 | }; |
| 18 | |
| 19 | + snand: snfi@1100d000 { |
| 20 | + compatible = "mediatek,mt7622-snand"; |
| 21 | + reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>; |
| 22 | + reg-names = "nfi", "ecc"; |
| 23 | + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; |
| 24 | + clocks = <&pericfg CLK_PERI_NFI_PD>, |
| 25 | + <&pericfg CLK_PERI_SNFI_PD>, |
| 26 | + <&pericfg CLK_PERI_NFIECC_PD>; |
| 27 | + clock-names = "nfi_clk", "pad_clk", "ecc_clk"; |
| 28 | + #address-cells = <1>; |
| 29 | + #size-cells = <0>; |
| 30 | + status = "disabled"; |
| 31 | + }; |
| 32 | + |
| 33 | nor_flash: spi@11014000 { |
| 34 | compatible = "mediatek,mt7622-nor", |
| 35 | "mediatek,mt8173-nor"; |
| 36 | -- |
| 37 | 2.34.1 |
| 38 | |