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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 35a6c72e9b1a51853d51114d2441221889b12098 / . / target / linux / mediatek / patches-5.4 / 999-2721-net-mt753x-phy-coverity-scan.patch
blob: a9b1316ad39e79de2d85238177414e620da68677 [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]1From 520aea1caf199f454a0988f23d000c18256caa2b Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:32 +0800
4Subject: [PATCH] [networking][999-2721-net-mt753x-phy-coverity-scan.patch]
5
6---
7 drivers/net/phy/mtk/mt753x/mt753x_common.c | 3 ++
8 drivers/net/phy/mtk/mt753x/mt753x_phy.c | 56 +++++++++++-----------
9 2 files changed, 32 insertions(+), 27 deletions(-)
10
11diff --git a/drivers/net/phy/mtk/mt753x/mt753x_common.c b/drivers/net/phy/mtk/mt753x/mt753x_common.c
12index 4015ddf12..0e08c8532 100644
13--- a/drivers/net/phy/mtk/mt753x/mt753x_common.c
14+++ b/drivers/net/phy/mtk/mt753x/mt753x_common.c
15@@ -49,6 +49,9 @@ static void display_port_link_status(struct gsw_mt753x *gsw, u32 port)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]16 case MAC_SPD_2500:
17 speed = "2.5Gbps";
18 break;
19+ default:
20+ dev_info(gsw->dev, "Invalid speed\n");
21+ return;
22 }
23
24 if (pmsr & MAC_LNK_STS) {
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]25diff --git a/drivers/net/phy/mtk/mt753x/mt753x_phy.c b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
26index 0c6f9c930..afc46cdd8 100644
27--- a/drivers/net/phy/mtk/mt753x/mt753x_phy.c
28+++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
29@@ -141,7 +141,7 @@ int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]30 u16 dev1e_17a_tmp, dev1e_e0_tmp;
31
32 /* *** Iext/Rext Cal start ************ */
33- all_ana_cal_status = ANACAL_INIT;
34+ //all_ana_cal_status = ANACAL_INIT;
35 /* analog calibration enable, Rext calibration enable */
36 /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
37 /* 1e_dc[0]:rg_txvos_calen */
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]38@@ -185,7 +185,7 @@ int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]39 all_ana_cal_status = ANACAL_FINISH;
40 //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
41 } else {
42- dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
43+ //dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
44 dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
45 if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
46 all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]47@@ -580,33 +580,35 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]48 } else if (phyaddr == 1) {
49 if (calibration_pair == ANACAL_PAIR_A)
50 tx_amp_temp = tx_amp_temp - 1;
51- else if(calibration_pair == ANACAL_PAIR_B)
52- tx_amp_temp = tx_amp_temp ;
53+ //else if(calibration_pair == ANACAL_PAIR_B)
54+ // tx_amp_temp = tx_amp_temp;
55 else if(calibration_pair == ANACAL_PAIR_C)
56 tx_amp_temp = tx_amp_temp - 1;
57 else if(calibration_pair == ANACAL_PAIR_D)
58 tx_amp_temp = tx_amp_temp - 1;
59 } else if (phyaddr == 2) {
60- if (calibration_pair == ANACAL_PAIR_A)
61- tx_amp_temp = tx_amp_temp;
62- else if(calibration_pair == ANACAL_PAIR_B)
63+ //if (calibration_pair == ANACAL_PAIR_A)
64+ // tx_amp_temp = tx_amp_temp;
65+ //else if(calibration_pair == ANACAL_PAIR_B)
66+ if(calibration_pair == ANACAL_PAIR_B)
67 tx_amp_temp = tx_amp_temp - 1;
68- else if(calibration_pair == ANACAL_PAIR_C)
69- tx_amp_temp = tx_amp_temp;
70+ //else if(calibration_pair == ANACAL_PAIR_C)
71+ // tx_amp_temp = tx_amp_temp;
72 else if(calibration_pair == ANACAL_PAIR_D)
73 tx_amp_temp = tx_amp_temp - 1;
74- } else if (phyaddr == 3) {
75- tx_amp_temp = tx_amp_temp;
76+ //} else if (phyaddr == 3) {
77+ // tx_amp_temp = tx_amp_temp;
78 } else if (phyaddr == 4) {
79- if (calibration_pair == ANACAL_PAIR_A)
80- tx_amp_temp = tx_amp_temp;
81- else if(calibration_pair == ANACAL_PAIR_B)
82+ //if (calibration_pair == ANACAL_PAIR_A)
83+ // tx_amp_temp = tx_amp_temp;
84+ //else if(calibration_pair == ANACAL_PAIR_B)
85+ if(calibration_pair == ANACAL_PAIR_B)
86 tx_amp_temp = tx_amp_temp - 1;
87- else if(calibration_pair == ANACAL_PAIR_C)
88- tx_amp_temp = tx_amp_temp;
89- else if(calibration_pair == ANACAL_PAIR_D)
90- tx_amp_temp = tx_amp_temp;
91- }
92+ //else if(calibration_pair == ANACAL_PAIR_C)
93+ // tx_amp_temp = tx_amp_temp;
94+ //else if(calibration_pair == ANACAL_PAIR_D)
95+ // tx_amp_temp = tx_amp_temp;
96+ }
97 reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
98 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
99 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]100@@ -704,7 +706,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]101 reg_backup = 0x0000;
102 reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
103 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
104- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
105+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
106 //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
107 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
108 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]109@@ -712,7 +714,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]110 reg_backup = (reg_backup & (~0x3f));
111 reg_backup |= (reg_tmp << 0);
112 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
113- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
114+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
115 //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
116 }
117 else if(calibration_pair == ANACAL_PAIR_B){
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]118@@ -722,7 +724,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]119 reg_backup = 0x0000;
120 reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
121 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
122- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
123+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
124 //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
125 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
126 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]127@@ -730,7 +732,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]128 reg_backup = (reg_backup & (~0x3f));
129 reg_backup |= (reg_tmp << 0);
130 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
131- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
132+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
133 //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
134 }
135 else if(calibration_pair == ANACAL_PAIR_C){
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]136@@ -740,7 +742,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]137 reg_backup = (reg_backup & (~0x3f00));
138 reg_backup |= (reg_tmp << 8);
139 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
140- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
141+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
142 //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
143 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
144 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]145@@ -748,7 +750,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]146 reg_backup = (reg_backup & (~0x3f));
147 reg_backup |= (reg_tmp << 0);
148 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
149- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
150+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
151 //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
152 }
153 else if(calibration_pair == ANACAL_PAIR_D){
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]154@@ -758,7 +760,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]155 reg_backup = (reg_backup & (~0x3f00));
156 reg_backup |= (reg_tmp << 8);
157 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
158- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
159+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
160 //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
161 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
162 reg_tmp = ((reg_backup & 0x3f) >> 0);
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]163@@ -766,7 +768,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]164 reg_backup = (reg_backup & (~0x3f));
165 reg_backup |= (reg_tmp << 0);
166 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
167- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
168+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
169 //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
170 }
171
developer5d148cb2023-06-02 13:08:11 +0800[diff] [blame]172--
1732.34.1
174