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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 34d9713f612ab76ac4bdc4cd4de30f355a6017ab / . / openwrt_patches-21.02 / 411-master-mt76-internaldebug.patch
blob: b6bbaf62aef063a75d3ffb6ca90848da75770a4e [file] [log] [blame]
developer1b2cb9a2021-12-21 00:57:14 +0800[diff] [blame]1diff --git a/package/kernel/mt76/patches/1001-mtk-internal-add-internal-debug-tools-for-mt76.patch b/package/kernel/mt76/patches/1001-mtk-internal-add-internal-debug-tools-for-mt76.patch
2new file mode 100644
3index 0000000..842b426
4--- /dev/null
5+++ b/package/kernel/mt76/patches/1001-mtk-internal-add-internal-debug-tools-for-mt76.patch
6@@ -0,0 +1,3323 @@
7+From b2469ddf76fecb0c1fe809ef1350f939248eaeaf Mon Sep 17 00:00:00 2001
8+From: Shayne Chen <shayne.chen@mediatek.com>
9+Date: Mon, 14 Dec 2020 11:19:32 +0800
10+Subject: [PATCH 1/4] mtk-internal: add internal debug tools for mt76
11+
12+Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
13+---
14+ mt7915/Makefile | 2 +
15+ mt7915/debugfs.c | 4 +
16+ mt7915/mac.c | 5 +
17+ mt7915/mac.h | 3 +
18+ mt7915/mcu.c | 6 +
19+ mt7915/mt7915.h | 25 +
20+ mt7915/mt7915_debug.h | 541 +++++++++++
21+ mt7915/mtk_debugfs.c | 2097 +++++++++++++++++++++++++++++++++++++++++
22+ mt7915/mtk_mcu.c | 485 ++++++++++
23+ mt7915/regs.h | 11 +
24+ 10 files changed, 3179 insertions(+)
25+ create mode 100644 mt7915/mt7915_debug.h
26+ create mode 100644 mt7915/mtk_debugfs.c
27+ create mode 100644 mt7915/mtk_mcu.c
28+
29+diff --git a/mt7915/Makefile b/mt7915/Makefile
30+index 40c80617..9511009d 100644
31+--- a/mt7915/Makefile
32++++ b/mt7915/Makefile
33+@@ -6,3 +6,5 @@ mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
34+ debugfs.o mmio.o
35+
36+ mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
37++
38++mt7915e-y += mtk_debugfs.o mtk_mcu.o
39+diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
40+index a15aa256..f3e4d9f2 100644
41+--- a/mt7915/debugfs.c
42++++ b/mt7915/debugfs.c
43+@@ -554,6 +554,10 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
44+ &fops_radar_trigger);
45+ }
46+
47++#ifdef MTK_DEBUG
48++ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
49++ mt7915_mtk_init_debugfs(phy, dir);
50++#endif
51+ return 0;
52+ }
53+
54+diff --git a/mt7915/mac.c b/mt7915/mac.c
55+index a1556fe2..6d5ec580 100644
56+--- a/mt7915/mac.c
57++++ b/mt7915/mac.c
58+@@ -1642,6 +1642,11 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
59+ mt7915_mac_add_txs(dev, rxd);
60+ dev_kfree_skb(skb);
61+ break;
62++#ifdef MTK_DEBUG
63++ case PKT_TYPE_RX_ICS:
64++ mt7915_mcu_rx_ics(dev, skb);
65++ break;
66++#endif
67+ case PKT_TYPE_NORMAL:
68+ if (!mt7915_mac_fill_rx(dev, skb)) {
69+ mt76_rx(&dev->mt76, q, skb);
70+diff --git a/mt7915/mac.h b/mt7915/mac.h
71+index 7a2c740d..15f43418 100644
72+--- a/mt7915/mac.h
73++++ b/mt7915/mac.h
74+@@ -23,6 +23,9 @@ enum rx_pkt_type {
75+ PKT_TYPE_RETRIEVE,
76+ PKT_TYPE_TXRX_NOTIFY,
77+ PKT_TYPE_RX_EVENT,
78++#ifdef MTK_DEBUG
79++ PKT_TYPE_RX_ICS = 0xc
80++#endif
81+ };
82+
83+ /* RXD DW1 */
84+diff --git a/mt7915/mcu.c b/mt7915/mcu.c
85+index 73a11448..3ef873f7 100644
86+--- a/mt7915/mcu.c
87++++ b/mt7915/mcu.c
88+@@ -487,6 +487,7 @@ mt7915_mcu_rx_radar_detected(struct mt7915_dev *dev, struct sk_buff *skb)
89+ dev->hw_pattern++;
90+ }
91+
92++#ifndef MTK_DEBUG
93+ static void
94+ mt7915_mcu_rx_log_message(struct mt7915_dev *dev, struct sk_buff *skb)
95+ {
96+@@ -509,6 +510,7 @@ mt7915_mcu_rx_log_message(struct mt7915_dev *dev, struct sk_buff *skb)
97+ wiphy_info(mt76_hw(dev)->wiphy, "%s: %.*s", type,
98+ (int)(skb->len - sizeof(*rxd)), data);
99+ }
100++#endif
101+
102+ static void
103+ mt7915_mcu_cca_finish(void *priv, u8 *mac, struct ieee80211_vif *vif)
104+@@ -535,7 +537,11 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
105+ mt7915_mcu_rx_csa_notify(dev, skb);
106+ break;
107+ case MCU_EXT_EVENT_FW_LOG_2_HOST:
108++#ifdef MTK_DEBUG
109++ mt7915_mcu_rx_log_message_internal(dev, skb);
110++#else
111+ mt7915_mcu_rx_log_message(dev, skb);
112++#endif
113+ break;
114+ case MCU_EXT_EVENT_BCC_NOTIFY:
115+ ieee80211_iterate_active_interfaces_atomic(dev->mt76.hw,
116+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
117+index c6c846d1..bbfaa617 100644
118+--- a/mt7915/mt7915.h
119++++ b/mt7915/mt7915.h
120+@@ -9,6 +9,7 @@
121+ #include "../mt76.h"
122+ #include "regs.h"
123+
124++#define MTK_DEBUG 1
125+ #define MT7915_MAX_INTERFACES 19
126+ #define MT7915_MAX_WMM_SETS 4
127+ #define MT7915_WTBL_SIZE 288
128+@@ -283,6 +284,25 @@ struct mt7915_dev {
129+ u8 table_mask;
130+ u8 n_agrt;
131+ } twt;
132++
133++#ifdef MTK_DEBUG
134++ u16 wlan_idx;
135++ struct {
136++ u16 eep_idx;
137++ u32 fixed_rate;
138++ u32 l1debugfs_reg;
139++ u32 l2debugfs_reg;
140++ u32 mac_reg;
141++ u8 fw_debug;
142++ u32 fw_dbg_module;
143++ u8 fw_dbg_lv;
144++ u8 fwlog_server_mac[ETH_ALEN];
145++ u32 fwlog_server_ip;
146++ char fwlog_ifname[10];
147++ u32 bcn_total_cnt[2];
148++ u16 fwlog_seq;
149++ } dbg;
150++#endif
151+ };
152+
153+ enum {
154+@@ -532,4 +552,9 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
155+ struct ieee80211_sta *sta, struct dentry *dir);
156+ #endif
157+
158++#ifdef MTK_DEBUG
159++int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
160++void mt7915_mcu_rx_log_message_internal(struct mt7915_dev *dev, struct sk_buff *skb);
161++void mt7915_mcu_rx_ics(struct mt7915_dev *dev, struct sk_buff *skb);
162++#endif
163+ #endif
164+diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
165+new file mode 100644
166+index 00000000..ff8fe503
167+--- /dev/null
168++++ b/mt7915/mt7915_debug.h
169+@@ -0,0 +1,541 @@
170++#ifndef __MT7915_DEBUG_H
171++#define __MT7915_DEBUG_H
172++
173++#ifdef MTK_DEBUG
174++
175++#define CONN_INFRA_REMAPPING_OFFSET 0x64000000
176++#define WF_WFDMA_HOST_DMA0_BASE (0x18024000 + CONN_INFRA_REMAPPING_OFFSET)
177++#define WF_WFDMA_HOST_DMA0_PCI_BASE(addr) (addr - WF_WFDMA_HOST_DMA0_BASE + 0xd4000)
178++
179++#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x200) // 4200
180++#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0X204) // 4204
181++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x208) // 4208
182++
183++#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x500) // 4500
184++#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x510) // 4510
185++
186++#define MT_DMA0_R0_RING_BASE WF_WFDMA_HOST_DMA0_PCI_BASE(WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR)
187++#define MT_DMA0_R1_RING_BASE WF_WFDMA_HOST_DMA0_PCI_BASE(WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR)
188++
189++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
190++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
191++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
192++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
193++
194++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
195++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
196++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
197++#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
198++
199++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_rx_don_int_sts_0_MASK 0x00010000 // host_dma0_rx_don_int_sts_0[16]
200++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_rx_don_int_sts_1_MASK 0x00020000 // host_dma0_rx_don_int_sts_1[17]
201++#define MT_INT_DMA0_R0_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_rx_don_int_sts_0_MASK
202++#define MT_INT_DMA0_R1_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_rx_don_int_sts_1_MASK
203++
204++#define WF_WFDMA_HOST_DMA1_BASE (0x18025000 + CONN_INFRA_REMAPPING_OFFSET)
205++#define WF_WFDMA_HOST_DMA1_PCI_BASE(addr) (addr - WF_WFDMA_HOST_DMA1_BASE + 0xd5000)
206++
207++#define WF_WFDMA_HOST_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x200) // 5200
208++#define WF_WFDMA_HOST_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0X204) // 5204
209++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x208) // 5208
210++
211++#define WF_WFDMA_HOST_DMA1_WPDMA_TX_RING16_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x400) // 5400
212++#define WF_WFDMA_HOST_DMA1_WPDMA_TX_RING17_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x410) // 5410
213++#define WF_WFDMA_HOST_DMA1_WPDMA_TX_RING18_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x420) // 5420
214++#define WF_WFDMA_HOST_DMA1_WPDMA_TX_RING19_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x430) // 5430
215++#define WF_WFDMA_HOST_DMA1_WPDMA_TX_RING20_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x440) // 5440
216++#define WF_WFDMA_HOST_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x500) // 5500
217++#define WF_WFDMA_HOST_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x510) // 5510
218++#define WF_WFDMA_HOST_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_BASE + 0x520) // 5520
219++
220++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
221++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
222++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
223++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
224++
225++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
226++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
227++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
228++#define WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
229++
230++#define MT_DMA1_T16_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_TX_RING16_CTRL0_ADDR)
231++#define MT_DMA1_T17_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_TX_RING17_CTRL0_ADDR)
232++#define MT_DMA1_T18_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_TX_RING18_CTRL0_ADDR)
233++#define MT_DMA1_T19_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_TX_RING19_CTRL0_ADDR)
234++#define MT_DMA1_T20_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_TX_RING20_CTRL0_ADDR)
235++#define MT_DMA1_R0_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_RX_RING0_CTRL0_ADDR)
236++#define MT_DMA1_R1_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_RX_RING1_CTRL0_ADDR)
237++#define MT_DMA1_R2_RING_BASE WF_WFDMA_HOST_DMA1_PCI_BASE(WF_WFDMA_HOST_DMA1_WPDMA_RX_RING2_CTRL0_ADDR)
238++
239++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_0_MASK 0x00000001 // host_dma1_rx_done_int_sts_0[0]
240++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_1_MASK 0x00000002 // host_dma1_rx_done_int_sts_1[1]
241++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_2_MASK 0x00000004 // host_dma1_rx_done_int_sts_2[2]
242++
243++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_20_MASK 0x00008000 // host_dma1_tx_done_int_sts_20[15]
244++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_19_MASK 0x80000000 // host_dma1_tx_done_int_sts_19[31]
245++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_18_MASK 0x40000000 // host_dma1_tx_done_int_sts_18[30]
246++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_17_MASK 0x08000000 // host_dma1_tx_done_int_sts_17[27]
247++#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_16_MASK 0x04000000 // host_dma1_tx_done_int_sts_16[26]
248++
249++#define MT_INT_DMA1_R0_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_0_MASK
250++#define MT_INT_DMA1_R1_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_1_MASK
251++#define MT_INT_DMA1_R2_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_2_MASK
252++
253++#define MT_INT_DMA1_T16_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_16_MASK
254++#define MT_INT_DMA1_T17_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_17_MASK
255++#define MT_INT_DMA1_T18_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_18_MASK
256++#define MT_INT_DMA1_T19_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_19_MASK
257++#define MT_INT_DMA1_T20_DONE WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_20_MASK
258++
259++
260++#define WF_WFDMA_EXT_WRAP_CSR_BASE (0x18027000 + CONN_INFRA_REMAPPING_OFFSET)
261++#define WF_WFDMA_EXT_WRAP_CSR_PCI_BASE(addr) (addr - WF_WFDMA_EXT_WRAP_CSR_BASE + 0xd7000)
262++
263++#define WF_WFDMA_EXT_WRAP_CSR_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_EXT_WRAP_CSR_BASE + 0x88) // 7088
264++#define WF_WFDMA_EXT_WRAP_CSR_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_EXT_WRAP_CSR_BASE + 0x8C) // 708C
265++
266++#define WF_WFDMA_HOST_DMA0_PCIE1_BASE (0x18028000 + CONN_INFRA_REMAPPING_OFFSET)
267++#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x200) // 8200
268++#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0X204) // 8204
269++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x208) // 8208
270++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
271++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
272++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
273++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
274++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
275++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
276++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
277++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
278++#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x510) // 8510
279++
280++#define WF_WFDMA_HOST_DMA1_PCIE1_BASE (0x18029000 + CONN_INFRA_REMAPPING_OFFSET)
281++#define WF_WFDMA_HOST_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA1_PCIE1_BASE + 0x200) // 9200
282++#define WF_WFDMA_HOST_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA1_PCIE1_BASE + 0X204) // 9204
283++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA1_PCIE1_BASE + 0x208) // 9208
284++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
285++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
286++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
287++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
288++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
289++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
290++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
291++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
292++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_TX_RING19_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_PCIE1_BASE + 0x330) // 9330
293++#define WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_HOST_DMA1_PCIE1_BASE + 0x520) // 9520
294++
295++#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
296++#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
297++#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
298++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
299++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
300++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
301++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
302++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
303++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
304++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
305++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
306++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
307++
308++#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
309++#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
310++#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
311++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
312++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
313++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
314++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
315++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
316++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
317++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
318++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
319++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
320++#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
321++#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
322++#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
323++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
324++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
325++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
326++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
327++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
328++
329++#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
330++#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
331++#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
332++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
333++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
334++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
335++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
336++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
337++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
338++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
339++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
340++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
341++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
342++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
343++
344++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
345++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
346++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
347++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
348++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
349++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
350++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
351++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
352++
353++
354++#define WF_WFDMA_MEM_DMA_BASE 0x58000000
355++#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
356++#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
357++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
358++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
359++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
360++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
361++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
362++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
363++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
364++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
365++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
366++#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
367++#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
368++#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
369++#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
370++
371++enum resource_attr {
372++ HIF_TX_DATA,
373++ HIF_TX_CMD,
374++ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
375++ HIF_TX_FWDL,
376++ HIF_RX_DATA,
377++ HIF_RX_EVENT,
378++ RING_ATTR_NUM
379++};
380++
381++struct hif_pci_tx_ring_desc {
382++ u32 hw_desc_base;
383++ u32 hw_int_mask;
384++ u16 ring_size;
385++ enum resource_attr ring_attr;
386++ u8 band_idx;
387++ char *const ring_info;
388++};
389++
390++struct hif_pci_rx_ring_desc {
391++ u32 hw_desc_base;
392++ u32 hw_int_mask;
393++ u16 ring_size;
394++ enum resource_attr ring_attr;
395++ u16 max_rx_process_cnt;
396++ u16 max_sw_read_idx_inc;
397++ char *const ring_info;
398++};
399++
400++
401++const struct hif_pci_tx_ring_desc tx_ring_layout[] = {
402++ {
403++ .hw_desc_base = MT_DMA1_T18_RING_BASE,
404++ .hw_int_mask = MT_INT_DMA1_T18_DONE,
405++ .ring_size = 2048,
406++ .ring_attr = HIF_TX_DATA,
407++ .ring_info = "band0 TXD"
408++ },
409++ {
410++ .hw_desc_base = MT_DMA1_T19_RING_BASE,
411++ .hw_int_mask = MT_INT_DMA1_T19_DONE,
412++ .ring_size = 2048,
413++ .ring_attr = HIF_TX_DATA,
414++ .ring_info = "band1 TXD"
415++ },
416++ {
417++ .hw_desc_base = MT_DMA1_T16_RING_BASE,
418++ .hw_int_mask = MT_INT_DMA1_T16_DONE,
419++ .ring_size = 128,
420++ .ring_attr = HIF_TX_FWDL,
421++ .ring_info = "FWDL"
422++ },
423++ {
424++ .hw_desc_base = MT_DMA1_T17_RING_BASE,
425++ .hw_int_mask = MT_INT_DMA1_T17_DONE,
426++ .ring_size = 256,
427++ .ring_attr = HIF_TX_CMD_WM,
428++ .ring_info = "cmd to WM"
429++ },
430++ {
431++ .hw_desc_base = MT_DMA1_T20_RING_BASE,
432++ .hw_int_mask = MT_INT_DMA1_T20_DONE,
433++ .ring_size = 256,
434++ .ring_attr = HIF_TX_CMD,
435++ .ring_info = "cmd to WA"
436++ }
437++};
438++
439++const struct hif_pci_rx_ring_desc rx_ring_layout[] = {
440++ {
441++ .hw_desc_base = MT_DMA0_R0_RING_BASE,
442++ .hw_int_mask = MT_INT_DMA0_R0_DONE,
443++ .ring_size = 1536,
444++ .ring_attr = HIF_RX_DATA,
445++ .ring_info = "band0 RX data"
446++ },
447++ {
448++ .hw_desc_base = MT_DMA0_R1_RING_BASE,
449++ .hw_int_mask = MT_INT_DMA0_R1_DONE,
450++ .ring_size = 1536,
451++ .ring_attr = HIF_RX_DATA,
452++ .ring_info = "band1 RX data"
453++ },
454++ {
455++ .hw_desc_base = MT_DMA1_R0_RING_BASE,
456++ .hw_int_mask = MT_INT_DMA1_R0_DONE,
457++ .ring_size = 512,
458++ .ring_attr = HIF_RX_EVENT,
459++ .ring_info = "event from WM"
460++ },
461++ {
462++ .hw_desc_base = MT_DMA1_R1_RING_BASE,
463++ .hw_int_mask = MT_INT_DMA1_R1_DONE,
464++ .ring_size = 1024,
465++ .ring_attr = HIF_RX_EVENT,
466++ .ring_info = "event from WA band0"
467++ },
468++ {
469++ .hw_desc_base = MT_DMA1_R2_RING_BASE,
470++ .hw_int_mask = MT_INT_DMA1_R2_DONE,
471++ .ring_size = 512,
472++ .ring_attr = HIF_RX_EVENT,
473++ .ring_info = "event from WA band1"
474++ }
475++};
476++
477++/* pleinfo related CRs. */
478++#define WF_PLE_TOP_BASE 0x820C0000
479++
480++#define WF_PLE_TOP_PBUF_CTRL_ADDR (WF_PLE_TOP_BASE + 0x14) // 0014
481++#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31]
482++#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31
483++#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17]
484++#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17
485++#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0]
486++#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0
487++#define WF_PLE_TOP_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0xB0) // 00B0
488++#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK 0x01000000 // ALL_AC_EMPTY[24]
489++#define WF_PLE_TOP_FREEPG_CNT_ADDR (WF_PLE_TOP_BASE + 0x100) // 0100
490++#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16]
491++#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16
492++#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0]
493++#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0
494++#define WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PLE_TOP_BASE + 0x104) // 0104
495++#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16]
496++#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16
497++#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0]
498++#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0
499++#define WF_PLE_TOP_PG_HIF_GROUP_ADDR (WF_PLE_TOP_BASE + 0x110) // 0110
500++#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK 0x0FFF0000 // HIF_MAX_QUOTA[27..16]
501++#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT 16
502++#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK 0x00000FFF // HIF_MIN_QUOTA[11..0]
503++#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT 0
504++#define WF_PLE_TOP_HIF_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x114) // 0114
505++#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK 0x0FFF0000 // HIF_SRC_CNT[27..16]
506++#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT 16
507++#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK 0x00000FFF // HIF_RSV_CNT[11..0]
508++#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT 0
509++#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x120) // 0120
510++#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK 0x0FFF0000 // HIF_TXCMD_MAX_QUOTA[27..16]
511++#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT 16
512++#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK 0x00000FFF // HIF_TXCMD_MIN_QUOTA[11..0]
513++#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT 0
514++#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x124) // 0124
515++#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK 0x0FFF0000 // HIF_TXCMD_SRC_CNT[27..16]
516++#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT 16
517++#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK 0x00000FFF // HIF_TXCMD_RSV_CNT[11..0]
518++#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT 0
519++#define WF_PLE_TOP_PG_CPU_GROUP_ADDR (WF_PLE_TOP_BASE + 0x150) // 0150
520++#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16]
521++#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16
522++#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0]
523++#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0
524++#define WF_PLE_TOP_CPU_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x154) // 0154
525++#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16]
526++#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16
527++#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0]
528++#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0
529++#define WF_PLE_TOP_FL_QUE_CTRL_0_ADDR (WF_PLE_TOP_BASE + 0x1B0) // 01B0
530++#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31]
531++#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24]
532++#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
533++#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_MASK 0x00000C00 // Q_BUF_PID[11..10]
534++#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
535++#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0
536++#define WF_PLE_TOP_FL_QUE_CTRL_1_ADDR (WF_PLE_TOP_BASE + 0x1B4) // 01B4
537++#define WF_PLE_TOP_FL_QUE_CTRL_2_ADDR (WF_PLE_TOP_BASE + 0x1B8) // 01B8
538++#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16]
539++#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16
540++#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0]
541++#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0
542++#define WF_PLE_TOP_FL_QUE_CTRL_3_ADDR (WF_PLE_TOP_BASE + 0x1BC) // 01BC
543++#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0]
544++#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0
545++#define WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x22c) // 022C
546++#define WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x230) // 0230
547++#define WF_PLE_TOP_STATION_PAUSE0_ADDR (WF_PLE_TOP_BASE + 0x400) // 0400
548++#define WF_PLE_TOP_STATION_PAUSE1_ADDR (WF_PLE_TOP_BASE + 0x404) // 0404
549++#define WF_PLE_TOP_STATION_PAUSE2_ADDR (WF_PLE_TOP_BASE + 0x408) // 0408
550++#define WF_PLE_TOP_STATION_PAUSE3_ADDR (WF_PLE_TOP_BASE + 0x40c) // 040C
551++#define WF_PLE_TOP_STATION_PAUSE4_ADDR (WF_PLE_TOP_BASE + 0x410) // 0410
552++#define WF_PLE_TOP_STATION_PAUSE5_ADDR (WF_PLE_TOP_BASE + 0x414) // 0414
553++#define WF_PLE_TOP_STATION_PAUSE6_ADDR (WF_PLE_TOP_BASE + 0x418) // 0418
554++#define WF_PLE_TOP_STATION_PAUSE7_ADDR (WF_PLE_TOP_BASE + 0x41c) // 041C
555++#define WF_PLE_TOP_STATION_PAUSE8_ADDR (WF_PLE_TOP_BASE + 0x420) // 0420
556++#define WF_PLE_TOP_DIS_STA_MAP0_ADDR (WF_PLE_TOP_BASE + 0x440) // 0440
557++#define WF_PLE_TOP_DIS_STA_MAP1_ADDR (WF_PLE_TOP_BASE + 0x444) // 0444
558++#define WF_PLE_TOP_DIS_STA_MAP2_ADDR (WF_PLE_TOP_BASE + 0x448) // 0448
559++#define WF_PLE_TOP_DIS_STA_MAP3_ADDR (WF_PLE_TOP_BASE + 0x44c) // 044C
560++#define WF_PLE_TOP_DIS_STA_MAP4_ADDR (WF_PLE_TOP_BASE + 0x450) // 0450
561++#define WF_PLE_TOP_DIS_STA_MAP5_ADDR (WF_PLE_TOP_BASE + 0x454) // 0454
562++#define WF_PLE_TOP_DIS_STA_MAP6_ADDR (WF_PLE_TOP_BASE + 0x458) // 0458
563++#define WF_PLE_TOP_DIS_STA_MAP7_ADDR (WF_PLE_TOP_BASE + 0x45c) // 045C
564++#define WF_PLE_TOP_DIS_STA_MAP8_ADDR (WF_PLE_TOP_BASE + 0x460) // 0460
565++#define WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x500) // 0500
566++#define WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x504) // 0504
567++#define WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x508) // 0508
568++#define WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x50c) // 050C
569++#define WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x510) // 0510
570++#define WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x514) // 0514
571++#define WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x518) // 0518
572++#define WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x51c) // 051C
573++#define WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x520) // 0520
574++#define WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x540) // 0540
575++#define WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x544) // 0544
576++#define WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x548) // 0548
577++#define WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x54c) // 054C
578++#define WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x550) // 0550
579++#define WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x554) // 0554
580++#define WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x558) // 0558
581++#define WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x55c) // 055C
582++#define WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x560) // 0560
583++#define WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x580) // 0580
584++#define WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x584) // 0584
585++#define WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x588) // 0588
586++#define WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x58c) // 058C
587++#define WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x590) // 0590
588++#define WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x594) // 0594
589++#define WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x598) // 0598
590++#define WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x59c) // 059C
591++#define WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x5a0) // 05A0
592++#define WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x5c0) // 05C0
593++#define WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x5c4) // 05C4
594++#define WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x5c8) // 05C8
595++#define WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x5cc) // 05CC
596++#define WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x5d0) // 05D0
597++#define WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x5d4) // 05D4
598++#define WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x5d8) // 05D8
599++#define WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x5dc) // 05DC
600++#define WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x5e0) // 05E0
601++
602++/* mibinfo related CRs. */
603++#define BN0_WF_MIB_TOP_BASE 0x820ed000
604++#define BN1_WF_MIB_TOP_BASE 0x820fd000
605++
606++#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x00) // D000
607++#define BN0_WF_MIB_TOP_M0PBSCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x04) // D004
608++#define BN0_WF_MIB_TOP_M0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x10) // D010
609++#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
610++#define BN0_WF_MIB_TOP_M0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x14) // D014
611++#define BN0_WF_MIB_TOP_M0SDR3_RX_FCS_ERROR_COUNT_MASK 0x0000FFFF // RX_FCS_ERROR_COUNT[15..0]
612++#define BN0_WF_MIB_TOP_M0SDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x18) // D018
613++#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
614++#define BN0_WF_MIB_TOP_M0SDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x1C) // D01C
615++#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
616++#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x20) // D020
617++#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
618++#define BN0_WF_MIB_TOP_M0SDR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x24) // D024
619++#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
620++#define BN0_WF_MIB_TOP_M0SDR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x28) // D028
621++#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
622++#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x2C) // D02C
623++#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
624++#define BN0_WF_MIB_TOP_M0SDR10_ADDR (BN0_WF_MIB_TOP_BASE + 0x30) // D030
625++#define BN0_WF_MIB_TOP_M0SDR10_RX_MDRDY_COUNT_MASK 0x03FFFFFF // RX_MDRDY_COUNT[25..0]
626++#define BN0_WF_MIB_TOP_M0SDR11_ADDR (BN0_WF_MIB_TOP_BASE + 0x34) // D034
627++#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
628++#define BN0_WF_MIB_TOP_M0SDR12_ADDR (BN0_WF_MIB_TOP_BASE + 0x38) // D038
629++#define BN0_WF_MIB_TOP_M0SDR14_ADDR (BN0_WF_MIB_TOP_BASE + 0x40) // D040
630++#define BN0_WF_MIB_TOP_M0SDR14_AMPDU_MPDU_COUNT_MASK 0x00FFFFFF // AMPDU_MPDU_COUNT[23..0]
631++#define BN0_WF_MIB_TOP_M0SDR15_ADDR (BN0_WF_MIB_TOP_BASE + 0x44) // D044
632++#define BN0_WF_MIB_TOP_M0SDR15_AMPDU_ACKED_COUNT_MASK 0x00FFFFFF // AMPDU_ACKED_COUNT[23..0]
633++#define BN0_WF_MIB_TOP_M0SDR16_ADDR (BN0_WF_MIB_TOP_BASE + 0x48) // D048
634++#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
635++#define BN0_WF_MIB_TOP_M0SDR17_ADDR (BN0_WF_MIB_TOP_BASE + 0x4C) // D04C
636++#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
637++#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x50) // D050
638++#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
639++#define BN0_WF_MIB_TOP_M0SDR19_ADDR (BN0_WF_MIB_TOP_BASE + 0x54) // D054
640++#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
641++#define BN0_WF_MIB_TOP_M0SDR20_ADDR (BN0_WF_MIB_TOP_BASE + 0x58) // D058
642++#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
643++#define BN0_WF_MIB_TOP_M0SDR21_ADDR (BN0_WF_MIB_TOP_BASE + 0x5C) // D05C
644++#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
645++#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
646++#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
647++#define BN0_WF_MIB_TOP_M0SDR34_ADDR (BN0_WF_MIB_TOP_BASE + 0x90) // D090
648++#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
649++#define BN0_WF_MIB_TOP_M0DR0_ADDR (BN0_WF_MIB_TOP_BASE + 0xA0) // D0A0
650++#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
651++#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
652++#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
653++#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
654++#define BN0_WF_MIB_TOP_M0DR1_ADDR (BN0_WF_MIB_TOP_BASE + 0xA4) // D0A4
655++#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
656++#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
657++#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
658++#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
659++#define BN0_WF_MIB_TOP_M0DR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xB8) // D0B8
660++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
661++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
662++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
663++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
664++#define BN0_WF_MIB_TOP_M0DR7_ADDR (BN0_WF_MIB_TOP_BASE + 0xBC) // D0BC
665++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
666++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
667++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
668++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
669++#define BN0_WF_MIB_TOP_M0DR8_ADDR (BN0_WF_MIB_TOP_BASE + 0XC0) // D0C0
670++#define BN0_WF_MIB_TOP_M0DR9_ADDR (BN0_WF_MIB_TOP_BASE + 0XC4) // D0C4
671++#define BN0_WF_MIB_TOP_M0DR10_ADDR (BN0_WF_MIB_TOP_BASE + 0XC8) // D0C8
672++#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
673++#define BN0_WF_MIB_TOP_M0DR11_ADDR (BN0_WF_MIB_TOP_BASE + 0XCC) // D0CC
674++#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
675++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
676++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
677++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
678++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
679++#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
680++#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
681++#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
682++#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
683++#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
684++#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
685++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
686++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
687++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
688++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
689++#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
690++#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
691++#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
692++#define BN0_WF_MIB_TOP_M0DR12_ADDR (BN0_WF_MIB_TOP_BASE + 0x160) // D160
693++#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
694++
695++#define WF_WTBLON_TOP_BASE 0x820D4000
696++#define WF_WTBLON_TOP_B0BTCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1000) // 5000
697++#define WF_WTBLON_TOP_B0BTBCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1010) // 5010
698++#define WF_WTBLON_TOP_B0BRCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1020) // 5020
699++#define WF_WTBLON_TOP_B0BRBCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1030) // 5030
700++#define WF_WTBLON_TOP_B0BTDCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1040) // 5040
701++#define WF_WTBLON_TOP_B0BRDCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1050) // 5050
702++#define WF_WTBLON_TOP_B0MBTCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1100) // 5100
703++#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1140) // 5140
704++#define WF_WTBLON_TOP_B0MBRCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1180) // 5180
705++#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (WF_WTBLON_TOP_BASE + 0x11C0) // 51C0
706++
707++#define WF_WTBLON_TOP_B1BTCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1800) // 5800
708++
709++#endif
710++#endif
711+diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
712+new file mode 100644
713+index 00000000..eaae509a
714+--- /dev/null
715++++ b/mt7915/mtk_debugfs.c
716+@@ -0,0 +1,2097 @@
717++#include<linux/inet.h>
718++#include "mt7915.h"
719++#include "mt7915_debug.h"
720++#include "mac.h"
721++#include "mcu.h"
722++
723++#ifdef MTK_DEBUG
724++
725++u32 mt7915_mac_cr_range[] = {
726++ 0x54000000, 0x02000, 0x1000, /* WFDMA PCIE0 MCU DMA0 */
727++ 0x55000000, 0x03000, 0x1000, /* WFDMA PCIE0 MCU DMA1 */
728++ 0x56000000, 0x04000, 0x1000, /* WFDMA reserved */
729++ 0x57000000, 0x05000, 0x1000, /* WFDMA MCU wrap CR */
730++ 0x58000000, 0x06000, 0x1000, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
731++ 0x59000000, 0x07000, 0x1000, /* WFDMA PCIE1 MCU DMA1 */
732++ 0x820c0000, 0x08000, 0x4000, /* WF_UMAC_TOP (PLE) */
733++ 0x820c8000, 0x0c000, 0x2000, /* WF_UMAC_TOP (PSE) */
734++ 0x820cc000, 0x0e000, 0x2000, /* WF_UMAC_TOP (PP) */
735++ 0x820e0000, 0x20000, 0x0400, /* WF_LMAC_TOP BN0 (WF_CFG) */
736++ 0x820e1000, 0x20400, 0x0200, /* WF_LMAC_TOP BN0 (WF_TRB) */
737++ 0x820e2000, 0x20800, 0x0400, /* WF_LMAC_TOP BN0 (WF_AGG) */
738++ 0x820e3000, 0x20c00, 0x0400, /* WF_LMAC_TOP BN0 (WF_ARB) */
739++ 0x820e4000, 0x21000, 0x0400, /* WF_LMAC_TOP BN0 (WF_TMAC) */
740++ 0x820e5000, 0x21400, 0x0800, /* WF_LMAC_TOP BN0 (WF_RMAC) */
741++ 0x820ce000, 0x21c00, 0x0200, /* WF_LMAC_TOP (WF_SEC) */
742++ 0x820e7000, 0x21e00, 0x0200, /* WF_LMAC_TOP BN0 (WF_DMA) */
743++ 0x820cf000, 0x22000, 0x1000, /* WF_LMAC_TOP (WF_PF) */
744++ 0x820e9000, 0x23400, 0x0200, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
745++ 0x820ea000, 0x24000, 0x0200, /* WF_LMAC_TOP BN0 (WF_ETBF) */
746++ 0x820eb000, 0x24200, 0x0400, /* WF_LMAC_TOP BN0 (WF_LPON) */
747++ 0x820ec000, 0x24600, 0x0200, /* WF_LMAC_TOP BN0 (WF_INT) */
748++ 0x820ed000, 0x24800, 0x0800, /* WF_LMAC_TOP BN0 (WF_MIB) */
749++ 0x820ca000, 0x26000, 0x2000, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
750++ 0x820d0000, 0x30000, 0x10000, /* WF_LMAC_TOP (WF_WTBLON) */
751++ 0x40000000, 0x70000, 0x10000, /* WF_UMAC_SYSRAM */
752++ 0x00400000, 0x80000, 0x10000, /* WF_MCU_SYSRAM */
753++ 0x00410000, 0x90000, 0x10000, /* WF_MCU_SYSRAM (configure register) */
754++ 0x820f0000, 0xa0000, 0x0400, /* WF_LMAC_TOP BN1 (WF_CFG) */
755++ 0x820f1000, 0xa0600, 0x0200, /* WF_LMAC_TOP BN1 (WF_TRB) */
756++ 0x820f2000, 0xa0800, 0x0400, /* WF_LMAC_TOP BN1 (WF_AGG) */
757++ 0x820f3000, 0xa0c00, 0x0400, /* WF_LMAC_TOP BN1 (WF_ARB) */
758++ 0x820f4000, 0xa1000, 0x0400, /* WF_LMAC_TOP BN1 (WF_TMAC) */
759++ 0x820f5000, 0xa1400, 0x0800, /* WF_LMAC_TOP BN1 (WF_RMAC) */
760++ 0x820f7000, 0xa1e00, 0x0200, /* WF_LMAC_TOP BN1 (WF_DMA) */
761++ 0x820f9000, 0xa3400, 0x0200, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
762++ 0x820fa000, 0xa4000, 0x0200, /* WF_LMAC_TOP BN1 (WF_ETBF) */
763++ 0x820fb000, 0xa4200, 0x0400, /* WF_LMAC_TOP BN1 (WF_LPON) */
764++ 0x820fc000, 0xa4600, 0x0200, /* WF_LMAC_TOP BN1 (WF_INT) */
765++ 0x820fd000, 0xa4800, 0x0800, /* WF_LMAC_TOP BN1 (WF_MIB) */
766++ 0x820cc000, 0xa5000, 0x2000, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
767++ 0x820c4000, 0xa8000, 0x4000, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
768++ 0x820b0000, 0xae000, 0x1000, /* [APB2] WFSYS_ON */
769++ 0x80020000, 0xb0000, 0x10000, /* WF_TOP_MISC_OFF */
770++ 0x81020000, 0xc0000, 0x10000, /* WF_TOP_MISC_ON */
771++ 0x7c020000, 0xd0000, 0x10000, /* CONN_INFRA, wfdma */
772++ 0x7c000000, 0xf0000, 0x10000, /* CONN_INFRA */
773++
774++ 0x0, 0x0, 0x100000, /* fixed remap range */
775++ 0x0, 0x0, 0x0, /* imply end of search */
776++};
777++
778++bool mt_mac_cr_range_mapping(struct mt7915_dev *dev, u32 *mac_addr)
779++{
780++ u32 mac_addr_hif = *mac_addr;
781++ int idx = 0;
782++ bool IsFound = false;
783++ do {
784++ if (mac_addr_hif >= mt7915_mac_cr_range[idx] &&
785++ mac_addr_hif < (mt7915_mac_cr_range[idx] +
786++ mt7915_mac_cr_range[idx + 2])) {
787++ mac_addr_hif -= mt7915_mac_cr_range[idx];
788++ mac_addr_hif += mt7915_mac_cr_range[idx + 1];
789++ IsFound = true;
790++ break;
791++ }
792++
793++ idx += 3;
794++ } while (mt7915_mac_cr_range[idx + 2] != 0);
795++
796++ *mac_addr = mac_addr_hif;
797++ return IsFound;
798++}
799++
800++#define CONN_INFRA_PHY_ADDR_START 0x18000000
801++#define CONN_INFRA_PHY_ADDR_END 0x183fffff
802++#define WFSYS_PHY_ADDR_START 0x18400000
803++#define WFSYS_PHY_ADDR_END 0x187fffff
804++#define BGFSYS_PHY_ADDR_START 0x18800000
805++#define BGFSYS_PHY_ADDR_END 0x18bfffff
806++#define CBTOP1_PHY_ADDR_START 0x70000000
807++#define CBTOP1_PHY_ADDR_END 0x77ffffff
808++#define CBTOP2_PHY_ADDR_START 0xf0000000
809++#define CBTOP2_PHY_ADDR_END 0xffffffff
810++
811++#define CONN_INFRA_MCU_ADDR_START 0x7c000000
812++#define CONN_INFRA_MCU_ADDR_END 0x7c3fffff
813++#define CONN_INFRA_MCU_TO_PHY_ADDR_OFFSET (CONN_INFRA_MCU_ADDR_START \
814++ - CONN_INFRA_PHY_ADDR_START)
815++
816++#define IS_CONN_INFRA_PHY_ADDR(_reg) ((_reg) >= CONN_INFRA_PHY_ADDR_START \
817++ && (_reg) <= CONN_INFRA_PHY_ADDR_END)
818++#define IS_WFSYS_PHY_ADDR(_reg) ((_reg) >= WFSYS_PHY_ADDR_START \
819++ && (_reg) <= WFSYS_PHY_ADDR_END)
820++#define IS_BGFSYS_PHY_ADDR(_reg) ((_reg) >= BGFSYS_PHY_ADDR_START \
821++ && (_reg) <= BGFSYS_PHY_ADDR_END)
822++#define IS_CBTOP_PHY_ADDR(_reg) (((_reg) >= CBTOP1_PHY_ADDR_START \
823++ && (_reg) <= CBTOP1_PHY_ADDR_END) \
824++ || ((_reg) >= CBTOP2_PHY_ADDR_START \
825++ && (_reg) <= CBTOP2_PHY_ADDR_END))
826++#define IS_PHY_ADDR(_reg) (IS_CONN_INFRA_PHY_ADDR(_reg) \
827++ || IS_WFSYS_PHY_ADDR(_reg) \
828++ || IS_BGFSYS_PHY_ADDR(_reg) \
829++ || IS_CBTOP_PHY_ADDR(_reg))
830++
831++#define IS_CONN_INFRA_MCU_ADDR(_reg) ((_reg) >= CONN_INFRA_MCU_ADDR_START \
832++ && (_reg) <= CONN_INFRA_MCU_ADDR_END)
833++
834++static bool pci_io_remap_is_l1_remap(u32 *reg)
835++{
836++ /* physical addr shall use layer 1 remap */
837++ if (IS_PHY_ADDR(*reg))
838++ return true;
839++
840++ /* mcu view addr are handled depends on domain */
841++ /* CBTOP: MCU view addr equals to physical addr, already handled */
842++
843++ /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
844++ if (IS_CONN_INFRA_MCU_ADDR(*reg)) {
845++ (*reg) -= CONN_INFRA_MCU_TO_PHY_ADDR_OFFSET;
846++ return true;
847++ }
848++
849++ /* WFSYS: shall use layer 2 remap */
850++ return false;
851++}
852++
853++#define MT_UWTBL_TOP_BASE 0xa8000
854++#define MT_UWTBL_TOP(ofs) (MT_UWTBL_TOP_BASE + (ofs))
855++#define MT_UWTBL_TOP_WDUCR MT_UWTBL_TOP(0x0)
856++#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
857++#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
858++
859++#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
860++#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
861++#define LWTBL_IDX2BASE(_id, _dw) (MT_WTBL_BASE | \
862++ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
863++ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
864++
865++#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
866++#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
867++#define UWTBL_IDX2BASE(_id, _dw) (MT_UWTBL_TOP_BASE | 0x2000 | \
868++ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
869++ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
870++
871++#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
872++#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
873++#define KEYTBL_IDX2BASE(_key, _dw) (MT_UWTBL_TOP_BASE | 0x2000 | \
874++ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
875++ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
876++
877++enum mt7915_wtbl_type {
878++ WTBL_TYPE_LMAC, /* WTBL in LMAC */
879++ WTBL_TYPE_UMAC, /* WTBL in UMAC */
880++ WTBL_TYPE_KEY, /* Key Table */
881++ MAX_NUM_WTBL_TYPE
882++};
883++
884++static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
885++ enum mt7915_wtbl_type type, u16 start_dw,
886++ u16 len, void *buf)
887++{
888++ u32 *dest_cpy = (u32 *)buf;
889++ u32 size_dw = len;
890++ u32 src = 0;
891++
892++ if (!buf)
893++ return 0xFF;
894++
895++ if (type == WTBL_TYPE_LMAC) {
896++ mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
897++ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
898++ src = LWTBL_IDX2BASE(idx, start_dw);
899++ } else if (type == WTBL_TYPE_UMAC) {
900++ mt76_wr(dev, MT_UWTBL_TOP_WDUCR,
901++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
902++ src = UWTBL_IDX2BASE(idx, start_dw);
903++ } else if (type == WTBL_TYPE_KEY) {
904++ mt76_wr(dev, MT_UWTBL_TOP_WDUCR,
905++ MT_UWTBL_TOP_WDUCR_TARGET |
906++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
907++ src = KEYTBL_IDX2BASE(idx, start_dw);
908++ }
909++
910++ while (size_dw--) {
911++ *dest_cpy++ = mt76_rr(dev, src);
912++ src += 4;
913++ };
914++
915++ return 0;
916++}
917++
918++#if 0
919++static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
920++ enum mt7915_wtbl_type type, u16 start_dw,
921++ u32 val)
922++{
923++ u32 addr = 0;
924++
925++ if (type == WTBL_TYPE_LMAC) {
926++ mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
927++ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
928++ addr = LWTBL_IDX2BASE(idx, start_dw);
929++ } else if (type == WTBL_TYPE_UMAC) {
930++ mt76_wr(dev, MT_UWTBL_TOP_WDUCR,
931++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
932++ addr = UWTBL_IDX2BASE(idx, start_dw);
933++ } else if (type == WTBL_TYPE_KEY) {
934++ mt76_wr(dev, MT_UWTBL_TOP_WDUCR,
935++ MT_UWTBL_TOP_WDUCR_TARGET |
936++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
937++ addr = KEYTBL_IDX2BASE(idx, start_dw);
938++ }
939++
940++ mt76_wr(dev, addr, val);
941++
942++ return 0;
943++}
944++#endif
945++
946++static int
947++mt7915_fw_debug_set(void *data, u64 val)
948++{
949++ struct mt7915_phy *phy = data;
950++ struct mt7915_dev *dev = phy->dev;
951++ u8 band_idx = phy != &dev->phy;
952++
953++ dev->dbg.fw_debug = val;
954++
955++ /* 88 is magic num enable ICS */
956++ if (val == 88)
957++ dev->dbg.fw_debug = 16;
958++
959++ /* 87 is magic num enable ICS for older FW */
960++ if (val == 87)
961++ dev->dbg.fw_debug = 15;
962++
963++ if (dev->dbg.fw_debug == 15)
964++ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 16);
965++ else
966++ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, dev->dbg.fw_debug);
967++
968++ if (val == 8 || val == 88 || val == 16 || val == 87 || val == 15) {
969++ mt7915_mcu_fw_dbg_ctrl(dev, 62, 1);
970++ mt7915_mcu_fw_dbg_ctrl(dev, 63, 1);
971++ mt7915_mcu_fw_dbg_ctrl(dev, 64, 1);
972++ mt7915_mcu_fw_dbg_ctrl(dev, 65, 1);
973++ mt7915_mcu_fw_dbg_ctrl(dev, 66, 1);
974++ mt7915_mcu_fw_dbg_ctrl(dev, 68, 1);
975++ }
976++
977++ if (val == 88 || val == 87) {
978++ switch (band_idx) {
979++ case 0:
980++ /* ICS report engine enable, use RXVEC page count,
981++ * ICS AGG timeout to maximum.
982++ */
983++ mt76_wr(dev, 0x21ef0, 0x1FF0000);
984++
985++ // ICS AGG size --> 1400b
986++ mt76_wr(dev, 0x21ef4, 0x5780070);
987++
988++ // ICS TX enable
989++ mt76_wr(dev, 0x21200, 1);
990++
991++ // ICS RX enable
992++ mt76_wr(dev, 0x21a18, 1);
993++ break;
994++ case 1:
995++ /* ICS report engine enable, use RXVEC page count,
996++ * ICS AGG timeout to maximum.
997++ */
998++ mt76_wr(dev, 0xa1ef0, 0x1FF0000);
999++
1000++ // ICS AGG size --> 1400b
1001++ mt76_wr(dev, 0xa1ef4, 0x5780070);
1002++
1003++ // ICS TX enable
1004++ mt76_wr(dev, 0xa1200, 1);
1005++
1006++ // ICS RX enable
1007++ mt76_wr(dev, 0xa1a18, 1);
1008++ break;
1009++ }
1010++ }
1011++
1012++ if (!val) {
1013++ // Stop ICS
1014++ switch (band_idx) {
1015++ case 0:
1016++ mt76_wr(dev, 0x21ef0, 0x0FF0000);
1017++ break;
1018++ case 1:
1019++ mt76_wr(dev, 0xa1ef0, 0x0FF0000);
1020++ break;
1021++ }
1022++ }
1023++
1024++ return 0;
1025++}
1026++
1027++static int
1028++mt7915_fw_debug_get(void *data, u64 *val)
1029++{
1030++ struct mt7915_dev *dev = data;
1031++
1032++ *val = dev->dbg.fw_debug;
1033++
1034++ return 0;
1035++}
1036++
1037++DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug, mt7915_fw_debug_get,
1038++ mt7915_fw_debug_set, "%lld\n");
1039++
1040++static int
1041++mt7915_fw_debug_module_set(void *data, u64 module)
1042++{
1043++ struct mt7915_dev *dev = data;
1044++
1045++ dev->dbg.fw_dbg_module = module;
1046++ return 0;
1047++}
1048++
1049++static int
1050++mt7915_fw_debug_module_get(void *data, u64 *module)
1051++{
1052++ struct mt7915_dev *dev = data;
1053++
1054++ *module = dev->dbg.fw_dbg_module;
1055++ return 0;
1056++}
1057++
1058++DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
1059++ mt7915_fw_debug_module_set, "%lld\n");
1060++
1061++static int
1062++mt7915_fw_debug_level_set(void *data, u64 level)
1063++{
1064++ struct mt7915_dev *dev = data;
1065++
1066++ dev->dbg.fw_dbg_lv = level;
1067++ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
1068++ return 0;
1069++}
1070++
1071++static int
1072++mt7915_fw_debug_level_get(void *data, u64 *level)
1073++{
1074++ struct mt7915_dev *dev = data;
1075++
1076++ *level = dev->dbg.fw_dbg_lv;
1077++ return 0;
1078++}
1079++
1080++DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
1081++ mt7915_fw_debug_level_set, "%lld\n");
1082++
1083++#define MAX_TX_MODE 12
1084++static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
1085++ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
1086++ "HE_TRIG", "HE_MU", "N/A"};
1087++static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
1088++ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
1089++ "N/A"};
1090++static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
1091++ "48M", "54M", "N/A"};
1092++static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
1093++ "20/40/80/160/80+80MHz"};
1094++
1095++static char *hw_rate_ofdm_str(u16 ofdm_idx)
1096++{
1097++ switch (ofdm_idx) {
1098++ case 11: /* 6M */
1099++ return HW_TX_RATE_OFDM_STR[0];
1100++
1101++ case 15: /* 9M */
1102++ return HW_TX_RATE_OFDM_STR[1];
1103++
1104++ case 10: /* 12M */
1105++ return HW_TX_RATE_OFDM_STR[2];
1106++
1107++ case 14: /* 18M */
1108++ return HW_TX_RATE_OFDM_STR[3];
1109++
1110++ case 9: /* 24M */
1111++ return HW_TX_RATE_OFDM_STR[4];
1112++
1113++ case 13: /* 36M */
1114++ return HW_TX_RATE_OFDM_STR[5];
1115++
1116++ case 8: /* 48M */
1117++ return HW_TX_RATE_OFDM_STR[6];
1118++
1119++ case 12: /* 54M */
1120++ return HW_TX_RATE_OFDM_STR[7];
1121++
1122++ default:
1123++ return HW_TX_RATE_OFDM_STR[8];
1124++ }
1125++}
1126++
1127++static char *hw_rate_str(u8 mode, u16 rate_idx)
1128++{
1129++ if (mode == 0)
1130++ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
1131++ else if (mode == 1)
1132++ return hw_rate_ofdm_str(rate_idx);
1133++ else
1134++ return "MCS";
1135++}
1136++
1137++static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
1138++{
1139++ u16 txmode, mcs, nss, stbc;
1140++
1141++ txmode = FIELD_GET(GENMASK(9, 6), txrate);
1142++ mcs = FIELD_GET(GENMASK(5, 0), txrate);
1143++ nss = FIELD_GET(GENMASK(12, 10), txrate);
1144++ stbc = FIELD_GET(BIT(13), txrate);
1145++
1146++ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
1147++ rate_idx + 1, txrate,
1148++ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
1149++ mcs, hw_rate_str(txmode, mcs), nss, stbc);
1150++}
1151++
1152++#define LWTBL_LEN_IN_DW 32
1153++#define UWTBL_LEN_IN_DW 8
1154++#define ONE_KEY_ENTRY_LEN_IN_DW 8
1155++static int mt7915_wtbl_read(struct seq_file *s, void *data)
1156++{
1157++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
1158++ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
1159++ int x;
1160++ u32 *addr = 0;
1161++ u32 dw_value = 0;
1162++
1163++ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
1164++ LWTBL_LEN_IN_DW, lwtbl);
1165++ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
1166++ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
1167++ MT_WTBLON_TOP_WDUCR,
1168++ mt76_rr(dev, MT_WTBLON_TOP_WDUCR),
1169++ LWTBL_IDX2BASE(dev->wlan_idx, 0));
1170++ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
1171++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
1172++ x,
1173++ lwtbl[x * 4 + 3],
1174++ lwtbl[x * 4 + 2],
1175++ lwtbl[x * 4 + 1],
1176++ lwtbl[x * 4]);
1177++ }
1178++
1179++
1180++ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
1181++ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
1182++
1183++ // DW0, DW1
1184++ seq_printf(s, "LWTBL DW 0/1\n\t");
1185++ addr = (u32 *)&(lwtbl[0]);
1186++ dw_value = *addr;
1187++ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
1188++ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
1189++ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
1190++ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
1191++ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
1192++ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
1193++ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
1194++ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
1195++ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
1196++
1197++ // DW2
1198++ seq_printf(s, "LWTBL DW 2\n\t");
1199++ addr = (u32 *)&(lwtbl[2*4]);
1200++ dw_value = *addr;
1201++ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
1202++ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
1203++ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
1204++ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
1205++ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
1206++ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
1207++ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
1208++ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
1209++ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
1210++ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
1211++ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
1212++ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
1213++ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
1214++ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
1215++ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
1216++
1217++ // DW3
1218++ seq_printf(s, "LWTBL DW 3\n\t");
1219++ addr = (u32 *)&(lwtbl[3*4]);
1220++ dw_value = *addr;
1221++ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
1222++ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
1223++ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
1224++ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
1225++ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
1226++ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
1227++ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
1228++ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
1229++ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
1230++ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
1231++ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
1232++ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
1233++ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
1234++
1235++ // DW4
1236++ seq_printf(s, "LWTBL DW 4\n\t");
1237++ addr = (u32 *)&(lwtbl[4*4]);
1238++ dw_value = *addr;
1239++ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
1240++ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
1241++ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
1242++ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
1243++ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
1244++ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
1245++ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
1246++ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
1247++ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
1248++ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
1249++ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
1250++ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
1251++ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
1252++ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
1253++ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
1254++ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
1255++
1256++ // DW5
1257++ seq_printf(s, "LWTBL DW 5\n\t");
1258++ addr = (u32 *)&(lwtbl[5*4]);
1259++ dw_value = *addr;
1260++ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
1261++ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
1262++ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
1263++ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
1264++ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
1265++ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
1266++ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
1267++ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
1268++ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
1269++ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
1270++ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
1271++ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
1272++ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
1273++ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
1274++ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
1275++ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
1276++ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
1277++ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
1278++
1279++ // DW6
1280++ seq_printf(s, "LWTBL DW 6\n\t");
1281++ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
1282++ addr = (u32 *)&(lwtbl[6*4]);
1283++ dw_value = *addr;
1284++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
1285++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
1286++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
1287++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
1288++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
1289++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
1290++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
1291++ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
1292++
1293++ // DW7
1294++ seq_printf(s, "LWTBL DW 7\n\t");
1295++ addr = (u32 *)&(lwtbl[7*4]);
1296++ dw_value = *addr;
1297++ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
1298++ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
1299++ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
1300++ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
1301++ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
1302++ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
1303++ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
1304++ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
1305++ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
1306++ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
1307++ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
1308++ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
1309++ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
1310++ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
1311++ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
1312++ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 26), dw_value));
1313++ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
1314++ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
1315++
1316++ // DW8
1317++ seq_printf(s, "LWTBL DW 8\n\t");
1318++ addr = (u32 *)&(lwtbl[8*4]);
1319++ dw_value = *addr;
1320++ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
1321++ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
1322++ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
1323++ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
1324++ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
1325++ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
1326++
1327++ // DW9
1328++ seq_printf(s, "LWTBL DW 9\n\t");
1329++ addr = (u32 *)&(lwtbl[9*4]);
1330++ dw_value = *addr;
1331++ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
1332++ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
1333++ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
1334++ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
1335++ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
1336++ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
1337++ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
1338++ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
1339++ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
1340++ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
1341++
1342++ // DW10
1343++ seq_printf(s, "LWTBL DW 10\n");
1344++ addr = (u32 *)&(lwtbl[10*4]);
1345++ dw_value = *addr;
1346++ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
1347++ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
1348++ // DW11
1349++ seq_printf(s, "LWTBL DW 11\n");
1350++ addr = (u32 *)&(lwtbl[11*4]);
1351++ dw_value = *addr;
1352++ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
1353++ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
1354++ // DW12
1355++ seq_printf(s, "LWTBL DW 12\n");
1356++ addr = (u32 *)&(lwtbl[12*4]);
1357++ dw_value = *addr;
1358++ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
1359++ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
1360++ // DW13
1361++ seq_printf(s, "LWTBL DW 13\n");
1362++ addr = (u32 *)&(lwtbl[13*4]);
1363++ dw_value = *addr;
1364++ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
1365++ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
1366++ return 0;
1367++}
1368++
1369++static int mt7915_uwtbl_read(struct seq_file *s, void *data)
1370++{
1371++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
1372++ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
1373++ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
1374++ int x;
1375++ u32 *addr = 0;
1376++ u32 dw_value = 0;
1377++ u32 amsdu_len = 0;
1378++ u32 u2SN = 0;
1379++ u16 keyloc0, keyloc1;
1380++
1381++ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
1382++ UWTBL_LEN_IN_DW, uwtbl);
1383++ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
1384++ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
1385++ MT_WTBLON_TOP_WDUCR,
1386++ mt76_rr(dev, MT_WTBLON_TOP_WDUCR),
1387++ UWTBL_IDX2BASE(dev->wlan_idx, 0));
1388++ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
1389++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
1390++ x,
1391++ uwtbl[x * 4 + 3],
1392++ uwtbl[x * 4 + 2],
1393++ uwtbl[x * 4 + 1],
1394++ uwtbl[x * 4]);
1395++ }
1396++
1397++ /* UMAC WTBL DW 0 */
1398++ seq_printf(s, "\nUWTBL PN\n\t");
1399++ addr = (u32 *)&(uwtbl[0]);
1400++ dw_value = *addr;
1401++ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
1402++ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
1403++ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
1404++ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
1405++
1406++ addr = (u32 *)&(uwtbl[1 * 4]);
1407++ dw_value = *addr;
1408++ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
1409++ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
1410++
1411++ /* UMAC WTBL DW SN part */
1412++ seq_printf(s, "\nUWTBL SN\n");
1413++ addr = (u32 *)&(uwtbl[2 * 4]);
1414++ dw_value = *addr;
1415++ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
1416++ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
1417++
1418++ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
1419++ addr = (u32 *)&(uwtbl[3 * 4]);
1420++ dw_value = *addr;
1421++ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
1422++ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
1423++ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
1424++ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
1425++
1426++ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
1427++ addr = (u32 *)&(uwtbl[4 * 4]);
1428++ dw_value = *addr;
1429++ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
1430++ seq_printf(s, "TID5_SN:%u\n", u2SN);
1431++ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
1432++ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
1433++
1434++ addr = (u32 *)&(uwtbl[1 * 4]);
1435++ dw_value = *addr;
1436++ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
1437++
1438++ /* UMAC WTBL DW 0 */
1439++ seq_printf(s, "\nUWTBL others\n");
1440++
1441++ addr = (u32 *)&(uwtbl[5 * 4]);
1442++ dw_value = *addr;
1443++ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
1444++ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
1445++ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
1446++ FIELD_GET(GENMASK(10, 0), dw_value),
1447++ FIELD_GET(GENMASK(26, 16), dw_value));
1448++ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
1449++ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
1450++
1451++ addr = (u32 *)&(uwtbl[6*4]);
1452++ dw_value = *addr;
1453++ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
1454++
1455++ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
1456++ if (amsdu_len == 0)
1457++ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
1458++ else if (amsdu_len == 1)
1459++ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
1460++ 1,
1461++ 255,
1462++ amsdu_len);
1463++ else
1464++ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
1465++ 256 * (amsdu_len - 1),
1466++ 256 * (amsdu_len - 1) + 255,
1467++ amsdu_len
1468++ );
1469++ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
1470++ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
1471++ FIELD_GET(GENMASK(8, 6), dw_value));
1472++
1473++ /* Parse KEY link */
1474++ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
1475++ if(keyloc0 != GENMASK(10, 0)) {
1476++ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
1477++ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
1478++ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
1479++ MT_WTBLON_TOP_WDUCR,
1480++ mt76_rr(dev, MT_WTBLON_TOP_WDUCR),
1481++ KEYTBL_IDX2BASE(keyloc0, 0));
1482++
1483++ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
1484++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
1485++ x,
1486++ keytbl[x * 4 + 3],
1487++ keytbl[x * 4 + 2],
1488++ keytbl[x * 4 + 1],
1489++ keytbl[x * 4]);
1490++ }
1491++ }
1492++
1493++ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
1494++ if(keyloc1 != GENMASK(10, 0)) {
1495++ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
1496++ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
1497++ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
1498++ MT_WTBLON_TOP_WDUCR,
1499++ mt76_rr(dev, MT_WTBLON_TOP_WDUCR),
1500++ KEYTBL_IDX2BASE(keyloc1, 0));
1501++
1502++ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
1503++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
1504++ x,
1505++ keytbl[x * 4 + 3],
1506++ keytbl[x * 4 + 2],
1507++ keytbl[x * 4 + 1],
1508++ keytbl[x * 4]);
1509++ }
1510++ }
1511++ return 0;
1512++}
1513++
1514++static int
1515++mt7915_l1reg_set(void *data, u64 val)
1516++{
1517++ struct mt7915_dev *dev = data;
1518++
1519++ mt76_wr(dev, dev->dbg.l1debugfs_reg, val);
1520++ return 0;
1521++}
1522++
1523++static int
1524++mt7915_l1reg_get(void *data, u64 *val)
1525++{
1526++ struct mt7915_dev *dev = data;
1527++
1528++ *val = mt76_rr(dev, dev->dbg.l1debugfs_reg);
1529++ return 0;
1530++}
1531++
1532++DEFINE_DEBUGFS_ATTRIBUTE(fops_l1regval, mt7915_l1reg_get, mt7915_l1reg_set,
1533++ "0x%08llx\n");
1534++
1535++static int
1536++mt7915_l2reg_set(void *data, u64 val)
1537++{
1538++ struct mt7915_dev *dev = data;
1539++
1540++ mt76_wr(dev, dev->dbg.l2debugfs_reg, val);
1541++ return 0;
1542++}
1543++
1544++static int
1545++mt7915_l2reg_get(void *data, u64 *val)
1546++{
1547++ struct mt7915_dev *dev = data;
1548++
1549++ *val = mt76_rr(dev, dev->dbg.l2debugfs_reg);
1550++ return 0;
1551++}
1552++
1553++DEFINE_DEBUGFS_ATTRIBUTE(fops_l2regval, mt7915_l2reg_get, mt7915_l2reg_set,
1554++ "0x%08llx\n");
1555++
1556++static int
1557++mt7915_mac_reg_set(void *data, u64 val)
1558++{
1559++ struct mt7915_dev *dev = data;
1560++ u8 remap = 0;
1561++
1562++ if (mt_mac_cr_range_mapping(dev, &dev->dbg.mac_reg) == true) {
1563++ mt76_wr(dev, dev->dbg.mac_reg, val);
1564++ } else {
1565++ if (pci_io_remap_is_l1_remap(&dev->dbg.mac_reg)) {
1566++ remap = 1;
1567++ mt76_wr(dev, dev->dbg.mac_reg, val);
1568++ } else {
1569++ remap = 2;
1570++ mt76_wr(dev, dev->dbg.mac_reg, val);
1571++ }
1572++ }
1573++
1574++ printk("MacAddr=0x%x, MacValue=0x%llx, IsRemap=%d\n",
1575++ dev->dbg.mac_reg, val, remap);
1576++ return 0;
1577++}
1578++
1579++static int
1580++mt7915_mac_reg_get(void *data, u64 *val)
1581++{
1582++ struct mt7915_dev *dev = data;
1583++ u8 remap = 0;
1584++
1585++ if (mt_mac_cr_range_mapping(dev, &dev->dbg.mac_reg) == true) {
1586++ *val = mt76_rr(dev, dev->dbg.mac_reg);
1587++ } else {
1588++ if (pci_io_remap_is_l1_remap(&dev->dbg.mac_reg)) {
1589++ remap = 1;
1590++ *val = mt76_rr(dev, dev->dbg.mac_reg);
1591++ } else {
1592++ remap = 2;
1593++ *val = mt76_rr(dev, dev->dbg.mac_reg);
1594++ }
1595++ }
1596++
1597++ printk("MacAddr=0x%x, MacValue=0x%llx, IsRemap=%d\n",
1598++ dev->dbg.mac_reg, *val, remap);
1599++ return 0;
1600++}
1601++
1602++DEFINE_DEBUGFS_ATTRIBUTE(fops_mac_regval, mt7915_mac_reg_get, mt7915_mac_reg_set,
1603++ "0x%08llx\n");
1604++
1605++/* copy again */
1606++static u32 mt7915_eeprom_read(struct mt7915_dev *dev, u32 offset)
1607++{
1608++ u8 *data = dev->mt76.eeprom.data;
1609++
1610++ if (data[offset] == 0xff)
1611++ mt7915_mcu_get_eeprom(dev, offset);
1612++
1613++ return data[offset];
1614++}
1615++
1616++static int mt7915_read_efuse(struct seq_file *s, void *data)
1617++{
1618++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
1619++ u8 *buf = dev->mt76.eeprom.data;
1620++ u16 idx_round = round_down(dev->dbg.eep_idx, 16);
1621++ u32 val = mt7915_eeprom_read(dev, dev->dbg.eep_idx);
1622++ int i;
1623++
1624++ seq_printf(s, "%08x ", idx_round);
1625++ for (i = 0; i < 16; i++) {
1626++ if (i < 15)
1627++ seq_printf(s, "%02x ", buf[idx_round + i]);
1628++ else
1629++ seq_printf(s, "%02x\n", buf[idx_round + i]);
1630++ }
1631++ seq_printf(s, "Value at 0x%x = 0x%x\n", dev->dbg.eep_idx, val);
1632++
1633++ return 0;
1634++}
1635++
1636++static ssize_t mt7915_fwlog_server_read(struct file *file,
1637++ char __user *user_buf,
1638++ size_t count,
1639++ loff_t *ppos)
1640++{
1641++ struct mt7915_dev *dev = dev_get_drvdata(file->private_data);
1642++
1643++ char buf[200]={};
1644++ int len = 0;
1645++
1646++ len = scnprintf(buf, sizeof(buf), "ip=%pI4\nmac=%pM\nif=%s\n",
1647++ &dev->dbg.fwlog_server_ip,
1648++ &dev->dbg.fwlog_server_mac,
1649++ dev->dbg.fwlog_ifname);
1650++
1651++ return simple_read_from_buffer(user_buf, count, ppos,
1652++ buf, len);
1653++}
1654++
1655++static int mac_aton(char *addr, u8 *n) {
1656++ int matches = sscanf(addr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
1657++ n, n+1, n+2, n+3, n+4, n+5);
1658++
1659++ return (ETH_ALEN == matches ? 0 : -EINVAL);
1660++}
1661++
1662++static ssize_t
1663++mt7915_fwlog_server_write(struct file *file,
1664++ const char __user *user_buf,
1665++ size_t count,
1666++ loff_t *ppos)
1667++{
1668++ struct mt7915_dev *dev = dev_get_drvdata(file->private_data);
1669++ char buf[100];
1670++ char ip[16] = {};
1671++ char mac[20] = {};
1672++ size_t len;
1673++
1674++ if (count > sizeof(buf))
1675++ return -EINVAL;
1676++
1677++ if (copy_from_user(buf, user_buf, count))
1678++ return -EFAULT;
1679++
1680++ buf[sizeof(buf) - 1] = '\0';
1681++ len = strlen(buf);
1682++ if (len > 0 && buf[len - 1] == '\n')
1683++ buf[len - 1] = 0;
1684++
1685++ if (sscanf(buf, "ip=%s", ip) == 1) {
1686++ dev->dbg.fwlog_server_ip = in_aton(ip);
1687++ return count;
1688++ } else if (sscanf(buf, "mac=%s", mac) == 1) {
1689++ if (mac_aton(mac, dev->dbg.fwlog_server_mac))
1690++ return -EFAULT;
1691++ return count;
1692++ } else if (sscanf(buf, "if=%s", dev->dbg.fwlog_ifname) == 1) {
1693++ return count;
1694++ }
1695++
1696++ printk("usage:\n");
1697++ printk("\techo ip=192.168.1.100 > fwlog_setting\n");
1698++ printk("\techo mac=aa:bb:cc:11:22:33 > fwlog_setting\n");
1699++ printk("\techo if=wlan0 > fwlog_setting\n");
1700++ printk("\techo 16 or 88 > fw_debug_internal (1953 FW after 20210330)\n");
1701++ printk("\techo 15 or 87 > fw_debug_internal (older or 2045 FW)\n");
1702++
1703++ return -EINVAL;
1704++}
1705++
1706++static const struct file_operations fops_fwlog_server = {
1707++ .read = mt7915_fwlog_server_read,
1708++ .write = mt7915_fwlog_server_write,
1709++ .open = simple_open,
1710++};
1711++
1712++static inline u32
1713++mt7915_mac_rr(struct mt7915_dev *dev, u32 addr)
1714++{
1715++ u32 val;
1716++ if (mt_mac_cr_range_mapping(dev, &addr) == true) {
1717++ val = mt76_rr(dev, addr);
1718++ } else {
1719++ if (pci_io_remap_is_l1_remap(&addr))
1720++ val = mt76_rr(dev, addr);
1721++ else
1722++ val = mt76_rr(dev, addr);
1723++ }
1724++ return val;
1725++}
1726++
1727++static inline void
1728++mt7915_mac_wr(struct mt7915_dev *dev, u32 addr, u32 val)
1729++{
1730++ if (mt_mac_cr_range_mapping(dev, &addr) == true) {
1731++ mt76_wr(dev, addr, val);
1732++ } else {
1733++ if (pci_io_remap_is_l1_remap(&addr))
1734++ mt76_wr(dev, addr, val);
1735++ else
1736++ mt76_wr(dev, addr, val);
1737++ }
1738++}
1739++
1740++static void
1741++dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
1742++{
1743++ u32 base, cnt, cidx, didx, queue_cnt;
1744++
1745++ base= mt7915_mac_rr(dev, ring_base);
1746++ cnt = mt7915_mac_rr(dev, ring_base + 4);
1747++ cidx = mt7915_mac_rr(dev, ring_base + 8);
1748++ didx = mt7915_mac_rr(dev, ring_base + 12);
1749++ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
1750++
1751++ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
1752++}
1753++
1754++static void
1755++dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
1756++{
1757++ u32 base, cnt, cidx, didx, queue_cnt;
1758++
1759++ base= mt7915_mac_rr(dev, ring_base);
1760++ cnt = mt7915_mac_rr(dev, ring_base + 4);
1761++ cidx = mt7915_mac_rr(dev, ring_base + 8);
1762++ didx = mt7915_mac_rr(dev, ring_base + 12);
1763++ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
1764++
1765++ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
1766++}
1767++
1768++static void
1769++mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
1770++{
1771++ u32 sys_ctrl[10] = {};
1772++
1773++ /* HOST DMA */
1774++ sys_ctrl[0] = mt76_rr(dev, MT_INT_SOURCE_CSR);
1775++ sys_ctrl[1] = mt76_rr(dev, MT_INT_MASK_CSR);
1776++ sys_ctrl[2] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR);
1777++ sys_ctrl[3] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR);
1778++ sys_ctrl[4] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA1_HOST_INT_STA_ADDR);
1779++ sys_ctrl[5] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA1_HOST_INT_ENA_ADDR);
1780++ sys_ctrl[6] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR);
1781++ sys_ctrl[7] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_ADDR);
1782++ seq_printf(s, "HOST_DMA Configuration\n");
1783++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
1784++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
1785++ seq_printf(s, "%10s %10x %10x\n",
1786++ "Merge", sys_ctrl[0], sys_ctrl[1]);
1787++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1788++ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
1789++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1790++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1791++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1792++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1793++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1794++ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
1795++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1796++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1797++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1798++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1799++
1800++ sys_ctrl[0] = mt76_rr(dev, MT_INT1_SOURCE_CSR);
1801++ sys_ctrl[1] = mt76_rr(dev, MT_INT1_MASK_CSR);
1802++ sys_ctrl[2] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR);
1803++ sys_ctrl[3] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR);
1804++ sys_ctrl[4] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA1_PCIE1_HOST_INT_STA_ADDR);
1805++ sys_ctrl[5] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA1_PCIE1_HOST_INT_ENA_ADDR);
1806++ sys_ctrl[6] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR);
1807++ sys_ctrl[7] = mt7915_mac_rr(dev, WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
1808++ seq_printf(s, "%10s %10x %10x\n",
1809++ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
1810++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1811++ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
1812++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1813++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1814++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1815++ (sys_ctrl[6] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1816++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1817++ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
1818++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1819++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1820++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1821++ (sys_ctrl[7] & WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1822++
1823++ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
1824++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1825++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1826++ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
1827++ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
1828++
1829++ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
1830++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1831++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1832++ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING1_CTRL0_ADDR);
1833++
1834++ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
1835++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1836++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1837++ dump_dma_tx_ring_info(s, dev, "T16:FWDL", WF_WFDMA_HOST_DMA1_WPDMA_TX_RING16_CTRL0_ADDR);
1838++ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", WF_WFDMA_HOST_DMA1_WPDMA_TX_RING17_CTRL0_ADDR);
1839++ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", WF_WFDMA_HOST_DMA1_WPDMA_TX_RING18_CTRL0_ADDR);
1840++ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", WF_WFDMA_HOST_DMA1_WPDMA_TX_RING19_CTRL0_ADDR);
1841++ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", WF_WFDMA_HOST_DMA1_WPDMA_TX_RING20_CTRL0_ADDR);
1842++ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", WF_WFDMA_HOST_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
1843++ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", WF_WFDMA_HOST_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
1844++ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", WF_WFDMA_HOST_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
1845++
1846++ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
1847++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1848++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1849++ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_TX_RING19_CTRL0_ADDR);
1850++ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", WF_WFDMA_HOST_DMA1_PCIE1_WPDMA_RX_RING2_CTRL0_ADDR);
1851++
1852++ /* MCU DMA information */
1853++ sys_ctrl[0] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
1854++ sys_ctrl[1] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
1855++ sys_ctrl[2] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
1856++ sys_ctrl[3] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
1857++ sys_ctrl[4] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
1858++ sys_ctrl[5] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
1859++ sys_ctrl[6] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
1860++ sys_ctrl[7] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
1861++ sys_ctrl[8] = mt7915_mac_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
1862++
1863++ seq_printf(s, "MCU_DMA Configuration\n");
1864++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
1865++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
1866++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1867++ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
1868++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1869++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1870++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1871++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1872++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1873++ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
1874++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1875++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1876++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1877++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1878++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1879++ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
1880++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1881++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1882++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1883++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1884++
1885++ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
1886++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1887++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1888++ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
1889++ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
1890++ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
1891++ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
1892++ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
1893++ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
1894++ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
1895++ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
1896++
1897++ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
1898++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1899++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1900++ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
1901++ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
1902++ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
1903++ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
1904++ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
1905++ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
1906++ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
1907++ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
1908++
1909++ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
1910++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1911++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1912++ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
1913++ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
1914++
1915++ /* MEM DMA information */
1916++ sys_ctrl[0] = mt7915_mac_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
1917++ sys_ctrl[1] = mt7915_mac_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
1918++ sys_ctrl[2] = mt7915_mac_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
1919++
1920++ seq_printf(s, "MEM_DMA Configuration\n");
1921++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
1922++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
1923++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
1924++ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
1925++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
1926++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
1927++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
1928++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
1929++
1930++ seq_printf(s, "MEM_DMA Ring Configuration\n");
1931++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
1932++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
1933++ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
1934++ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
1935++ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
1936++ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
1937++}
1938++
1939++static int mt7915_trinfo_read(struct seq_file *s, void *data)
1940++{
1941++#define TX_RING_NUM ARRAY_SIZE(tx_ring_layout)
1942++#define RX_RING_NUM ARRAY_SIZE(rx_ring_layout)
1943++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
1944++ u32 tbase[TX_RING_NUM], tcnt[TX_RING_NUM];
1945++ u32 tcidx[TX_RING_NUM], tdidx[TX_RING_NUM];
1946++ u32 rbase[RX_RING_NUM], rcnt[RX_RING_NUM];
1947++ u32 rcidx[RX_RING_NUM], rdidx[RX_RING_NUM];
1948++ int idx;
1949++
1950++ for (idx = 0; idx < TX_RING_NUM; idx++) {
1951++ tbase[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base);
1952++ tcnt[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x04);
1953++ tcidx[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x08);
1954++ tdidx[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x0c);
1955++ }
1956++
1957++ for (idx = 0; idx < RX_RING_NUM; idx++) {
1958++ rbase[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base);
1959++ rcnt[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x04);
1960++ rcidx[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x08);
1961++ rdidx[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x0c);
1962++ }
1963++
1964++ seq_printf(s, "=================================================\n");
1965++ seq_printf(s, "TxRing Configuration\n");
1966++ seq_printf(s, "%4s %8s %8s %10s %6s %6s %6s %6s\n",
1967++ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
1968++ "QCnt");
1969++ for (idx = 0; idx < RX_RING_NUM; idx++) {
1970++ u32 queue_cnt;
1971++
1972++ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
1973++ (tcidx[idx] - tdidx[idx]) :
1974++ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
1975++ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
1976++ idx,
1977++ (tx_ring_layout[idx].ring_attr == HIF_TX_DATA) ? "DATA" :
1978++ (tx_ring_layout[idx].ring_attr == HIF_TX_CMD) ? "CMD" :
1979++ (tx_ring_layout[idx].ring_attr == HIF_TX_CMD_WM) ? "CMD_WM" :
1980++ (tx_ring_layout[idx].ring_attr == HIF_TX_FWDL) ? "FWDL" : "UN",
1981++ tx_ring_layout[idx].hw_desc_base, tbase[idx],
1982++ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
1983++ }
1984++
1985++ seq_printf(s, "RxRing Configuration\n");
1986++ seq_printf(s, "%4s %8s %8s %10s %6s %6s %6s %6s\n",
1987++ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
1988++ "QCnt");
1989++
1990++ for (idx = 0; idx < RX_RING_NUM; idx++) {
1991++ u32 queue_cnt;
1992++
1993++ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
1994++ (rdidx[idx] - rcidx[idx] - 1) :
1995++ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
1996++ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
1997++ idx,
1998++ (rx_ring_layout[idx].ring_attr == HIF_RX_DATA) ? "DATA" :
1999++ (rx_ring_layout[idx].ring_attr == HIF_RX_EVENT) ? "EVENT" : "UN",
2000++ rx_ring_layout[idx].hw_desc_base, rbase[idx],
2001++ rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2002++ }
2003++
2004++ mt7915_show_dma_info(s, dev);
2005++ return 0;
2006++}
2007++
2008++static int mt7915_drr_info(struct seq_file *s, void *data)
2009++{
2010++#define DL_AC_START 0x00
2011++#define DL_AC_END 0x0F
2012++#define UL_AC_START 0x10
2013++#define UL_AC_END 0x1F
2014++
2015++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2016++ u32 drr_sta_status[16];
2017++ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
2018++ bool is_show = false;
2019++ int idx, sta_line = 0, sta_no = 0, max_sta_line = (MT7915_WTBL_SIZE+31)/32;
2020++ seq_printf(s, "DRR Table STA Info:\n");
2021++
2022++ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2023++ is_show = true;
2024++ drr_ctrl_val = (drr_ctrl_def_val | idx);
2025++ mt76_wr(dev, MT_PLE_DRR_TABLE_CTRL, drr_ctrl_val);
2026++ drr_sta_status[0] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA0);
2027++ drr_sta_status[1] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA1);
2028++ drr_sta_status[2] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA2);
2029++ drr_sta_status[3] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA3);
2030++ drr_sta_status[4] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA4);
2031++ drr_sta_status[5] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA5);
2032++ drr_sta_status[6] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA6);
2033++ drr_sta_status[7] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA7);
2034++
2035++ if (max_sta_line > 8) {
2036++ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
2037++ mt76_wr(dev, MT_PLE_DRR_TABLE_CTRL, drr_ctrl_val);
2038++ drr_sta_status[8] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA0);
2039++ drr_sta_status[9] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA1);
2040++ drr_sta_status[10] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA2);
2041++ drr_sta_status[11] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA3);
2042++ drr_sta_status[12] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA4);
2043++ drr_sta_status[13] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA5);
2044++ drr_sta_status[14] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA6);
2045++ drr_sta_status[15] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA7);
2046++ }
2047++
2048++ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2049++ if (drr_sta_status[sta_line] > 0) {
2050++ for (sta_no = 0; sta_no < 32; sta_no++) {
2051++ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2052++ if (is_show) {
2053++ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
2054++ is_show = false;
2055++ }
2056++ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2057++ }
2058++ }
2059++ }
2060++ }
2061++ }
2062++
2063++ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
2064++ is_show = true;
2065++ drr_ctrl_val = (drr_ctrl_def_val | idx);
2066++ mt76_wr(dev, MT_PLE_DRR_TABLE_CTRL, drr_ctrl_val);
2067++ drr_sta_status[0] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA0);
2068++ drr_sta_status[1] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA1);
2069++ drr_sta_status[2] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA2);
2070++ drr_sta_status[3] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA3);
2071++ drr_sta_status[4] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA4);
2072++ drr_sta_status[5] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA5);
2073++ drr_sta_status[6] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA6);
2074++ drr_sta_status[7] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA7);
2075++
2076++ if (max_sta_line > 8) {
2077++ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
2078++ mt76_wr(dev, MT_PLE_DRR_TABLE_CTRL, drr_ctrl_val);
2079++ drr_sta_status[8] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA0);
2080++ drr_sta_status[9] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA1);
2081++ drr_sta_status[10] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA2);
2082++ drr_sta_status[11] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA3);
2083++ drr_sta_status[12] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA4);
2084++ drr_sta_status[13] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA5);
2085++ drr_sta_status[14] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA6);
2086++ drr_sta_status[15] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA7);
2087++ }
2088++
2089++ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2090++ if (drr_sta_status[sta_line] > 0) {
2091++ for (sta_no = 0; sta_no < 32; sta_no++) {
2092++ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2093++ if (is_show) {
2094++ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
2095++ is_show = false;
2096++ }
2097++ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2098++ }
2099++ }
2100++ }
2101++ }
2102++ }
2103++
2104++ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2105++ drr_ctrl_def_val = 0x80420000;
2106++ drr_ctrl_val = (drr_ctrl_def_val | idx);
2107++ mt76_wr(dev, MT_PLE_DRR_TABLE_CTRL, drr_ctrl_val);
2108++ drr_sta_status[0] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA0);
2109++ drr_sta_status[1] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA1);
2110++ drr_sta_status[2] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA2);
2111++ drr_sta_status[3] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA3);
2112++ drr_sta_status[4] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA4);
2113++ drr_sta_status[5] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA5);
2114++ drr_sta_status[6] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA6);
2115++ drr_sta_status[7] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA7);
2116++
2117++ if (max_sta_line > 8) {
2118++ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
2119++ mt76_wr(dev, MT_PLE_DRR_TABLE_CTRL, drr_ctrl_val);
2120++ drr_sta_status[8] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA0);
2121++ drr_sta_status[9] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA1);
2122++ drr_sta_status[10] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA2);
2123++ drr_sta_status[11] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA3);
2124++ drr_sta_status[12] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA4);
2125++ drr_sta_status[13] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA5);
2126++ drr_sta_status[14] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA6);
2127++ drr_sta_status[15] = mt76_rr(dev, MT_PLE_DRR_TABLE_RDATA7);
2128++ }
2129++
2130++ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
2131++
2132++ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2133++ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
2134++
2135++ if ((sta_line % 4) == 3)
2136++ seq_printf(s, "\n");
2137++ }
2138++ }
2139++
2140++ return 0;
2141++}
2142++
2143++#define CR_NUM_OF_AC 9
2144++#define ALL_CR_NUM_OF_ALL_AC (CR_NUM_OF_AC * 4)
2145++
2146++
2147++typedef enum _ENUM_UMAC_PORT_T {
2148++ ENUM_UMAC_HIF_PORT_0 = 0,
2149++ ENUM_UMAC_CPU_PORT_1 = 1,
2150++ ENUM_UMAC_LMAC_PORT_2 = 2,
2151++ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
2152++ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
2153++} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
2154++
2155++/* N9 MCU QUEUE LIST */
2156++typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
2157++ ENUM_UMAC_CTX_Q_0 = 0,
2158++ ENUM_UMAC_CTX_Q_1 = 1,
2159++ ENUM_UMAC_CTX_Q_2 = 2,
2160++ ENUM_UMAC_CTX_Q_3 = 3,
2161++ ENUM_UMAC_CRX = 0,
2162++ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
2163++} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
2164++
2165++/* LMAC PLE TX QUEUE LIST */
2166++typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
2167++ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
2168++ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
2169++ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
2170++ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
2171++
2172++ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
2173++ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
2174++ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
2175++ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
2176++
2177++ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
2178++ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
2179++ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
2180++ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
2181++
2182++ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
2183++ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
2184++ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
2185++ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
2186++
2187++ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
2188++ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
2189++ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
2190++ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
2191++
2192++ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
2193++ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
2194++ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
2195++ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
2196++ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
2197++ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
2198++ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
2199++ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
2200++
2201++} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
2202++
2203++typedef struct _EMPTY_QUEUE_INFO_T {
2204++ char *QueueName;
2205++ u32 Portid;
2206++ u32 Queueid;
2207++} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
2208++
2209++static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
2210++ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
2211++ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
2212++ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
2213++ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
2214++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
2215++ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
2216++ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
2217++ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
2218++ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
2219++ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
2220++ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
2221++ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
2222++ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
2223++ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
2224++ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
2225++ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
2226++ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
2227++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
2228++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
2229++ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
2230++ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
2231++};
2232++
2233++static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
2234++ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
2235++ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
2236++ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
2237++ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
2238++ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
2239++ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
2240++ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
2241++ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
2242++ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
2243++ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
2244++ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
2245++ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
2246++ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
2247++ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
2248++ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
2249++ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
2250++ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
2251++ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
2252++ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
2253++ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
2254++ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
2255++ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
2256++ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
2257++ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
2258++ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
2259++ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
2260++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
2261++};
2262++
2263++
2264++
2265++static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
2266++static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
2267++ u32 *sta_pause, u32 *dis_sta_map,
2268++ u32 dumptxd)
2269++{
2270++ int i, j;
2271++ u32 total_nonempty_cnt = 0;
2272++
2273++ for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) { /* show AC Q info */
2274++ for (i = 0; i < 32; i++) {
2275++ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
2276++ u32 hfid, tfid, pktcnt, ac_num = j / CR_NUM_OF_AC, ctrl = 0;
2277++ u32 sta_num = i + (j % CR_NUM_OF_AC) * 32, fl_que_ctrl[3] = {0};
2278++ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
2279++ u32 wmmidx = 0;
2280++ struct mt7915_sta *msta;
2281++ struct mt76_wcid *wcid;
2282++ struct ieee80211_sta *sta = NULL;
2283++
2284++ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
2285++ sta = wcid_to_sta(wcid);
2286++ if (!sta) {
2287++ printk("ERROR!! no found STA wcid=%d\n", sta_num);
2288++ return 0;
2289++ }
2290++ msta = container_of(wcid, struct mt7915_sta, wcid);
2291++ wmmidx = msta->vif->wmm_idx;
2292++
2293++ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_num);
2294++
2295++ fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK;
2296++ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
2297++ fl_que_ctrl[0] |= (ac_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
2298++ fl_que_ctrl[0] |= (sta_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT);
2299++ mt7915_mac_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
2300++ fl_que_ctrl[1] = mt7915_mac_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR);
2301++ fl_que_ctrl[2] = mt7915_mac_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR);
2302++ hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >>
2303++ WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT;
2304++ tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >>
2305++ WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT;
2306++ pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >>
2307++ WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT;
2308++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
2309++ tfid, hfid, pktcnt);
2310++
2311++ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
2312++ ctrl = 2;
2313++
2314++ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
2315++ ctrl = 1;
2316++
2317++ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
2318++ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
2319++
2320++ total_nonempty_cnt++;
2321++
2322++ // TODO
2323++ //if (pktcnt > 0 && dumptxd > 0)
2324++ // ShowTXDInfo(pAd, hfid);
2325++ }
2326++ }
2327++ }
2328++
2329++ return total_nonempty_cnt;
2330++}
2331++
2332++static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
2333++{
2334++ int i;
2335++
2336++ seq_printf(s, "Nonempty TXCMD Q info:\n");
2337++ for (i = 0; i < 31; i++) {
2338++ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
2339++ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
2340++
2341++ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
2342++ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
2343++ fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK;
2344++ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
2345++ WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
2346++ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
2347++ WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
2348++ } else
2349++ continue;
2350++
2351++ mt7915_mac_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
2352++ fl_que_ctrl[1] = mt7915_mac_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR);
2353++ fl_que_ctrl[2] = mt7915_mac_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR);
2354++ hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >>
2355++ WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT;
2356++ tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >>
2357++ WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT;
2358++ pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >>
2359++ WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT;
2360++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
2361++ tfid, hfid, pktcnt);
2362++ }
2363++ }
2364++}
2365++
2366++static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
2367++{
2368++ ple_stat[0] = mt7915_mac_rr(dev, WF_PLE_TOP_QUEUE_EMPTY_ADDR);
2369++
2370++ ple_stat[1] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR);
2371++ ple_stat[2] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR);
2372++ ple_stat[3] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR);
2373++ ple_stat[4] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR);
2374++ ple_stat[5] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR);
2375++ ple_stat[6] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR);
2376++ ple_stat[7] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR);
2377++ ple_stat[8] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR);
2378++ ple_stat[9] = mt7915_mac_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR);
2379++
2380++ ple_stat[10] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR);
2381++ ple_stat[11] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR);
2382++ ple_stat[12] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR);
2383++ ple_stat[13] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR);
2384++ ple_stat[14] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR);
2385++ ple_stat[15] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR);
2386++ ple_stat[16] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR);
2387++ ple_stat[17] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR);
2388++ ple_stat[18] = mt7915_mac_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR);
2389++
2390++ ple_stat[19] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR);
2391++ ple_stat[20] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR);
2392++ ple_stat[21] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR);
2393++ ple_stat[22] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR);
2394++ ple_stat[23] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR);
2395++ ple_stat[24] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR);
2396++ ple_stat[25] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR);
2397++ ple_stat[26] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR);
2398++ ple_stat[27] = mt7915_mac_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR);
2399++
2400++ ple_stat[28] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR);
2401++ ple_stat[29] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR);
2402++ ple_stat[30] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR);
2403++ ple_stat[31] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR);
2404++ ple_stat[32] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR);
2405++ ple_stat[33] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR);
2406++ ple_stat[34] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR);
2407++ ple_stat[35] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR);
2408++ ple_stat[36] = mt7915_mac_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR);
2409++}
2410++
2411++static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
2412++{
2413++ dis_sta_map[0] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP0_ADDR);
2414++ dis_sta_map[1] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP1_ADDR);
2415++ dis_sta_map[2] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP2_ADDR);
2416++ dis_sta_map[3] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP3_ADDR);
2417++ dis_sta_map[4] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP4_ADDR);
2418++ dis_sta_map[5] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP5_ADDR);
2419++ dis_sta_map[6] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP6_ADDR);
2420++ dis_sta_map[7] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP7_ADDR);
2421++ dis_sta_map[8] = mt7915_mac_rr(dev, WF_PLE_TOP_DIS_STA_MAP8_ADDR);
2422++}
2423++
2424++static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
2425++{
2426++ sta_pause[0] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE0_ADDR);
2427++ sta_pause[1] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE1_ADDR);
2428++ sta_pause[2] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE2_ADDR);
2429++ sta_pause[3] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE3_ADDR);
2430++ sta_pause[4] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE4_ADDR);
2431++ sta_pause[5] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE5_ADDR);
2432++ sta_pause[6] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE6_ADDR);
2433++ sta_pause[7] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE7_ADDR);
2434++ sta_pause[8] = mt7915_mac_rr(dev, WF_PLE_TOP_STATION_PAUSE8_ADDR);
2435++}
2436++
2437++static int mt7915_pleinfo_read(struct seq_file *s, void *data)
2438++{
2439++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2440++ u32 ple_buf_ctrl, pg_sz, pg_num;
2441++ u32 ple_stat[ALL_CR_NUM_OF_ALL_AC + 1] = {0}, pg_flow_ctrl[8] = {0};
2442++ u32 ple_native_txcmd_stat;
2443++ u32 ple_txcmd_stat;
2444++ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
2445++ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
2446++ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
2447++ int i, j;
2448++
2449++ ple_buf_ctrl = mt7915_mac_rr(dev, WF_PLE_TOP_PBUF_CTRL_ADDR);
2450++ chip_get_ple_acq_stat(dev, ple_stat);
2451++ ple_txcmd_stat = mt7915_mac_rr(dev, WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR);
2452++ ple_native_txcmd_stat = mt7915_mac_rr(dev, WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR);
2453++ pg_flow_ctrl[0] = mt7915_mac_rr(dev, WF_PLE_TOP_FREEPG_CNT_ADDR);
2454++ pg_flow_ctrl[1] = mt7915_mac_rr(dev, WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR);
2455++ pg_flow_ctrl[2] = mt7915_mac_rr(dev, WF_PLE_TOP_PG_HIF_GROUP_ADDR);
2456++ pg_flow_ctrl[3] = mt7915_mac_rr(dev, WF_PLE_TOP_HIF_PG_INFO_ADDR);
2457++ pg_flow_ctrl[4] = mt7915_mac_rr(dev, WF_PLE_TOP_PG_CPU_GROUP_ADDR);
2458++ pg_flow_ctrl[5] = mt7915_mac_rr(dev, WF_PLE_TOP_CPU_PG_INFO_ADDR);
2459++ pg_flow_ctrl[6] = mt7915_mac_rr(dev, WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR);
2460++ pg_flow_ctrl[7] = mt7915_mac_rr(dev, WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR);
2461++ chip_get_dis_sta_map(dev, dis_sta_map);
2462++ chip_get_sta_pause(dev, sta_pause);
2463++
2464++ seq_printf(s, "PLE Configuration Info:\n");
2465++ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
2466++ WF_PLE_TOP_PBUF_CTRL_ADDR, ple_buf_ctrl);
2467++ pg_sz = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT;
2468++ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
2469++ pg_sz, (pg_sz == 1 ? 128 : 64));
2470++ seq_printf(s, "\t\tPage Offset=%d(in unit of 2KB)\n",
2471++ (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT);
2472++ pg_num = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT;
2473++ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
2474++
2475++ /* Page Flow Control */
2476++ seq_printf(s, "PLE Page Flow Control:\n");
2477++ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
2478++ WF_PLE_TOP_FREEPG_CNT_ADDR, pg_flow_ctrl[0]);
2479++ fpg_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT;
2480++ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
2481++ ffa_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT;
2482++ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
2483++ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
2484++ WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR, pg_flow_ctrl[1]);
2485++ fpg_head = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT;
2486++ fpg_tail = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT;
2487++ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
2488++ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
2489++ WF_PLE_TOP_PG_HIF_GROUP_ADDR, pg_flow_ctrl[2]);
2490++ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
2491++ WF_PLE_TOP_HIF_PG_INFO_ADDR, pg_flow_ctrl[3]);
2492++ hif_min_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT;
2493++ hif_max_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT;
2494++ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
2495++ rpg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT;
2496++ upg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT;
2497++ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
2498++
2499++ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
2500++ WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR, pg_flow_ctrl[6]);
2501++ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
2502++ WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR, pg_flow_ctrl[7]);
2503++ cpu_min_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT;
2504++ cpu_max_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT;
2505++ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
2506++ rpg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT;
2507++ upg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT;
2508++ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
2509++
2510++ seq_printf(s, "\tReserved page counter of CPU group(0x820c0150): 0x%08x\n", pg_flow_ctrl[4]);
2511++ seq_printf(s, "\tCPU group page status(0x820c0154): 0x%08x\n", pg_flow_ctrl[5]);
2512++ cpu_min_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT;
2513++ cpu_max_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT;
2514++ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
2515++ rpg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT;
2516++ upg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT;
2517++ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
2518++
2519++ if ((ple_stat[0] & WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
2520++ for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) {
2521++ if (j % CR_NUM_OF_AC == 0) {
2522++ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / CR_NUM_OF_AC);
2523++ }
2524++
2525++ for (i = 0; i < ALL_CR_NUM_OF_ALL_AC; i++) {
2526++ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
2527++ seq_printf(s, "%d ", i + (j % CR_NUM_OF_AC) * 32);
2528++ }
2529++ }
2530++ }
2531++
2532++ seq_printf(s, "\n");
2533++ }
2534++
2535++ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
2536++
2537++ seq_printf(s, "Nonempty Q info:\n");
2538++
2539++ for (i = 0; i < ALL_CR_NUM_OF_ALL_AC; i++) {
2540++ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
2541++ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
2542++
2543++ if (ple_queue_empty_info[i].QueueName != NULL) {
2544++ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
2545++ fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK;
2546++ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
2547++ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
2548++ } else
2549++ continue;
2550++
2551++ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
2552++ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
2553++ /* band0 set TGID 0, bit31 = 0 */
2554++ mt7915_mac_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, 0x0);
2555++ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
2556++ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
2557++ /* band1 set TGID 1, bit31 = 1 */
2558++ mt7915_mac_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, 0x80000000);
2559++
2560++ mt7915_mac_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
2561++ fl_que_ctrl[1] = mt7915_mac_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR);
2562++ fl_que_ctrl[2] = mt7915_mac_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR);
2563++ hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT;
2564++ tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT;
2565++ pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT;
2566++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
2567++ tfid, hfid, pktcnt);
2568++
2569++ /* TODO */
2570++ //if (pktcnt > 0 && dumptxd > 0)
2571++ // ShowTXDInfo(pAd, hfid);
2572++ }
2573++ }
2574++
2575++ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
2576++ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
2577++
2578++ return 0;
2579++}
2580++
2581++
2582++static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
2583++{
2584++#define BSS_NUM 4
2585++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2586++ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
2587++ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
2588++ u32 mbxsdr[BSS_NUM][4];
2589++ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
2590++ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
2591++ u32 mu_cnt[5];
2592++ u32 ampdu_cnt[3];
2593++ unsigned long per;
2594++
2595++ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
2596++ seq_printf(s, "Band %d MIB Status\n", band_idx);
2597++ seq_printf(s, "===============================\n");
2598++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SCR0_ADDR + band_offset);
2599++ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
2600++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0PBSCR_ADDR + band_offset);
2601++ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
2602++
2603++ msdr6 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR6_ADDR + band_offset);
2604++ msdr7 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR7_ADDR + band_offset);
2605++ msdr8 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR8_ADDR + band_offset);
2606++ msdr9 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR9_ADDR + band_offset);
2607++ msdr10 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR10_ADDR + band_offset);
2608++ msdr16 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR16_ADDR + band_offset);
2609++ msdr17 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR17_ADDR + band_offset);
2610++ msdr18 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR18_ADDR + band_offset);
2611++ msdr19 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR19_ADDR + band_offset);
2612++ msdr20 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR20_ADDR + band_offset);
2613++ msdr21 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR21_ADDR + band_offset);
2614++ ampdu_cnt[0] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR12_ADDR + band_offset);
2615++ ampdu_cnt[1] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR14_ADDR + band_offset);
2616++ ampdu_cnt[2] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR15_ADDR + band_offset);
2617++ ampdu_cnt[1] &= BN0_WF_MIB_TOP_M0SDR14_AMPDU_MPDU_COUNT_MASK;
2618++ ampdu_cnt[2] &= BN0_WF_MIB_TOP_M0SDR15_AMPDU_ACKED_COUNT_MASK;
2619++
2620++ seq_printf(s, "===Phy/Timing Related Counters===\n");
2621++ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
2622++ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
2623++ seq_printf(s, "\tRx_MDRDY_CNT=0x%x\n", msdr10 & BN0_WF_MIB_TOP_M0SDR10_RX_MDRDY_COUNT_MASK);
2624++ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
2625++ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
2626++ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
2627++ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
2628++ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
2629++ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
2630++ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
2631++
2632++ seq_printf(s, "===Tx Related Counters(Generic)===\n");
2633++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR0_ADDR + band_offset);
2634++ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
2635++ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
2636++ dev->dbg.bcn_total_cnt[band_idx] = 0;
2637++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR0_ADDR + band_offset);
2638++ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
2639++ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
2640++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR1_ADDR + band_offset);
2641++ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
2642++ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
2643++ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
2644++ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
2645++ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
2646++ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
2647++ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
2648++
2649++ seq_printf(s, "===MU Related Counters===\n");
2650++ mu_cnt[0] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR34_ADDR + band_offset);
2651++ mu_cnt[1] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR8_ADDR + band_offset);
2652++ mu_cnt[2] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR9_ADDR + band_offset);
2653++ mu_cnt[3] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR10_ADDR + band_offset);
2654++ mu_cnt[4] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR11_ADDR + band_offset);
2655++ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
2656++ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
2657++ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
2658++ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
2659++ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
2660++
2661++ seq_printf(s, "===Rx Related Counters(Generic)===\n");
2662++ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
2663++ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
2664++
2665++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR3_ADDR + band_offset);
2666++ seq_printf(s, "\tRxFCSErrCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR3_RX_FCS_ERROR_COUNT_MASK));
2667++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR4_ADDR + band_offset);
2668++ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
2669++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR11_ADDR + band_offset);
2670++ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
2671++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR5_ADDR + band_offset);
2672++ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
2673++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR22_ADDR + band_offset);
2674++ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
2675++ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
2676++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0SDR23_ADDR + band_offset);
2677++ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
2678++
2679++ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
2680++ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
2681++ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
2682++
2683++ for (idx = 0; idx < BSS_NUM; idx++) {
2684++ btcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
2685++ btbcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
2686++ brcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
2687++ brbcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
2688++ btdcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
2689++ brdcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
2690++ }
2691++
2692++ for (idx = 0; idx < BSS_NUM; idx++) {
2693++ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
2694++ idx, btcr[idx], btdcr[idx], btbcr[idx],
2695++ brcr[idx], brdcr[idx], brbcr[idx]);
2696++ }
2697++
2698++ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
2699++ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
2700++ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
2701++
2702++ for (idx = 0; idx < BSS_NUM; idx++) {
2703++ mbxsdr[idx][0] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
2704++ mbxsdr[idx][1] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
2705++ mbxsdr[idx][2] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
2706++ mbxsdr[idx][3] = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
2707++ }
2708++
2709++ for (idx = 0; idx < BSS_NUM; idx++) {
2710++ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
2711++ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
2712++ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
2713++ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
2714++ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
2715++ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
2716++ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
2717++ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
2718++ }
2719++
2720++ seq_printf(s, "===Dummy delimiter insertion result===\n");
2721++ mac_val0 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR12_ADDR + band_offset);
2722++ mac_val = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR6_ADDR + band_offset);
2723++ mac_val1 = mt7915_mac_rr(dev, BN0_WF_MIB_TOP_M0DR7_ADDR + band_offset);
2724++ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
2725++ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
2726++ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
2727++ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
2728++ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
2729++ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
2730++
2731++ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
2732++ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
2733++ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
2734++
2735++ for (idx = 0; idx < 16; idx++) {
2736++ mbtcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
2737++ mbtbcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
2738++ mbrcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
2739++ mbrbcr[idx] = mt7915_mac_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
2740++ }
2741++
2742++ for (idx = 0; idx < 16; idx++) {
2743++ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
2744++ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
2745++ }
2746++ return 0;
2747++}
2748++
2749++static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
2750++{
2751++ mt7915_mibinfo_read_per_band(s, 0);
2752++ return 0;
2753++}
2754++
2755++static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
2756++{
2757++ mt7915_mibinfo_read_per_band(s, 1);
2758++ return 0;
2759++}
2760++
2761++int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
2762++{
2763++ struct mt7915_dev *dev = phy->dev;
2764++ /* fwlog parser default setting */
2765++ u8 fwlog_def_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2766++ memcpy(dev->dbg.fwlog_server_mac, fwlog_def_mac, ETH_ALEN);
2767++ dev->dbg.fwlog_server_ip = 0xFFFFFFFF;
2768++ scnprintf(dev->dbg.fwlog_ifname, sizeof(dev->dbg.fwlog_ifname), "wlan0");
2769++
2770++ debugfs_create_file("fw_debug_internal", 0600, dir, phy, &fops_fw_debug);
2771++ debugfs_create_file("fw_debug_module", 0600, dir, dev,
2772++ &fops_fw_debug_module);
2773++ debugfs_create_file("fw_debug_level", 0600, dir, dev,
2774++ &fops_fw_debug_level);
2775++ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
2776++ mt7915_wtbl_read);
2777++ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
2778++ mt7915_uwtbl_read);
2779++
2780++ debugfs_create_u32("l1regidx", 0600, dir, &dev->dbg.l1debugfs_reg);
2781++ debugfs_create_file_unsafe("l1regval", 0600, dir, dev,
2782++ &fops_l1regval);
2783++
2784++ debugfs_create_u32("l2regidx", 0600, dir, &dev->dbg.l2debugfs_reg);
2785++ debugfs_create_file_unsafe("l2regval", 0600, dir, dev,
2786++ &fops_l2regval);
2787++
2788++ debugfs_create_u32("mac_regidx", 0600, dir, &dev->dbg.mac_reg);
2789++ debugfs_create_file_unsafe("mac_regval", 0600, dir, dev,
2790++ &fops_mac_regval);
2791++
2792++ debugfs_create_x16("eep_idx", 0600, dir, &dev->dbg.eep_idx);
2793++ debugfs_create_devm_seqfile(dev->mt76.dev, "eep_val", dir,
2794++ mt7915_read_efuse);
2795++
2796++ debugfs_create_file("fwlog_setting", 0600, dir, dev->mt76.dev, &fops_fwlog_server);
2797++
2798++ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
2799++ mt7915_trinfo_read);
2800++
2801++ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
2802++ mt7915_drr_info);
2803++
2804++ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
2805++ mt7915_pleinfo_read);
2806++
2807++ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
2808++ mt7915_mibinfo_band0);
2809++ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
2810++ mt7915_mibinfo_band1);
2811++ return 0;
2812++}
2813++#endif
2814+diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
2815+new file mode 100644
2816+index 00000000..aaacb019
2817+--- /dev/null
2818++++ b/mt7915/mtk_mcu.c
2819+@@ -0,0 +1,485 @@
2820++#include <linux/firmware.h>
2821++#include <linux/fs.h>
2822++#include<linux/inet.h>
2823++#include "mt7915.h"
2824++#include "mcu.h"
2825++#include "mac.h"
2826++
2827++#ifdef MTK_DEBUG
2828++
2829++#define MT_LPON_FRCR MT_WF_LPON(0, 0x314)
2830++
2831++#define FWLOG_PARSER 1
2832++#ifdef FWLOG_PARSER
2833++typedef struct file *RTMP_OS_FD;
2834++typedef struct _OS_FS_INFO_ {
2835++ int fsuid;
2836++ int fsgid;
2837++ mm_segment_t fs;
2838++} OS_FS_INFO;
2839++typedef struct _RTMP_OS_FD {
2840++ RTMP_OS_FD fsFd;
2841++ OS_FS_INFO fsInfo;
2842++ int Status;
2843++ u32 fsize;
2844++} RTMP_OS_FD_EXT;
2845++
2846++#define RTMP_FILE_RDONLY 0x0F01
2847++#define RTMP_FILE_WRONLY 0x0F02
2848++#define RTMP_FILE_CREAT 0x0F03
2849++#define RTMP_FILE_TRUNC 0x0F04
2850++#define RTMP_OS_FS_INFO OS_FS_INFO
2851++
2852++#define FW_BIN_LOG_MAGIC_NUM_OLD 0x44E98CAF
2853++#define FW_BIN_LOG_MAGIC_NUM 0x44D9C99A
2854++#define FW_BIN_LOG_VERSION 0x01
2855++#define FW_BIN_LOG_RSV 0
2856++
2857++RTMP_OS_FD RtmpOSFileOpen(char *pPath, int flag, int mode)
2858++{
2859++ struct file *filePtr;
2860++
2861++ if (flag == RTMP_FILE_RDONLY)
2862++ flag = O_RDONLY;
2863++ else if (flag == RTMP_FILE_WRONLY)
2864++ flag = O_WRONLY;
2865++ else if (flag == RTMP_FILE_CREAT)
2866++ flag = O_CREAT;
2867++ else if (flag == RTMP_FILE_TRUNC)
2868++ flag = O_TRUNC;
2869++
2870++ filePtr = filp_open(pPath, flag, 0);
2871++
2872++ if (IS_ERR(filePtr)) {
2873++ printk("%s(): Error %ld opening %s\n", __func__,
2874++ -PTR_ERR(filePtr), pPath);
2875++ }
2876++
2877++ return (RTMP_OS_FD) filePtr;
2878++}
2879++
2880++
2881++int RtmpOSFileClose(RTMP_OS_FD osfd)
2882++{
2883++ filp_close(osfd, NULL);
2884++ return 0;
2885++}
2886++#define IS_FILE_OPEN_ERR(_fd) ((_fd == NULL) || IS_ERR((_fd)))
2887++
2888++
2889++
2890++static inline void __RtmpOSFSInfoChange(OS_FS_INFO *pOSFSInfo, bool bSet)
2891++{
2892++ if (bSet) {
2893++ /* Save uid and gid used for filesystem access. */
2894++ /* Set user and group to 0 (root) */
2895++#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE)
2896++ pOSFSInfo->fsuid = current->fsuid;
2897++ pOSFSInfo->fsgid = current->fsgid;
2898++ current->fsuid = current->fsgid = 0;
2899++#else
2900++#ifdef CONFIG_UIDGID_STRICT_TYPE_CHECKS
2901++ kuid_t uid;
2902++ kgid_t gid;
2903++
2904++ uid = current_fsuid();
2905++ gid = current_fsgid();
2906++ pOSFSInfo->fsuid = (int)uid.val;
2907++ pOSFSInfo->fsgid = (int)gid.val;
2908++#else
2909++ /* pOSFSInfo->fsuid = (int)(current_fsuid()); */
2910++ /* pOSFSInfo->fsgid = (int)(current_fsgid()); */
2911++#endif
2912++#endif
2913++ pOSFSInfo->fs = get_fs();
2914++ set_fs(KERNEL_DS);
2915++ } else {
2916++ set_fs(pOSFSInfo->fs);
2917++#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE)
2918++ current->fsuid = pOSFSInfo->fsuid;
2919++ current->fsgid = pOSFSInfo->fsgid;
2920++#endif
2921++ }
2922++}
2923++
2924++void RtmpOSFSInfoChange(RTMP_OS_FS_INFO *pOSFSInfoOrg, bool bSet)
2925++{
2926++ __RtmpOSFSInfoChange(pOSFSInfoOrg, bSet);
2927++}
2928++
2929++/*Unify Utility APIs*/
2930++static RTMP_OS_FD_EXT os_file_open(
2931++ u8 * pPath,
2932++ int flag, /* CreateDisposition */
2933++ int file_mode)
2934++{
2935++ RTMP_OS_FD_EXT fd;
2936++ //os_zero_mem(&fd, sizeof(RTMP_OS_FD_EXT));
2937++ memset(&fd, 0, sizeof(RTMP_OS_FD_EXT));
2938++ fd.fsFd = RtmpOSFileOpen(pPath, flag, file_mode);
2939++ fd.Status = IS_FILE_OPEN_ERR(fd.fsFd);
2940++
2941++ if (!fd.Status) {
2942++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)
2943++ fd.fsize = (unsigned long)fd.fsFd->f_dentry->d_inode->i_size;
2944++#else
2945++ fd.fsize = (unsigned long)fd.fsFd->f_path.dentry->d_inode->i_size;
2946++#endif
2947++ RtmpOSFSInfoChange(&fd.fsInfo, true);
2948++ }
2949++
2950++ return fd;
2951++}
2952++
2953++static int os_file_close(
2954++ RTMP_OS_FD_EXT osfd)
2955++{
2956++ int ret;
2957++ ret = RtmpOSFileClose(osfd.fsFd);
2958++
2959++ if (!ret)
2960++ RtmpOSFSInfoChange(&osfd.fsInfo, false);
2961++
2962++ return ret;
2963++}
2964++
2965++static void RtmpOSFileWrite(RTMP_OS_FD osfd, char *pDataPtr, int writeLen)
2966++{
2967++ kernel_write(osfd, pDataPtr, (size_t) writeLen, &osfd->f_pos);
2968++}
2969++
2970++static void
2971++fw_log_to_file(struct mt7915_dev *dev, u8 *fw_log, u16 log_len)
2972++{
2973++ RTMP_OS_FD_EXT srcf;
2974++ u8 Ret;
2975++#define log_path "/tmp/fwlog.bin"
2976++ srcf = os_file_open(log_path, O_WRONLY|O_CREAT|O_APPEND, 0);
2977++ if (srcf.Status) {
2978++ dev_err(dev->mt76.dev, "Open file \"%s\" failed!\n", log_path);
2979++ return;
2980++ }
2981++
2982++ RtmpOSFileWrite(srcf.fsFd, fw_log, log_len);
2983++
2984++ Ret = os_file_close(srcf);
2985++
2986++ if (Ret)
2987++ dev_err(dev->mt76.dev, "File Close Error ! Ret = %d\n", Ret);
2988++}
2989++
2990++typedef struct ip_v4_hdr {
2991++#ifdef RT_BIG_ENDIAN
2992++ u8 version:4, ihl:4;
2993++#else
2994++ u8 ihl:4, version:4;
2995++#endif
2996++ u8 tos;
2997++ u16 tot_len;
2998++ u16 identifier;
2999++} IP_V4_HDR;
3000++
3001++#define LENGTH_802_3_TYPE 2
3002++#define LENGTH_802_3 14
3003++
3004++u16 Checksum16(u8 *pData, int len)
3005++{
3006++ int sum = 0;
3007++
3008++ while (len > 1) {
3009++ sum += *((u16 *)pData);
3010++
3011++ pData = pData + 2;
3012++
3013++ if (sum & 0x80000000)
3014++ sum = (sum & 0xFFFF) + (sum >> 16);
3015++ len -= 2;
3016++ }
3017++
3018++ if (len)
3019++ sum += *((u8 *)pData);
3020++
3021++ while (sum >> 16)
3022++ sum = (sum & 0xFFFF) + (sum >> 16);
3023++
3024++ return ~sum;
3025++}
3026++
3027++static void
3028++fw_log_to_ethernet(struct mt7915_dev *dev, u8 *fw_log, u16 log_len)
3029++{
3030++ u8 s_addr[ETH_ALEN];
3031++ u32 source_ip = 0x00000000, dest_ip = 0xFFFFFFFF;
3032++ u8 ETH_P_AIR_MONITOR[LENGTH_802_3_TYPE] = {0x08, 0x00};
3033++ struct sk_buff *skb = NULL;
3034++ u8 isPadding = 0;
3035++ u8 *data, *header;
3036++ u8 *ip_header, *ip_checksum;
3037++ u8 *udp_header, *udp_checksum, *pseudo_header;
3038++ u16 data_len, header_len;
3039++ IP_V4_HDR *ipv4_hdr_ptr;
3040++ u16 checksum;
3041++ struct net_device *pNetDev = NULL;
3042++ static struct net_device *net_dev = NULL;
3043++ struct net *net= &init_net;
3044++
3045++ /* TODO : how to get net_device via mt7915_dev ?? */
3046++ if (net_dev == NULL)
3047++ {
3048++ for_each_netdev(net, pNetDev)
3049++ {
3050++ if (!strncmp(pNetDev->name, dev->dbg.fwlog_ifname,
3051++ strlen(dev->dbg.fwlog_ifname)))
3052++ {
3053++ net_dev = pNetDev;
3054++ printk("%s: get %s net_dev=%p\n", __func__,
3055++ dev->dbg.fwlog_ifname, net_dev);
3056++ break;
3057++ }
3058++ }
3059++ }
3060++
3061++ if (net_dev)
3062++ {
3063++ /* unicast fwlog pkt - src ip would be x.x.x.254 */
3064++ if (dev->dbg.fwlog_server_ip != 0xFFFFFFFF) {
3065++ dest_ip = dev->dbg.fwlog_server_ip;
3066++ source_ip = (dest_ip & 0x00FFFFFF) | 0xFE000000;
3067++ }
3068++
3069++ header_len = LENGTH_802_3 + 20 + 8; /* 802.3 + IP + UDP */
3070++ if ((log_len % 2) == 0)
3071++ data_len = log_len;
3072++ else {
3073++ data_len = log_len + 1;
3074++ isPadding = 1;
3075++ }
3076++
3077++ skb = dev_alloc_skb(log_len + header_len + 2);
3078++ skb->dev = net_dev;
3079++
3080++ skb_reserve(skb, header_len);
3081++
3082++ /* Prepare payload*/
3083++ data = skb_put(skb, data_len);
3084++
3085++ memcpy(data, fw_log, log_len);
3086++
3087++ if (isPadding)
3088++ *(data + log_len) = 0;
3089++
3090++ /* Prepare UDP header */
3091++ header = skb_push(skb, 8);
3092++
3093++ udp_header = header;
3094++ *(u16 *)header = htons(54321); /* source port */
3095++ header += sizeof(u16);
3096++ *(u16 *)header = htons(55688); /* destination port */
3097++ header += sizeof(u16);
3098++ *(u16 *)header = htons(data_len + 8); /* Length */
3099++ header += sizeof(u16);
3100++ udp_checksum = header;
3101++ *(u16 *)header = htons(0); /* UDP Checksum */
3102++ pseudo_header = udp_header - 12;
3103++ header = pseudo_header;
3104++ *(u32 *)header = source_ip; /* Source IP */
3105++ header += sizeof(u32);
3106++ *(u32 *)header = dest_ip; /* Destination IP */
3107++ header += sizeof(u32);
3108++ *(u16 *)header = htons(data_len + 8); /* Length */
3109++ header += sizeof(u16);
3110++ *(u16 *)header = htons(17); /* Length */
3111++ checksum = Checksum16(pseudo_header, data_len + 8 + 12);
3112++ *(u16 *)udp_checksum = checksum;
3113++
3114++ /* Prepare IP header */
3115++ header = skb_push(skb, 20);
3116++
3117++ ip_header = header;
3118++ ipv4_hdr_ptr = (IP_V4_HDR *)header;
3119++ ipv4_hdr_ptr->version = 4;
3120++ ipv4_hdr_ptr->ihl = 5;
3121++ ipv4_hdr_ptr->tos = 0;
3122++ ipv4_hdr_ptr->tot_len = htons(data_len + 20 + 8);
3123++ ipv4_hdr_ptr->identifier = 0;
3124++ header += sizeof(IP_V4_HDR);
3125++ *(u16 *)header = htons(0x4000); /* Fragmentation flags and offset */
3126++ header += sizeof(u16);
3127++ *header = 7; /* Time to live */
3128++ header++;
3129++ *header = 17; /* Protocol UDP */
3130++ header++;
3131++ ip_checksum = header;
3132++ *(u16 *)header = htons(0); /* IP Checksum */
3133++ header += sizeof(u16);
3134++ *(u32 *)header = source_ip; /* Source IP */
3135++ header += sizeof(u32);
3136++ *(u32 *)header = dest_ip; /* Destination IP */
3137++ checksum = Checksum16(ip_header, 20);
3138++ *(u16 *)ip_checksum = checksum;
3139++
3140++ /* Prepare 802.3 header */
3141++ header = skb_push(skb, LENGTH_802_3);
3142++
3143++ /* Fake a Source Address for transmission */
3144++ memcpy(s_addr, dev->mphy.macaddr, ETH_ALEN);
3145++
3146++ if (s_addr[1] == 0xff)
3147++ s_addr[1] = 0;
3148++ else
3149++ s_addr[1]++;
3150++
3151++ memcpy(header, dev->dbg.fwlog_server_mac, ETH_ALEN);
3152++ memcpy((header + ETH_ALEN), s_addr, ETH_ALEN);
3153++ memcpy((header + (ETH_ALEN*2)), ETH_P_AIR_MONITOR, LENGTH_802_3_TYPE);
3154++
3155++ /* Report to upper layer */
3156++ skb->protocol = eth_type_trans(skb, skb->dev);
3157++ netif_rx(skb);
3158++ }
3159++}
3160++#else
3161++static void
3162++fw_log_to_file(struct mt7915_dev *dev, u8 *fw_log, u32 log_len)
3163++{
3164++ return 0;
3165++}
3166++
3167++static void
3168++fw_log_to_ethernet(struct mt7915_dev *dev, u8 * fw_log, u32 log_len)
3169++{
3170++ return 0;
3171++}
3172++#endif
3173++
3174++void mt7915_mcu_rx_log_message_internal(struct mt7915_dev *dev, struct sk_buff *skb)
3175++{
3176++ struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
3177++ const char *type;
3178++ u16 len = le16_to_cpu(rxd->len) - (sizeof(struct mt7915_mcu_rxd) - sizeof(rxd->rxd));
3179++ u32 magic_num = 0;
3180++
3181++ skb_pull(skb, sizeof(struct mt7915_mcu_rxd));
3182++
3183++ switch (rxd->s2d_index) {
3184++ case 0:
3185++ magic_num = le32_to_cpu(*(u32 *)skb->data);
3186++ if (magic_num == FW_BIN_LOG_MAGIC_NUM ||
3187++ magic_num == FW_BIN_LOG_MAGIC_NUM_OLD) {
3188++ if (dev->dbg.fw_debug == 8)
3189++ fw_log_to_file(dev, skb->data, len);
3190++ else if (dev->dbg.fw_debug == 16 || dev->dbg.fw_debug == 15)
3191++ fw_log_to_ethernet(dev, skb->data, len);
3192++
3193++ return;
3194++ }
3195++ type = "WM";
3196++ break;
3197++ case 2:
3198++ type = "WA";
3199++ break;
3200++ default:
3201++ type = "unknown";
3202++ break;
3203++ }
3204++
3205++ wiphy_info(mt76_hw(dev)->wiphy, "%s: %s", type, skb->data);
3206++}
3207++
3208++#ifdef FWLOG_PARSER
3209++typedef struct _ICS_AGG_HEADER {
3210++ u16 rxByteCount;
3211++ u16 frameCount:5;
3212++ u16 reserved1:6;
3213++ u16 pktType:5;
3214++ u16 reserved2;
3215++ u16 pseFid;
3216++} ICS_AGG_HEADER, *PICS_AGG_HEADER;
3217++
3218++typedef struct _FW_BIN_LOG_HDR_T_OLD {
3219++ u32 u4MagicNum;
3220++ u32 u4Timestamp;
3221++ u16 u2MsgID;
3222++ u16 u2Length;
3223++} FW_BIN_LOG_HDR_T_OLD, *P_FW_BIN_LOG_HDR_T_OLD;
3224++
3225++typedef struct _FW_BIN_LOG_HDR_T {
3226++ u32 u4MagicNum;
3227++ u8 u1Version;
3228++ u8 u1Rsv;
3229++ u16 u2SerialID;
3230++ u32 u4Timestamp;
3231++ u16 u2MsgID;
3232++ u16 u2Length;
3233++} FW_BIN_LOG_HDR_T, *P_FW_BIN_LOG_HDR_T;
3234++
3235++typedef enum _ENUM_DGB_LOG_PKT_TYPE_T {
3236++ DBG_LOG_PKT_TYPE_ICS = 0x0C,
3237++ DBG_LOG_PKT_TYPE_TXV = 0x11,
3238++ DBG_LOG_PKT_TYPE_FTRACE = 0x12,
3239++ DBG_LOG_PKT_TYPE_TRIG_FRAME = 0x13,
3240++} ENUM_HW_LOG_PKT_TYPE_T;
3241++
3242++void mt7915_mcu_rx_ics(struct mt7915_dev *dev, struct sk_buff *skb)
3243++{
3244++ u8 *buffer = NULL;
3245++ u16 msg_len = 0;
3246++ PICS_AGG_HEADER prIcsAggHeader;
3247++
3248++ /* use older fw log header format */
3249++ if (dev->dbg.fw_debug == 15) {
3250++ P_FW_BIN_LOG_HDR_T_OLD log_hdr;
3251++
3252++ prIcsAggHeader = (PICS_AGG_HEADER)skb->data;
3253++ msg_len = prIcsAggHeader->rxByteCount + sizeof(FW_BIN_LOG_HDR_T_OLD);
3254++
3255++ buffer = kmalloc(msg_len, GFP_ATOMIC);
3256++ log_hdr = (P_FW_BIN_LOG_HDR_T_OLD)buffer;
3257++
3258++ /* prepare ICS header */
3259++ log_hdr->u4MagicNum = FW_BIN_LOG_MAGIC_NUM_OLD;
3260++ log_hdr->u4Timestamp = mt76_rr(dev, MT_LPON_FRCR);
3261++ log_hdr->u2MsgID = DBG_LOG_PKT_TYPE_ICS;
3262++ log_hdr->u2Length = prIcsAggHeader->rxByteCount;
3263++
3264++ /* prepare ICS frame */
3265++ memcpy(buffer + sizeof(FW_BIN_LOG_HDR_T_OLD), prIcsAggHeader, prIcsAggHeader->rxByteCount);
3266++ } else {
3267++ P_FW_BIN_LOG_HDR_T log_hdr;
3268++
3269++ prIcsAggHeader = (PICS_AGG_HEADER)skb->data;
3270++ msg_len = prIcsAggHeader->rxByteCount + sizeof(FW_BIN_LOG_HDR_T);
3271++
3272++ buffer = kmalloc(msg_len, GFP_ATOMIC);
3273++ log_hdr = (P_FW_BIN_LOG_HDR_T)buffer;
3274++
3275++ /* prepare ICS header */
3276++ log_hdr->u4MagicNum = FW_BIN_LOG_MAGIC_NUM;
3277++ log_hdr->u1Version = FW_BIN_LOG_VERSION;
3278++ log_hdr->u1Rsv = FW_BIN_LOG_RSV;
3279++ log_hdr->u2SerialID = dev->dbg.fwlog_seq++;
3280++ log_hdr->u4Timestamp = mt76_rr(dev, MT_LPON_FRCR);
3281++ log_hdr->u2MsgID = DBG_LOG_PKT_TYPE_ICS;
3282++ log_hdr->u2Length = prIcsAggHeader->rxByteCount;
3283++
3284++ /* prepare ICS frame */
3285++ memcpy(buffer + sizeof(FW_BIN_LOG_HDR_T), prIcsAggHeader, prIcsAggHeader->rxByteCount);
3286++ }
3287++
3288++ if (msg_len) {
3289++ if (dev->dbg.fw_debug == 8)
3290++ fw_log_to_file(dev, buffer, msg_len);
3291++ if (dev->dbg.fw_debug == 16 || dev->dbg.fw_debug == 15)
3292++ fw_log_to_ethernet(dev, buffer, msg_len);
3293++
3294++ kfree(buffer);
3295++ }
3296++
3297++ dev_kfree_skb(skb);
3298++}
3299++#else
3300++void mt7915_mcu_rx_ics(struct mt7915_dev *dev, struct sk_buff *skb) {
3301++ dev_kfree_skb(skb);
3302++}
3303++#endif
3304++#endif
3305+diff --git a/mt7915/regs.h b/mt7915/regs.h
3306+index ff71f562..e9a5323b 100644
3307+--- a/mt7915/regs.h
3308++++ b/mt7915/regs.h
3309+@@ -33,6 +33,17 @@
3310+ #define MT_PLE_HIF_PG_INFO MT_PLE(0x114)
3311+ #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x500 + 0x40 * (ac) + \
3312+ ((n) << 2))
3313++
3314++#define MT_PLE_DRR_TABLE_CTRL MT_PLE(0x388)
3315++#define MT_PLE_DRR_TABLE_RDATA0 MT_PLE(0x350)
3316++#define MT_PLE_DRR_TABLE_RDATA1 MT_PLE(0x354)
3317++#define MT_PLE_DRR_TABLE_RDATA2 MT_PLE(0x358)
3318++#define MT_PLE_DRR_TABLE_RDATA3 MT_PLE(0x35C)
3319++#define MT_PLE_DRR_TABLE_RDATA4 MT_PLE(0x690)
3320++#define MT_PLE_DRR_TABLE_RDATA5 MT_PLE(0x694)
3321++#define MT_PLE_DRR_TABLE_RDATA6 MT_PLE(0x698)
3322++#define MT_PLE_DRR_TABLE_RDATA7 MT_PLE(0x69c)
3323++
3324+ #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
3325+
3326+ #define MT_PSE_BASE 0xc000
3327+--
3328+2.29.2
3329+
3330diff --git a/package/kernel/mt76/patches/1002-mtk-internal-add-debug-tools-pseinfo-dump-txd.patch b/package/kernel/mt76/patches/1002-mtk-internal-add-debug-tools-pseinfo-dump-txd.patch
3331new file mode 100644
3332index 0000000..83c8677
3333--- /dev/null
3334+++ b/package/kernel/mt76/patches/1002-mtk-internal-add-debug-tools-pseinfo-dump-txd.patch
3335@@ -0,0 +1,886 @@
3336+From 7904c2c4acb150cbe228a8536cf287e1901fe8ad Mon Sep 17 00:00:00 2001
3337+From: MeiChia Chiu <meichia.chiu@mediatek.com>
3338+Date: Wed, 15 Dec 2021 13:34:47 +0800
3339+Subject: [PATCH 2/4] mtk-internal: add debug tools pseinfo, dump txd.
3340+
3341+Signed-off-by: Chih-Min Chen <chih-min.chen@mediatek.com>
3342+---
3343+ mt7915/mt7915.h | 2 +
3344+ mt7915/mt7915_debug.h | 210 +++++++++++++++
3345+ mt7915/mtk_debugfs.c | 596 ++++++++++++++++++++++++++++++++++++++++++
3346+ 3 files changed, 808 insertions(+)
3347+
3348+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
3349+index bbfaa617..de981336 100644
3350+--- a/mt7915/mt7915.h
3351++++ b/mt7915/mt7915.h
3352+@@ -301,6 +301,7 @@ struct mt7915_dev {
3353+ char fwlog_ifname[10];
3354+ u32 bcn_total_cnt[2];
3355+ u16 fwlog_seq;
3356++ u32 token_idx;
3357+ } dbg;
3358+ #endif
3359+ };
3360+@@ -556,5 +557,6 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3361+ int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
3362+ void mt7915_mcu_rx_log_message_internal(struct mt7915_dev *dev, struct sk_buff *skb);
3363+ void mt7915_mcu_rx_ics(struct mt7915_dev *dev, struct sk_buff *skb);
3364++void mtf_dump_tmac_info(u8 *tmac_info);
3365+ #endif
3366+ #endif
3367+diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
3368+index ff8fe503..d39e145f 100644
3369+--- a/mt7915/mt7915_debug.h
3370++++ b/mt7915/mt7915_debug.h
3371+@@ -430,6 +430,203 @@ const struct hif_pci_rx_ring_desc rx_ring_layout[] = {
3372+ #define WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x5dc) // 05DC
3373+ #define WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x5e0) // 05E0
3374+
3375++/* pseinfo related CRs. */
3376++#define WF_PSE_TOP_BASE 0x820C8000
3377++
3378++#define WF_PSE_TOP_PBUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x14) // 8014
3379++#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31]
3380++#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31
3381++#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17]
3382++#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17
3383++#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0]
3384++#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0
3385++#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) // 80B0
3386++#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3387++#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK 0x80000000 // RLS_Q_EMTPY[31]
3388++#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT 31
3389++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3390++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK 0x00800000 // MDP_RXIOC_QUEUE_EMPTY[23]
3391++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT 23
3392++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3393++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK 0x00400000 // MDP_TXIOC_QUEUE_EMPTY[22]
3394++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT 22
3395++#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3396++#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK 0x00200000 // SFD_PARK_QUEUE_EMPTY[21]
3397++#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT 21
3398++#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3399++#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK 0x00100000 // SEC_RX_QUEUE_EMPTY[20]
3400++#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT 20
3401++#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3402++#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK 0x00080000 // SEC_TX_QUEUE_EMPTY[19]
3403++#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT 19
3404++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3405++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK 0x00040000 // MDP_RX_QUEUE_EMPTY[18]
3406++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT 18
3407++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3408++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK 0x00020000 // MDP_TX_QUEUE_EMPTY[17]
3409++#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT 17
3410++#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3411++#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK 0x00010000 // LMAC_TX_QUEUE_EMPTY[16]
3412++#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT 16
3413++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_MASK 0x00002000 // HIF_5_EMPTY[13]
3414++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_SHFT 13
3415++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3416++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_MASK 0x00001000 // HIF_4_EMPTY[12]
3417++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_SHFT 12
3418++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3419++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_MASK 0x00000800 // HIF_3_EMPTY[11]
3420++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_SHFT 11
3421++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3422++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_MASK 0x00000400 // HIF_2_EMPTY[10]
3423++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_SHFT 10
3424++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3425++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_MASK 0x00000200 // HIF_1_EMPTY[9]
3426++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_SHFT 9
3427++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3428++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_MASK 0x00000100 // HIF_0_EMPTY[8]
3429++#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_SHFT 8
3430++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3431++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK 0x00000008 // CPU_Q3_EMPTY[3]
3432++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT 3
3433++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3434++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK 0x00000004 // CPU_Q2_EMPTY[2]
3435++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT 2
3436++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3437++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK 0x00000002 // CPU_Q1_EMPTY[1]
3438++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT 1
3439++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
3440++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK 0x00000001 // CPU_Q0_EMPTY[0]
3441++#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT 0
3442++#define WF_PSE_TOP_FREEPG_CNT_ADDR (WF_PSE_TOP_BASE + 0x100) // 8100
3443++#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16]
3444++#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16
3445++#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0]
3446++#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0
3447++#define WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PSE_TOP_BASE + 0x104) // 8104
3448++#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16]
3449++#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16
3450++#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0]
3451++#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0
3452++#define WF_PSE_TOP_PG_HIF0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x110) // 8110
3453++#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK 0x0FFF0000 // HIF0_MAX_QUOTA[27..16]
3454++#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT 16
3455++#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK 0x00000FFF // HIF0_MIN_QUOTA[11..0]
3456++#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT 0
3457++#define WF_PSE_TOP_HIF0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x114) // 8114
3458++#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK 0x0FFF0000 // HIF0_SRC_CNT[27..16]
3459++#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT 16
3460++#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK 0x00000FFF // HIF0_RSV_CNT[11..0]
3461++#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT 0
3462++#define WF_PSE_TOP_PG_HIF1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x118) // 8118
3463++#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK 0x0FFF0000 // HIF1_MAX_QUOTA[27..16]
3464++#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT 16
3465++#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK 0x00000FFF // HIF1_MIN_QUOTA[11..0]
3466++#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT 0
3467++#define WF_PSE_TOP_HIF1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x11C) // 811C
3468++#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK 0x0FFF0000 // HIF1_SRC_CNT[27..16]
3469++#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT 16
3470++#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK 0x00000FFF // HIF1_RSV_CNT[11..0]
3471++#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT 0
3472++#define WF_PSE_TOP_PG_CPU_GROUP_ADDR (WF_PSE_TOP_BASE + 0x150) // 8150
3473++#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16]
3474++#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16
3475++#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0]
3476++#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0
3477++#define WF_PSE_TOP_CPU_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x154) // 8154
3478++#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16]
3479++#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16
3480++#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0]
3481++#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0
3482++#define WF_PSE_TOP_PG_PLE_GROUP_ADDR (WF_PSE_TOP_BASE + 0x160) // 8160
3483++#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK 0x0FFF0000 // PLE_MAX_QUOTA[27..16]
3484++#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT 16
3485++#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK 0x00000FFF // PLE_MIN_QUOTA[11..0]
3486++#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT 0
3487++#define WF_PSE_TOP_PLE_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x164) // 8164
3488++#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK 0x0FFF0000 // PLE_SRC_CNT[27..16]
3489++#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT 16
3490++#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK 0x00000FFF // PLE_RSV_CNT[11..0]
3491++#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT 0
3492++#define WF_PSE_TOP_PG_LMAC0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x170) // 8170
3493++#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK 0x0FFF0000 // LMAC0_MAX_QUOTA[27..16]
3494++#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT 16
3495++#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK 0x00000FFF // LMAC0_MIN_QUOTA[11..0]
3496++#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT 0
3497++#define WF_PSE_TOP_LMAC0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x174) // 8174
3498++#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK 0x0FFF0000 // LMAC0_SRC_CNT[27..16]
3499++#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT 16
3500++#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK 0x00000FFF // LMAC0_RSV_CNT[11..0]
3501++#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT 0
3502++#define WF_PSE_TOP_PG_LMAC1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x178) // 8178
3503++#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK 0x0FFF0000 // LMAC1_MAX_QUOTA[27..16]
3504++#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT 16
3505++#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK 0x00000FFF // LMAC1_MIN_QUOTA[11..0]
3506++#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT 0
3507++#define WF_PSE_TOP_LMAC1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x17C) // 817C
3508++#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK 0x0FFF0000 // LMAC1_SRC_CNT[27..16]
3509++#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT 16
3510++#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK 0x00000FFF // LMAC1_RSV_CNT[11..0]
3511++#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT 0
3512++#define WF_PSE_TOP_PG_LMAC2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x180) // 8180
3513++#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK 0x0FFF0000 // LMAC2_MAX_QUOTA[27..16]
3514++#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT 16
3515++#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK 0x00000FFF // LMAC2_MIN_QUOTA[11..0]
3516++#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT 0
3517++#define WF_PSE_TOP_LMAC2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x184) // 8184
3518++#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK 0x0FFF0000 // LMAC2_SRC_CNT[27..16]
3519++#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT 16
3520++#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK 0x00000FFF // LMAC2_RSV_CNT[11..0]
3521++#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT 0
3522++#define WF_PSE_TOP_PG_LMAC3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x188) // 8188
3523++#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK 0x0FFF0000 // LMAC3_MAX_QUOTA[27..16]
3524++#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT 16
3525++#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK 0x00000FFF // LMAC3_MIN_QUOTA[11..0]
3526++#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT 0
3527++#define WF_PSE_TOP_LMAC3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x18C) // 818C
3528++#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK 0x0FFF0000 // LMAC3_SRC_CNT[27..16]
3529++#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT 16
3530++#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK 0x00000FFF // LMAC3_RSV_CNT[11..0]
3531++#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT 0
3532++#define WF_PSE_TOP_PG_MDP_GROUP_ADDR (WF_PSE_TOP_BASE + 0x198) // 8198
3533++#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK 0x0FFF0000 // MDP_MAX_QUOTA[27..16]
3534++#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT 16
3535++#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK 0x00000FFF // MDP_MIN_QUOTA[11..0]
3536++#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT 0
3537++#define WF_PSE_TOP_MDP_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x19C) // 819C
3538++#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK 0x0FFF0000 // MDP_SRC_CNT[27..16]
3539++#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT 16
3540++#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK 0x00000FFF // MDP_RSV_CNT[11..0]
3541++#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT 0
3542++#define WF_PSE_TOP_PG_PLE1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x168) // 8168
3543++#define WF_PSE_TOP_PLE1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x16C) // 816C
3544++#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) // 81B0
3545++#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
3546++#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31]
3547++#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31
3548++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
3549++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24]
3550++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
3551++#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
3552++#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_MASK 0x00FFF000 // FL_BUFFER_ADDR[23..12]
3553++#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_SHFT 12
3554++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
3555++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_MASK 0x00000C00 // Q_BUF_PID[11..10]
3556++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
3557++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
3558++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK 0x000003FF // Q_BUF_WLANID[9..0]
3559++#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0
3560++#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) // 81B8
3561++#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR
3562++#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16]
3563++#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16
3564++#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR
3565++#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0]
3566++#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0
3567++#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) // 81BC
3568++#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR
3569++#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0]
3570++#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0
3571++
3572+ /* mibinfo related CRs. */
3573+ #define BN0_WF_MIB_TOP_BASE 0x820ed000
3574+ #define BN1_WF_MIB_TOP_BASE 0x820fd000
3575+@@ -537,5 +734,18 @@ const struct hif_pci_rx_ring_desc rx_ring_layout[] = {
3576+
3577+ #define WF_WTBLON_TOP_B1BTCRn_ADDR (WF_WTBLON_TOP_BASE + 0x1800) // 5800
3578+
3579++/* TXD */
3580++#define MT_TXD1_ETYP BIT(15)
3581++#define MT_TXD1_VLAN BIT(14)
3582++#define MT_TXD1_RMVL BIT(13)
3583++#define MT_TXD1_AMS BIT(13)
3584++#define MT_TXD1_EOSP BIT(12)
3585++#define MT_TXD1_MRD BIT(11)
3586++
3587++#define MT_TXD7_CTXD BIT(26)
3588++#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
3589++
3590++#define MT_TXD7_TAT GENMASK(9, 0)
3591++
3592+ #endif
3593+ #endif
3594+diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
3595+index eaae509a..9072ff3f 100644
3596+--- a/mt7915/mtk_debugfs.c
3597++++ b/mt7915/mtk_debugfs.c
3598+@@ -1862,6 +1862,238 @@ static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3599+ return 0;
3600+ }
3601+
3602++typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3603++ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3604++ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3605++ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3606++} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3607++
3608++static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3609++ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3610++ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3611++ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3612++ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3613++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3614++ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3615++ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3616++ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3617++ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3618++ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3619++ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3620++ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3621++ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3622++ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3623++ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3624++ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3625++ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3626++ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3627++ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3628++ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3629++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3630++ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3631++};
3632++
3633++static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3634++{
3635++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3636++ u32 pse_buf_ctrl, pg_sz, pg_num;
3637++ u32 pse_stat, pg_flow_ctrl[22] = {0};
3638++ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3639++ u32 max_q, min_q, rsv_pg, used_pg;
3640++ int i;
3641++
3642++ pse_buf_ctrl = mt7915_mac_rr(dev, WF_PSE_TOP_PBUF_CTRL_ADDR);
3643++ pse_stat = mt7915_mac_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR);
3644++ pg_flow_ctrl[0] = mt7915_mac_rr(dev, WF_PSE_TOP_FREEPG_CNT_ADDR);
3645++ pg_flow_ctrl[1] = mt7915_mac_rr(dev, WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR);
3646++ pg_flow_ctrl[2] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_HIF0_GROUP_ADDR);
3647++ pg_flow_ctrl[3] = mt7915_mac_rr(dev, WF_PSE_TOP_HIF0_PG_INFO_ADDR);
3648++ pg_flow_ctrl[4] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_HIF1_GROUP_ADDR);
3649++ pg_flow_ctrl[5] = mt7915_mac_rr(dev, WF_PSE_TOP_HIF1_PG_INFO_ADDR);
3650++ pg_flow_ctrl[6] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_CPU_GROUP_ADDR);
3651++ pg_flow_ctrl[7] = mt7915_mac_rr(dev, WF_PSE_TOP_CPU_PG_INFO_ADDR);
3652++ pg_flow_ctrl[8] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_LMAC0_GROUP_ADDR);
3653++ pg_flow_ctrl[9] = mt7915_mac_rr(dev, WF_PSE_TOP_LMAC0_PG_INFO_ADDR);
3654++ pg_flow_ctrl[10] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_LMAC1_GROUP_ADDR);
3655++ pg_flow_ctrl[11] = mt7915_mac_rr(dev, WF_PSE_TOP_LMAC1_PG_INFO_ADDR);
3656++ pg_flow_ctrl[12] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_LMAC2_GROUP_ADDR);
3657++ pg_flow_ctrl[13] = mt7915_mac_rr(dev, WF_PSE_TOP_LMAC2_PG_INFO_ADDR);
3658++ pg_flow_ctrl[14] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_PLE_GROUP_ADDR);
3659++ pg_flow_ctrl[15] = mt7915_mac_rr(dev, WF_PSE_TOP_PLE_PG_INFO_ADDR);
3660++ pg_flow_ctrl[16] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_LMAC3_GROUP_ADDR);
3661++ pg_flow_ctrl[17] = mt7915_mac_rr(dev, WF_PSE_TOP_LMAC3_PG_INFO_ADDR);
3662++ pg_flow_ctrl[18] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_MDP_GROUP_ADDR);
3663++ pg_flow_ctrl[19] = mt7915_mac_rr(dev, WF_PSE_TOP_MDP_PG_INFO_ADDR);
3664++ pg_flow_ctrl[20] = mt7915_mac_rr(dev, WF_PSE_TOP_PG_PLE1_GROUP_ADDR);
3665++ pg_flow_ctrl[21] = mt7915_mac_rr(dev, WF_PSE_TOP_PLE1_PG_INFO_ADDR);
3666++
3667++ /* Configuration Info */
3668++ seq_printf(s, "PSE Configuration Info:\n");
3669++ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3670++ pg_sz = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT;
3671++
3672++ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3673++ seq_printf(s, "\t\tPage Offset=%d(in unit of 64KB)\n",
3674++ (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT);
3675++ pg_num = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT;
3676++ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3677++
3678++ /* Page Flow Control */
3679++ seq_printf(s, "PSE Page Flow Control:\n");
3680++ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3681++ fpg_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT;
3682++ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3683++ ffa_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT;
3684++ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3685++ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3686++ fpg_head = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT;
3687++ fpg_tail = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT;
3688++ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3689++ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3690++ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3691++ min_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT;
3692++ max_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT;
3693++ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3694++ rsv_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT;
3695++ used_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT;
3696++ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3697++ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3698++ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3699++ min_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT;
3700++ max_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT;
3701++ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3702++ rsv_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT;
3703++ used_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT;
3704++ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3705++ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3706++ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3707++ min_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT;
3708++ max_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT;
3709++ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3710++ rsv_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT;
3711++ used_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT;
3712++ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3713++ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3714++ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3715++ min_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT;
3716++ max_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT;
3717++ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3718++ rsv_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT;
3719++ used_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT;
3720++ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3721++ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3722++ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3723++ min_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT;
3724++ max_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT;
3725++ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3726++ rsv_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT;
3727++ used_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT;
3728++ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3729++ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3730++ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3731++ min_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT;
3732++ max_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT;
3733++ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3734++ rsv_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT;
3735++ used_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT;
3736++ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3737++
3738++ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3739++ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3740++ min_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT;
3741++ max_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT;
3742++ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3743++ rsv_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT;
3744++ used_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT;
3745++ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3746++
3747++ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3748++ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3749++ min_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT;
3750++ max_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT;
3751++ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3752++ rsv_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT;
3753++ used_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT;
3754++ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3755++
3756++ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3757++ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3758++ min_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT;
3759++ max_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT;
3760++ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3761++ rsv_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT;
3762++ used_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT;
3763++ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3764++
3765++ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3766++ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3767++ min_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT;
3768++ max_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT;
3769++ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3770++ rsv_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT;
3771++ used_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT;
3772++ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3773++
3774++ /* Queue Empty Status */
3775++ seq_printf(s, "PSE Queue Empty Status:\n");
3776++ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3777++ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%d/%d/%d/%d\n",
3778++ (pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT,
3779++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT),
3780++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT),
3781++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT));
3782++ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%d/%d/%d/%d/%d/%d\n",
3783++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_SHFT),
3784++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_SHFT),
3785++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_SHFT),
3786++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_SHFT),
3787++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_SHFT),
3788++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_SHFT));
3789++ seq_printf(s, "\t\tLMAC TX Q empty=%d\n",
3790++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT));
3791++ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%d/%d\n",
3792++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT),
3793++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT));
3794++ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%d/%d\n",
3795++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT),
3796++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT));
3797++ seq_printf(s, "\t\tSFD PARK Q empty=%d\n",
3798++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT));
3799++ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%d/%d\n",
3800++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT),
3801++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT));
3802++ seq_printf(s, "\t\tRLS Q empty=%d\n",
3803++ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT));
3804++ seq_printf(s, "Nonempty Q info:\n");
3805++
3806++ for (i = 0; i < 31; i++) {
3807++ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3808++ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3809++
3810++ if (pse_queue_empty_info[i].QueueName != NULL) {
3811++ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3812++ fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK;
3813++ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3814++ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3815++ } else
3816++ continue;
3817++
3818++ fl_que_ctrl[0] |= (0x1 << 31);
3819++
3820++ mt7915_mac_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3821++ fl_que_ctrl[1] = mt7915_mac_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR);
3822++ fl_que_ctrl[2] = mt7915_mac_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR);
3823++
3824++ hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT;
3825++ tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT;
3826++ pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT;
3827++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3828++ tfid, hfid, pktcnt);
3829++ }
3830++ }
3831++
3832++ return 0;
3833++}
3834+
3835+ static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3836+ {
3837+@@ -2042,6 +2274,360 @@ static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
3838+ return 0;
3839+ }
3840+
3841++static int mt7915_token_read(struct seq_file *s, void *data)
3842++{
3843++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3844++ int id, count = 0;
3845++ struct mt76_txwi_cache *txwi;
3846++
3847++ seq_printf(s, "Cut through token:\n");
3848++ spin_lock_bh(&dev->mt76.token_lock);
3849++ idr_for_each_entry(&dev->mt76.token, txwi, id) {
3850++ seq_printf(s, "%4d ", id);
3851++ count++;
3852++ if (count % 8 == 0)
3853++ seq_printf(s, "\n");
3854++ }
3855++ spin_unlock_bh(&dev->mt76.token_lock);
3856++ seq_printf(s, "\n");
3857++
3858++ return 0;
3859++}
3860++
3861++struct txd_l {
3862++ u32 txd_0;
3863++ u32 txd_1;
3864++ u32 txd_2;
3865++ u32 txd_3;
3866++ u32 txd_4;
3867++ u32 txd_5;
3868++ u32 txd_6;
3869++ u32 txd_7;
3870++} __packed;
3871++
3872++char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
3873++char *hdr_fmt_str[] = {
3874++ "Non-80211-Frame",
3875++ "Command-Frame",
3876++ "Normal-80211-Frame",
3877++ "enhanced-80211-Frame",
3878++};
3879++/* TMAC_TXD_1.hdr_format */
3880++#define TMI_HDR_FT_NON_80211 0x0
3881++#define TMI_HDR_FT_CMD 0x1
3882++#define TMI_HDR_FT_NOR_80211 0x2
3883++#define TMI_HDR_FT_ENH_80211 0x3
3884++
3885++void mtf_dump_tmac_info(u8 *tmac_info)
3886++{
3887++ struct txd_l *txd = (struct txd_l *)tmac_info;
3888++
3889++ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
3890++ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
3891++
3892++ printk("TMAC_TXD Fields:\n");
3893++ printk("\tTMAC_TXD_0:\n");
3894++
3895++ /* DW0 */
3896++ /* TX Byte Count [15:0] */
3897++ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
3898++
3899++ /* PKT_FT: Packet Format [24:23] */
3900++ printk("\t\tpkt_ft = %ld(%s)\n",
3901++ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
3902++ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
3903++
3904++ /* Q_IDX [31:25] */
3905++ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
3906++
3907++ printk("\tTMAC_TXD_1:\n");
3908++
3909++ /* DW1 */
3910++ /* WLAN Indec [9:0] */
3911++ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
3912++
3913++ /* VTA [10] */
3914++ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
3915++
3916++ /* HF: Header Format [17:16] */
3917++ printk("\t\tHdrFmt = %ld(%s)\n",
3918++ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
3919++ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
3920++ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
3921++
3922++ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
3923++ case TMI_HDR_FT_NON_80211:
3924++ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
3925++ printk("\t\t\tMRD = %d, EOSP = %d,\
3926++ RMVL = %d, VLAN = %d, ETYP = %d\n",
3927++ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
3928++ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
3929++ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
3930++ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
3931++ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
3932++ break;
3933++ case TMI_HDR_FT_NOR_80211:
3934++ /* HEADER_LENGTH [15:11] */
3935++ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
3936++ break;
3937++
3938++ case TMI_HDR_FT_ENH_80211:
3939++ /* EOSP [12], AMS [13] */
3940++ printk("\t\t\tEOSP = %d, AMS = %d\n",
3941++ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
3942++ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
3943++ break;
3944++ }
3945++
3946++ /* Header Padding [19:18] */
3947++ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
3948++
3949++ /* TID [22:20] */
3950++ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
3951++
3952++
3953++ /* UtxB/AMSDU_C/AMSDU [23] */
3954++ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
3955++
3956++ /* OM [29:24] */
3957++ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
3958++
3959++
3960++ /* TGID [30] */
3961++ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
3962++
3963++
3964++ /* FT [31] */
3965++ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
3966++
3967++ printk("\tTMAC_TXD_2:\n");
3968++ /* DW2 */
3969++ /* Subtype [3:0] */
3970++ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
3971++
3972++ /* Type[5:4] */
3973++ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
3974++
3975++ /* NDP [6] */
3976++ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
3977++
3978++ /* NDPA [7] */
3979++ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
3980++
3981++ /* SD [8] */
3982++ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
3983++
3984++ /* RTS [9] */
3985++ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
3986++
3987++ /* BM [10] */
3988++ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
3989++
3990++ /* B [11] */
3991++ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
3992++
3993++ /* DU [12] */
3994++ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
3995++
3996++ /* HE [13] */
3997++ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
3998++
3999++ /* FRAG [15:14] */
4000++ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
4001++
4002++
4003++ /* Remaining Life Time [23:16]*/
4004++ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
4005++ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4006++
4007++ /* Power Offset [29:24] */
4008++ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4009++
4010++ /* FRM [30] */
4011++ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4012++
4013++ /* FR[31] */
4014++ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4015++
4016++
4017++ printk("\tTMAC_TXD_3:\n");
4018++
4019++ /* DW3 */
4020++ /* NA [0] */
4021++ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4022++
4023++ /* PF [1] */
4024++ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4025++
4026++ /* EMRD [2] */
4027++ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4028++
4029++ /* EEOSP [3] */
4030++ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4031++
4032++ /* DAS [4] */
4033++ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4034++
4035++ /* TM [5] */
4036++ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4037++
4038++ /* TX Count [10:6] */
4039++ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4040++
4041++ /* Remaining TX Count [15:11] */
4042++ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4043++
4044++ /* SN [27:16] */
4045++ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4046++
4047++ /* BA_DIS [28] */
4048++ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4049++
4050++ /* Power Management [29] */
4051++ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4052++
4053++ /* PN_VLD [30] */
4054++ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4055++
4056++ /* SN_VLD [31] */
4057++ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4058++
4059++
4060++ /* DW4 */
4061++ printk("\tTMAC_TXD_4:\n");
4062++
4063++ /* PN_LOW [31:0] */
4064++ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4065++
4066++
4067++ /* DW5 */
4068++ printk("\tTMAC_TXD_5:\n");
4069++
4070++ /* PID [7:0] */
4071++ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4072++
4073++ /* TXSFM [8] */
4074++ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4075++
4076++ /* TXS2M [9] */
4077++ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4078++
4079++ /* TXS2H [10] */
4080++ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4081++
4082++ /* ADD_BA [14] */
4083++ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4084++
4085++ /* MD [15] */
4086++ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4087++
4088++ /* PN_HIGH [31:16] */
4089++ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4090++
4091++ /* DW6 */
4092++ printk("\tTMAC_TXD_6:\n");
4093++
4094++ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4095++ /* Fixed BandWidth mode [2:0] */
4096++ printk("\t\tbw = %ld\n", FIELD_GET(MT_TXD6_BW, txd->txd_6));
4097++
4098++ /* DYN_BW [3] */
4099++ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4100++
4101++ /* ANT_ID [7:4] */
4102++ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4103++
4104++ /* SPE_IDX_SEL [10] */
4105++ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4106++
4107++ /* LDPC [11] */
4108++ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4109++
4110++ /* HELTF Type[13:12] */
4111++ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4112++
4113++ /* GI Type [15:14] */
4114++ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4115++
4116++ /* Rate to be Fixed [29:16] */
4117++ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4118++ }
4119++
4120++ /* TXEBF [30] */
4121++ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4122++
4123++ /* TXIBF [31] */
4124++ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4125++
4126++ /* DW7 */
4127++ printk("\tTMAC_TXD_7:\n");
4128++
4129++ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4130++ /* SW Tx Time [9:0] */
4131++ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4132++ } else {
4133++ /* TXD Arrival Time [9:0] */
4134++ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4135++ }
4136++
4137++ /* HW_AMSDU_CAP [10] */
4138++ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4139++
4140++ /* SPE_IDX [15:11] */
4141++ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4142++ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4143++ }
4144++
4145++ /* PSE_FID [27:16] */
4146++ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4147++
4148++ /* Subtype [19:16] */
4149++ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4150++
4151++ /* Type [21:20] */
4152++ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4153++
4154++ /* CTXD_CNT [25:23] */
4155++ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4156++
4157++ /* CTXD [26] */
4158++ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4159++
4160++ /* I [28] */
4161++ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4162++
4163++ /* UT [29] */
4164++ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4165++
4166++ /* TXDLEN [31:30] */
4167++ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4168++}
4169++
4170++
4171++static int mt7915_token_txd_read(struct seq_file *s, void *data)
4172++{
4173++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4174++ struct mt76_txwi_cache *t;
4175++ u8* txwi;
4176++
4177++ seq_printf(s, "\n");
4178++ spin_lock_bh(&dev->mt76.token_lock);
4179++
4180++ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4181++
4182++ spin_unlock_bh(&dev->mt76.token_lock);
4183++ if (t != NULL) {
4184++ struct mt76_dev *mdev = &dev->mt76;
4185++ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4186++ mtf_dump_tmac_info((u8*) txwi);
4187++ seq_printf(s, "\n");
4188++ printk("[SKB]\n");
4189++ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4190++ seq_printf(s, "\n");
4191++ }
4192++ return 0;
4193++}
4194++
4195+ int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
4196+ {
4197+ struct mt7915_dev *dev = phy->dev;
4198+@@ -2088,10 +2674,20 @@ int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
4199+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
4200+ mt7915_pleinfo_read);
4201+
4202++ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
4203++ mt7915_pseinfo_read);
4204++
4205+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4206+ mt7915_mibinfo_band0);
4207+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4208+ mt7915_mibinfo_band1);
4209++
4210++ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
4211++ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
4212++ mt7915_token_read);
4213++ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
4214++ mt7915_token_txd_read);
4215++
4216+ return 0;
4217+ }
4218+ #endif
4219+--
4220+2.29.2
4221+
4222diff --git a/package/kernel/mt76/patches/1003-mt7915-csi-implement-csi-support.patch b/package/kernel/mt76/patches/1003-mt7915-csi-implement-csi-support.patch
4223new file mode 100644
4224index 0000000..40afd06
4225--- /dev/null
4226+++ b/package/kernel/mt76/patches/1003-mt7915-csi-implement-csi-support.patch
4227@@ -0,0 +1,917 @@
4228+From 91d306f7b967f2ea347e020c7d612ffa81e013fc Mon Sep 17 00:00:00 2001
4229+From: Evelyn Tsai <evelyn.tsai@mediatek.com>
4230+Date: Mon, 20 Dec 2021 19:51:11 +0800
4231+Subject: [PATCH 3/4] mt7915: csi: implement csi support
4232+
4233+Work with the latest FW (after 202106)
4234+Last update: 2021/06/22
4235+---
4236+ mt7915/Makefile | 3 +-
4237+ mt7915/init.c | 37 ++++
4238+ mt7915/mcu.c | 111 ++++++++++++
4239+ mt7915/mcu.h | 78 +++++++++
4240+ mt7915/mt7915.h | 20 +++
4241+ mt7915/vendor.c | 452 ++++++++++++++++++++++++++++++++++++++++++++++++
4242+ mt7915/vendor.h | 60 +++++++
4243+ 7 files changed, 760 insertions(+), 1 deletion(-)
4244+ create mode 100644 mt7915/vendor.c
4245+ create mode 100644 mt7915/vendor.h
4246+
4247+diff --git a/mt7915/Makefile b/mt7915/Makefile
4248+index 9511009d..89d84d53 100644
4249+--- a/mt7915/Makefile
4250++++ b/mt7915/Makefile
4251+@@ -1,5 +1,6 @@
4252+ #SPDX-License-Identifier: ISC
4253+
4254++EXTRA_CFLAGS += -DCONFIG_MTK_VENDOR
4255+ obj-$(CONFIG_MT7915E) += mt7915e.o
4256+
4257+ mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
4258+@@ -7,4 +8,4 @@ mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
4259+
4260+ mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
4261+
4262+-mt7915e-y += mtk_debugfs.o mtk_mcu.o
4263++mt7915e-y += mtk_debugfs.o mtk_mcu.o vendor.o
4264+diff --git a/mt7915/init.c b/mt7915/init.c
4265+index 4b56358d..e32cefc7 100644
4266+--- a/mt7915/init.c
4267++++ b/mt7915/init.c
4268+@@ -6,6 +6,7 @@
4269+ #include <linux/hwmon-sysfs.h>
4270+ #include <linux/thermal.h>
4271+ #include "mt7915.h"
4272++#include "mcu.h"
4273+ #include "mac.h"
4274+ #include "mcu.h"
4275+ #include "eeprom.h"
4276+@@ -469,6 +470,11 @@ static int mt7915_register_ext_phy(struct mt7915_dev *dev)
4277+ if (ret)
4278+ goto error;
4279+
4280++#ifdef CONFIG_MTK_VENDOR
4281++ INIT_LIST_HEAD(&phy->csi.csi_list);
4282++ spin_lock_init(&phy->csi.csi_lock);
4283++ mt7915_vendor_register(phy);
4284++#endif
4285+ ret = mt76_register_phy(mphy, true, mt76_rates,
4286+ ARRAY_SIZE(mt76_rates));
4287+ if (ret)
4288+@@ -889,6 +895,25 @@ void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
4289+ }
4290+ }
4291+
4292++#ifdef CONFIG_MTK_VENDOR
4293++static int mt7915_unregister_features(struct mt7915_phy *phy)
4294++{
4295++ struct csi_data *c, *tmp_c;
4296++
4297++ spin_lock_bh(&phy->csi.csi_lock);
4298++ phy->csi.enable = 0;
4299++
4300++ list_for_each_entry_safe(c, tmp_c, &phy->csi.csi_list, node) {
4301++ list_del(&c->node);
4302++ kfree(c);
4303++ }
4304++ spin_unlock_bh(&phy->csi.csi_lock);
4305++
4306++
4307++ return 0;
4308++}
4309++#endif
4310++
4311+ static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
4312+ {
4313+ struct mt7915_phy *phy = mt7915_ext_phy(dev);
4314+@@ -897,6 +922,9 @@ static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
4315+ if (!phy)
4316+ return;
4317+
4318++#ifdef CONFIG_MTK_VENDOR
4319++ mt7915_unregister_features(phy);
4320++#endif
4321+ mt7915_unregister_thermal(phy);
4322+ mt76_unregister_phy(mphy);
4323+ ieee80211_free_hw(mphy->hw);
4324+@@ -938,6 +966,11 @@ int mt7915_register_device(struct mt7915_dev *dev)
4325+ #ifdef CONFIG_NL80211_TESTMODE
4326+ dev->mt76.test_ops = &mt7915_testmode_ops;
4327+ #endif
4328++#ifdef CONFIG_MTK_VENDOR
4329++ INIT_LIST_HEAD(&dev->phy.csi.csi_list);
4330++ spin_lock_init(&dev->phy.csi.csi_lock);
4331++ mt7915_vendor_register(&dev->phy);
4332++#endif
4333+
4334+ /* init led callbacks */
4335+ if (IS_ENABLED(CONFIG_MT76_LEDS)) {
4336+@@ -973,5 +1006,9 @@ void mt7915_unregister_device(struct mt7915_dev *dev)
4337+ mt7915_dma_cleanup(dev);
4338+ tasklet_disable(&dev->irq_tasklet);
4339+
4340++#ifdef CONFIG_MTK_VENDOR
4341++ mt7915_unregister_features(&dev->phy);
4342++#endif
4343++
4344+ mt76_free_device(&dev->mt76);
4345+ }
4346+diff --git a/mt7915/mcu.c b/mt7915/mcu.c
4347+index 3ef873f7..012c52bf 100644
4348+--- a/mt7915/mcu.c
4349++++ b/mt7915/mcu.c
4350+@@ -88,6 +88,10 @@ struct mt7915_fw_region {
4351+ #define HE_PHY(p, c) u8_get_bits(c, IEEE80211_HE_PHY_##p)
4352+ #define HE_MAC(m, c) u8_get_bits(c, IEEE80211_HE_MAC_##m)
4353+
4354++#ifdef CONFIG_MTK_VENDOR
4355++static int mt7915_mcu_report_csi(struct mt7915_dev *dev, struct sk_buff *skb);
4356++#endif
4357++
4358+ static enum mcu_cipher_type
4359+ mt7915_mcu_get_cipher(int cipher)
4360+ {
4361+@@ -548,6 +552,11 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
4362+ IEEE80211_IFACE_ITER_RESUME_ALL,
4363+ mt7915_mcu_cca_finish, dev);
4364+ break;
4365++#ifdef CONFIG_MTK_VENDOR
4366++ case MCU_EXT_EVENT_CSI_REPORT:
4367++ mt7915_mcu_report_csi(dev, skb);
4368++ break;
4369++#endif
4370+ default:
4371+ break;
4372+ }
4373+@@ -4236,3 +4245,105 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
4374+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TWT_AGRT_UPDATE),
4375+ &req, sizeof(req), true);
4376+ }
4377++
4378++#ifdef CONFIG_MTK_VENDOR
4379++int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
4380++ u8 cfg, u8 v1, u32 v2, u8 *mac_addr)
4381++{
4382++ struct mt7915_dev *dev = phy->dev;
4383++ struct mt7915_mcu_csi req = {
4384++ .band = phy != &dev->phy,
4385++ .mode = mode,
4386++ .cfg = cfg,
4387++ .v1 = v1,
4388++ .v2 = cpu_to_le32(v2),
4389++ };
4390++
4391++ if (is_valid_ether_addr(mac_addr))
4392++ ether_addr_copy(req.mac_addr, mac_addr);
4393++
4394++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CSI_CTRL), &req,
4395++ sizeof(req), false);
4396++}
4397++
4398++static int
4399++mt7915_mcu_report_csi(struct mt7915_dev *dev, struct sk_buff *skb)
4400++{
4401++ struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
4402++ struct mt7915_phy *phy = &dev->phy;
4403++ struct mt7915_mcu_csi_report *cr;
4404++ struct csi_data *csi;
4405++ int len, i;
4406++
4407++ skb_pull(skb, sizeof(struct mt7915_mcu_rxd));
4408++
4409++ len = le16_to_cpu(rxd->len) - sizeof(struct mt7915_mcu_rxd) + 24;
4410++ if (len < sizeof(*cr))
4411++ return -EINVAL;
4412++
4413++ cr = (struct mt7915_mcu_csi_report *)skb->data;
4414++
4415++ if (phy->csi.interval &&
4416++ le32_to_cpu(cr->ts) < phy->csi.last_record + phy->csi.interval)
4417++ return 0;
4418++
4419++ csi = kzalloc(sizeof(*csi), GFP_KERNEL);
4420++ if (!csi)
4421++ return -ENOMEM;
4422++
4423++#define SET_CSI_DATA(_field) csi->_field = le32_to_cpu(cr->_field)
4424++ SET_CSI_DATA(ch_bw);
4425++ SET_CSI_DATA(rssi);
4426++ SET_CSI_DATA(snr);
4427++ SET_CSI_DATA(data_num);
4428++ SET_CSI_DATA(data_bw);
4429++ SET_CSI_DATA(pri_ch_idx);
4430++ SET_CSI_DATA(info);
4431++ SET_CSI_DATA(rx_mode);
4432++ SET_CSI_DATA(h_idx);
4433++ SET_CSI_DATA(ts);
4434++
4435++ SET_CSI_DATA(band);
4436++ if (csi->band)
4437++ phy = mt7915_ext_phy(dev);
4438++#undef SET_CSI_DATA
4439++
4440++ for (i = 0; i < csi->data_num; i++) {
4441++ csi->data_i[i] = le16_to_cpu(cr->data_i[i]);
4442++ csi->data_q[i] = le16_to_cpu(cr->data_q[i]);
4443++ }
4444++
4445++ memcpy(csi->ta, cr->ta, ETH_ALEN);
4446++ csi->tx_idx = le32_get_bits(cr->trx_idx, GENMASK(31, 16));
4447++ csi->rx_idx = le32_get_bits(cr->trx_idx, GENMASK(15, 0));
4448++
4449++ INIT_LIST_HEAD(&csi->node);
4450++ spin_lock_bh(&phy->csi.csi_lock);
4451++
4452++ if (!phy->csi.enable) {
4453++ kfree(csi);
4454++ spin_unlock_bh(&phy->csi.csi_lock);
4455++ return 0;
4456++ }
4457++
4458++ list_add_tail(&csi->node, &phy->csi.csi_list);
4459++ phy->csi.count++;
4460++
4461++ if (phy->csi.count > CSI_MAX_BUF_NUM) {
4462++ struct csi_data *old;
4463++
4464++ old = list_first_entry(&phy->csi.csi_list,
4465++ struct csi_data, node);
4466++
4467++ list_del(&old->node);
4468++ kfree(old);
4469++ phy->csi.count--;
4470++ }
4471++
4472++ if (csi->h_idx & BIT(15)) /* last chain */
4473++ phy->csi.last_record = csi->ts;
4474++ spin_unlock_bh(&phy->csi.csi_lock);
4475++
4476++ return 0;
4477++}
4478++#endif
4479+diff --git a/mt7915/mcu.h b/mt7915/mcu.h
4480+index 4636b7dc..2a02bad4 100644
4481+--- a/mt7915/mcu.h
4482++++ b/mt7915/mcu.h
4483+@@ -44,6 +44,7 @@ enum {
4484+ MCU_EXT_EVENT_RDD_REPORT = 0x3a,
4485+ MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
4486+ MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
4487++ MCU_EXT_EVENT_CSI_REPORT = 0xc2,
4488+ };
4489+
4490+ enum {
4491+@@ -292,6 +293,7 @@ enum {
4492+ MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
4493+ MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
4494+ MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
4495++ MCU_EXT_CMD_CSI_CTRL = 0xc2,
4496+ };
4497+
4498+ enum {
4499+@@ -1221,4 +1223,80 @@ enum {
4500+ #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
4501+ #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
4502+
4503++#ifdef CONFIG_MTK_VENDOR
4504++struct mt7915_mcu_csi {
4505++ u8 band;
4506++ u8 mode;
4507++ u8 cfg;
4508++ u8 v1;
4509++ __le32 v2;
4510++ u8 mac_addr[ETH_ALEN];
4511++ u8 _rsv[34];
4512++} __packed;
4513++
4514++struct csi_tlv {
4515++ __le32 tag;
4516++ __le32 len;
4517++} __packed;
4518++
4519++#define CSI_MAX_COUNT 256
4520++#define CSI_MAX_BUF_NUM 3000
4521++
4522++struct mt7915_mcu_csi_report {
4523++ struct csi_tlv _t0;
4524++ __le32 ver;
4525++ struct csi_tlv _t1;
4526++ __le32 ch_bw;
4527++ struct csi_tlv _t2;
4528++ __le32 rssi;
4529++ struct csi_tlv _t3;
4530++ __le32 snr;
4531++ struct csi_tlv _t4;
4532++ __le32 band;
4533++ struct csi_tlv _t5;
4534++ __le32 data_num;
4535++ struct csi_tlv _t6;
4536++ __le16 data_i[CSI_MAX_COUNT];
4537++ struct csi_tlv _t7;
4538++ __le16 data_q[CSI_MAX_COUNT];
4539++ struct csi_tlv _t8;
4540++ __le32 data_bw;
4541++ struct csi_tlv _t9;
4542++ __le32 pri_ch_idx;
4543++ struct csi_tlv _t10;
4544++ u8 ta[8];
4545++ struct csi_tlv _t11;
4546++ __le32 info;
4547++ struct csi_tlv _t12;
4548++ __le32 rx_mode;
4549++ struct csi_tlv _t17;
4550++ __le32 h_idx;
4551++ struct csi_tlv _t18;
4552++ __le32 trx_idx;
4553++ struct csi_tlv _t19;
4554++ __le32 ts;
4555++} __packed;
4556++
4557++struct csi_data {
4558++ u8 ch_bw;
4559++ u16 data_num;
4560++ s16 data_i[CSI_MAX_COUNT];
4561++ s16 data_q[CSI_MAX_COUNT];
4562++ u8 band;
4563++ s8 rssi;
4564++ u8 snr;
4565++ u32 ts;
4566++ u8 data_bw;
4567++ u8 pri_ch_idx;
4568++ u8 ta[ETH_ALEN];
4569++ u32 info;
4570++ u8 rx_mode;
4571++ u32 h_idx;
4572++ u16 tx_idx;
4573++ u16 rx_idx;
4574++
4575++ struct list_head node;
4576++};
4577++#endif
4578++
4579+ #endif
4580+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
4581+index de981336..f3dcf666 100644
4582+--- a/mt7915/mt7915.h
4583++++ b/mt7915/mt7915.h
4584+@@ -242,6 +242,20 @@ struct mt7915_phy {
4585+ u8 spe_idx;
4586+ } test;
4587+ #endif
4588++
4589++#ifdef CONFIG_MTK_VENDOR
4590++ struct {
4591++ struct list_head csi_list;
4592++ spinlock_t csi_lock;
4593++ u32 count;
4594++ bool mask;
4595++ bool reorder;
4596++ bool enable;
4597++
4598++ u32 interval;
4599++ u32 last_record;
4600++ } csi;
4601++#endif
4602+ };
4603+
4604+ struct mt7915_dev {
4605+@@ -553,6 +567,12 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4606+ struct ieee80211_sta *sta, struct dentry *dir);
4607+ #endif
4608+
4609++#ifdef CONFIG_MTK_VENDOR
4610++void mt7915_vendor_register(struct mt7915_phy *phy);
4611++int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
4612++ u8 cfg, u8 v1, u32 v2, u8 *mac_addr);
4613++#endif
4614++
4615+ #ifdef MTK_DEBUG
4616+ int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
4617+ void mt7915_mcu_rx_log_message_internal(struct mt7915_dev *dev, struct sk_buff *skb);
4618+diff --git a/mt7915/vendor.c b/mt7915/vendor.c
4619+new file mode 100644
4620+index 00000000..98fd9c2d
4621+--- /dev/null
4622++++ b/mt7915/vendor.c
4623+@@ -0,0 +1,452 @@
4624++// SPDX-License-Identifier: ISC
4625++/*
4626++ * Copyright (C) 2020, MediaTek Inc. All rights reserved.
4627++ */
4628++
4629++#include <net/netlink.h>
4630++
4631++#include "mt7915.h"
4632++#include "mcu.h"
4633++#include "vendor.h"
4634++
4635++static const struct nla_policy
4636++csi_ctrl_policy[NUM_MTK_VENDOR_ATTRS_CSI_CTRL] = {
4637++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG] = {.type = NLA_NESTED },
4638++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE] = { .type = NLA_U8 },
4639++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE] = { .type = NLA_U8 },
4640++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1] = { .type = NLA_U8 },
4641++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2] = { .type = NLA_U8 },
4642++ [MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR] = { .type = NLA_NESTED },
4643++ [MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL] = { .type = NLA_U32 },
4644++ [MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM] = { .type = NLA_U16 },
4645++ [MTK_VENDOR_ATTR_CSI_CTRL_DATA] = { .type = NLA_NESTED },
4646++};
4647++
4648++struct csi_null_tone {
4649++ u8 start;
4650++ u8 end;
4651++};
4652++
4653++struct csi_reorder{
4654++ u8 dest;
4655++ u8 start;
4656++ u8 end;
4657++};
4658++
4659++struct csi_mask {
4660++ struct csi_null_tone null[10];
4661++ u8 pilot[8];
4662++ struct csi_reorder ro[3];
4663++};
4664++
4665++static const struct csi_mask csi_mask_groups[] = {
4666++ /* OFDM */
4667++ { .null = { { 0 }, { 27, 37 } },
4668++ .ro = { {0, 0, 63} },
4669++ },
4670++ { .null = { { 0, 69 }, { 96 }, { 123, 127 } },
4671++ .ro = { { 0, 96 }, { 38, 70, 95 }, { 1, 97, 122 } },
4672++ },
4673++ { .null = { { 0, 5 }, { 32 }, { 59, 127 } },
4674++ .ro = { { 0, 32 }, { 38, 6, 31 }, { 1, 33, 58 } },
4675++ },
4676++ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 127 } },
4677++ .ro = { { 0, 0, 127 } },
4678++ },
4679++ { .null = { { 0, 133 }, { 160 }, { 187, 255 } },
4680++ .ro = { { 0, 160 }, { 1, 161, 186 }, { 38, 134, 159 } },
4681++ },
4682++ { .null = { { 0, 197 }, { 224 }, { 251, 255 } },
4683++ .ro = { { 0, 224 }, { 1, 225, 250 }, { 38, 198, 223 } },
4684++ },
4685++ { .null = { { 0, 5 }, { 32 }, { 59, 255 } },
4686++ .ro = { { 0, 32 }, { 1, 33, 58 }, { 38, 6, 31 } },
4687++ },
4688++ { .null = { { 0, 69 }, { 96 }, { 123, 255 } },
4689++ .ro = { { 0, 96 }, { 1, 97, 122 }, { 38, 70, 95 } },
4690++ },
4691++ { .null = { { 0, 133 }, { 160 }, { 187, 197 }, { 224 }, { 251, 255 } },
4692++ .ro = { { 0, 192 }, { 2, 198, 250 }, { 74, 134, 186 } },
4693++ },
4694++ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 255 } },
4695++ .ro = { { 0, 64 }, { 2, 70, 122 }, { 74, 6, 58 } },
4696++ },
4697++ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 133 },
4698++ { 160 }, { 187, 197 }, { 224 }, { 251, 255 } },
4699++ .ro = { { 0, 0, 255 } },
4700++ },
4701++
4702++ /* HT/VHT */
4703++ { .null = { { 0 }, { 29, 35 } },
4704++ .pilot = { 7, 21, 43, 57 },
4705++ .ro = { { 0, 0, 63 } },
4706++ },
4707++ { .null = { { 0, 67 }, { 96 }, { 125, 127 } },
4708++ .pilot = { 75, 89, 103, 117 },
4709++ .ro = { { 0, 96 }, { 36, 68, 95 }, { 1, 97, 124 } },
4710++ },
4711++ { .null = { { 0, 3 }, { 32 }, { 61, 127 } },
4712++ .pilot = { 11, 25, 39, 53 },
4713++ .ro = { { 0, 32 }, { 36, 4, 31 }, { 1, 33, 60 } },
4714++ },
4715++ { .null = { { 0, 1 }, { 59, 69 }, { 127 } },
4716++ .pilot = { 11, 25, 53, 75, 103, 117 },
4717++ .ro = { { 0, 0, 127 } },
4718++ },
4719++ { .null = { { 0, 131 }, { 160 }, { 189, 255 } },
4720++ .pilot = { 139, 153, 167, 181 },
4721++ .ro = { { 0, 160 }, { 1, 161, 188 }, { 36, 132, 159 } },
4722++ },
4723++ { .null = { { 0, 195 }, { 224 }, { 253 }, { 255 } },
4724++ .pilot = { 203, 217, 231, 245 },
4725++ .ro = { { 0, 224 }, { 1, 225, 252 }, { 36, 196, 223 } },
4726++ },
4727++ { .null = { { 0, 3 }, { 32 }, { 61, 255 } },
4728++ .pilot = { 11, 25, 39, 53 },
4729++ .ro = { { 0, 32 }, { 1, 33, 60 }, { 36, 4, 31 } },
4730++ },
4731++ { .null = { { 0, 67 }, { 96 }, { 125, 255 } },
4732++ .pilot = { 75, 89, 103, 117 },
4733++ .ro = { { 0, 96 }, { 1, 97, 124 }, { 36, 68, 95 } },
4734++ },
4735++ { .null = { { 0, 133 }, { 191, 193 }, { 251, 255 } },
4736++ .pilot = { 139, 167, 181, 203, 217, 245 },
4737++ .ro = { { 0, 192 }, { 2, 194, 250 }, { 70, 134, 190 } },
4738++ },
4739++ { .null = { { 0, 5 }, { 63, 65 }, { 123, 127 } },
4740++ .pilot = { 11, 39, 53, 75, 89, 117 },
4741++ .ro = { { 0, 64 }, { 2, 66, 122 }, { 70, 6, 62 } },
4742++ },
4743++ { .null = { { 0, 1 }, { 123, 133 }, { 255 } },
4744++ .pilot = { 11, 39, 75, 103, 153, 181, 217, 245 },
4745++ .ro = { { 0, 0, 255 } },
4746++ },
4747++
4748++ /* HE */
4749++ { .null = { { 0 }, { 31, 33 } },
4750++ .pilot = { 12, 29, 35, 52 },
4751++ .ro = { { 0, 0, 63 } },
4752++ },
4753++ { .null = { { 30, 34 }, { 96 } },
4754++ .pilot = { 4, 21, 43, 60, 70, 87, 105, 122 },
4755++ .ro = { { 0, 96 }, { 34, 66, 95 }, { 1, 97, 126 } },
4756++ },
4757++ { .null = { { 32 }, { 94, 98 } },
4758++ .pilot = { 6, 23, 41, 58, 68, 85, 107, 124 },
4759++ .ro = { { 0, 32 }, { 34, 2, 31 }, { 1, 31, 62 } },
4760++ },
4761++ { .null = { { 0 }, { 62, 66 } },
4762++ .pilot = { 9, 26, 36, 53, 75, 92, 102, 119 },
4763++ .ro = { { 0, 0, 127 } },
4764++ },
4765++ { .null = { { 30, 34 }, { 160 } },
4766++ .pilot = { 4, 21, 43, 60, 137, 154, 166, 183 },
4767++ .ro = { { 0, 160 }, { 1, 161, 190 }, { 34, 130, 159 } },
4768++ },
4769++ { .null = { { 94, 98 }, { 224 } },
4770++ .pilot = { 68, 85, 107, 124, 201, 218, 230, 247 },
4771++ .ro = { { 0, 224 }, { 1, 225, 254 }, { 34, 194, 223 } },
4772++ },
4773++ { .null = { { 32 }, { 158, 162 } },
4774++ .pilot = { 9, 26, 38, 55, 132, 149, 171, 188 },
4775++ .ro = { { 0, 32 }, { 1, 33, 62 }, { 34, 2, 31 } },
4776++ },
4777++ { .null = { { 96 }, { 222, 226 } },
4778++ .pilot = { 73, 90, 102, 119, 196, 213, 235, 252 },
4779++ .ro = { { 0, 96 }, { 1, 97, 126 }, { 34, 66, 95 } },
4780++ },
4781++ { .null = { { 62, 66 }, { 192 } },
4782++ .pilot = { 36, 53, 75, 92, 169, 186, 198, 215 },
4783++ .ro = { { 0, 192 }, { 1, 193, 253 }, { 67, 131, 191 } },
4784++ },
4785++ { .null = { { 64 }, { 190, 194 } },
4786++ .pilot = { 41, 58, 70, 87, 164, 181, 203, 220 },
4787++ .ro = { { 0, 64 }, { 1, 65, 125 }, { 67, 3, 63 } },
4788++ },
4789++ { .null = { { 0 }, { 126, 130 } },
4790++ .pilot = { 6, 23, 100, 117, 139, 156, 233, 250 },
4791++ .ro = { { 0, 0, 255 } },
4792++ },
4793++};
4794++
4795++static inline u8 csi_group_idx(u8 mode, u8 ch_bw, u8 data_bw, u8 pri_ch_idx)
4796++{
4797++ if (ch_bw < 2 || data_bw < 1)
4798++ return mode * 11 + ch_bw * ch_bw + pri_ch_idx;
4799++ else
4800++ return mode * 11 + ch_bw * ch_bw + (data_bw + 1) * 2 + pri_ch_idx;
4801++}
4802++
4803++static int mt7915_vendor_csi_ctrl(struct wiphy *wiphy,
4804++ struct wireless_dev *wdev,
4805++ const void *data,
4806++ int data_len)
4807++{
4808++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
4809++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
4810++ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_CSI_CTRL];
4811++ int err;
4812++
4813++ err = nla_parse(tb, MTK_VENDOR_ATTR_CSI_CTRL_MAX, data, data_len,
4814++ csi_ctrl_policy, NULL);
4815++ if (err)
4816++ return err;
4817++
4818++ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_CFG]) {
4819++ u8 mode = 0, type = 0, v1 = 0, v2 = 0;
4820++ u8 mac_addr[ETH_ALEN] = {};
4821++ struct nlattr *cur;
4822++ int rem;
4823++
4824++ nla_for_each_nested(cur, tb[MTK_VENDOR_ATTR_CSI_CTRL_CFG], rem) {
4825++ switch(nla_type(cur)) {
4826++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE:
4827++ mode = nla_get_u8(cur);
4828++ break;
4829++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE:
4830++ type = nla_get_u8(cur);
4831++ break;
4832++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1:
4833++ v1 = nla_get_u8(cur);
4834++ break;
4835++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2:
4836++ v2 = nla_get_u8(cur);
4837++ break;
4838++ default:
4839++ return -EINVAL;
4840++ };
4841++ }
4842++
4843++ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR]) {
4844++ int idx = 0;
4845++
4846++ nla_for_each_nested(cur, tb[MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR], rem) {
4847++ mac_addr[idx++] = nla_get_u8(cur);
4848++ }
4849++ }
4850++
4851++ mt7915_mcu_set_csi(phy, mode, type, v1, v2, mac_addr);
4852++
4853++ spin_lock_bh(&phy->csi.csi_lock);
4854++
4855++ phy->csi.enable = !!mode;
4856++
4857++ if (mode == 2 && type == 5) {
4858++ if (v1 >= 1)
4859++ phy->csi.mask = 1;
4860++ if (v1 == 2)
4861++ phy->csi.reorder = 1;
4862++ }
4863++
4864++ /* clean up old csi stats */
4865++ if ((mode == 0 || mode == 2) && !list_empty(&phy->csi.csi_list)) {
4866++ struct csi_data *c, *tmp_c;
4867++
4868++ list_for_each_entry_safe(c, tmp_c, &phy->csi.csi_list,
4869++ node) {
4870++ list_del(&c->node);
4871++ kfree(c);
4872++ phy->csi.count--;
4873++ }
4874++ } else if (mode == 1) {
4875++ phy->csi.last_record = 0;
4876++ }
4877++
4878++ spin_unlock_bh(&phy->csi.csi_lock);
4879++ }
4880++
4881++ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL])
4882++ phy->csi.interval = nla_get_u32(tb[MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL]);
4883++
4884++ return 0;
4885++}
4886++
4887++static void
4888++mt7915_vendor_csi_tone_mask(struct mt7915_phy *phy, struct csi_data *csi)
4889++{
4890++ static const u8 mode_map[] = {
4891++ [MT_PHY_TYPE_OFDM] = 0,
4892++ [MT_PHY_TYPE_HT] = 1,
4893++ [MT_PHY_TYPE_VHT] = 1,
4894++ [MT_PHY_TYPE_HE_SU] = 2,
4895++ };
4896++ const struct csi_mask *cmask;
4897++ int i;
4898++
4899++ if (csi->rx_mode == MT_PHY_TYPE_CCK || !phy->csi.mask)
4900++ return;
4901++
4902++ if (csi->data_bw == IEEE80211_STA_RX_BW_40)
4903++ csi->pri_ch_idx /= 2;
4904++
4905++ cmask = &csi_mask_groups[csi_group_idx(mode_map[csi->rx_mode],
4906++ csi->ch_bw,
4907++ csi->data_bw,
4908++ csi->pri_ch_idx)];
4909++
4910++ for (i = 0; i < 10; i++) {
4911++ const struct csi_null_tone *ntone = &cmask->null[i];
4912++ u8 start = ntone->start;
4913++ u8 end = ntone->end;
4914++ int j;
4915++
4916++ if (!start && !end && i > 0)
4917++ break;
4918++
4919++ if (!end)
4920++ end = start;
4921++
4922++ for (j = start; j <= end; j++) {
4923++ csi->data_i[j] = 0;
4924++ csi->data_q[j] = 0;
4925++ }
4926++ }
4927++
4928++ for (i = 0; i < 8; i++) {
4929++ u8 pilot = cmask->pilot[i];
4930++
4931++ if (!pilot)
4932++ break;
4933++
4934++ csi->data_i[pilot] = 0;
4935++ csi->data_q[pilot] = 0;
4936++ }
4937++
4938++ if (!phy->csi.reorder)
4939++ return;
4940++
4941++ for (i = 0; i < 3; i++) {
4942++ const struct csi_reorder *ro = &cmask->ro[i];
4943++ u8 dest = ro->dest;
4944++ u8 start = ro->start;
4945++ u8 end = ro->end;
4946++
4947++ if (!dest && !start && !end)
4948++ break;
4949++
4950++ if (dest == start)
4951++ continue;
4952++
4953++ if (end) {
4954++ memmove(&csi->data_i[dest], &csi->data_i[start],
4955++ end - start + 1);
4956++ memmove(&csi->data_q[dest], &csi->data_q[start],
4957++ end - start + 1);
4958++ } else {
4959++ csi->data_i[dest] = csi->data_i[start];
4960++ csi->data_q[dest] = csi->data_q[start];
4961++ }
4962++ }
4963++}
4964++
4965++static int
4966++mt7915_vendor_csi_ctrl_dump(struct wiphy *wiphy, struct wireless_dev *wdev,
4967++ struct sk_buff *skb, const void *data, int data_len,
4968++ unsigned long *storage)
4969++{
4970++#define RESERVED_SET BIT(31)
4971++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
4972++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
4973++ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_CSI_CTRL];
4974++ int err = 0;
4975++
4976++ if (*storage & RESERVED_SET) {
4977++ if ((*storage & GENMASK(15, 0)) == 0)
4978++ return -ENOENT;
4979++ (*storage)--;
4980++ }
4981++
4982++ if (data) {
4983++ err = nla_parse(tb, MTK_VENDOR_ATTR_CSI_CTRL_MAX, data, data_len,
4984++ csi_ctrl_policy, NULL);
4985++ if (err)
4986++ return err;
4987++ }
4988++
4989++ if (!(*storage & RESERVED_SET) && tb[MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM]) {
4990++ *storage = nla_get_u16(tb[MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM]);
4991++ *storage |= RESERVED_SET;
4992++ }
4993++
4994++ spin_lock_bh(&phy->csi.csi_lock);
4995++
4996++ if (!list_empty(&phy->csi.csi_list)) {
4997++ struct csi_data *csi;
4998++ void *a, *b;
4999++ int i;
5000++
5001++ csi = list_first_entry(&phy->csi.csi_list, struct csi_data, node);
5002++
5003++ mt7915_vendor_csi_tone_mask(phy, csi);
5004++
5005++ a = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_CTRL_DATA);
5006++
5007++ if (nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_VER, 1) ||
5008++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_RSSI, csi->rssi) ||
5009++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_SNR, csi->snr) ||
5010++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_BW, csi->data_bw) ||
5011++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_CH_IDX, csi->pri_ch_idx) ||
5012++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_MODE, csi->rx_mode))
5013++ goto out;
5014++
5015++ if (nla_put_u16(skb, MTK_VENDOR_ATTR_CSI_DATA_TX_ANT, csi->tx_idx) ||
5016++ nla_put_u16(skb, MTK_VENDOR_ATTR_CSI_DATA_RX_ANT, csi->rx_idx))
5017++ goto out;
5018++
5019++ if (nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_INFO, csi->info) ||
5020++ nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_H_IDX, csi->h_idx) ||
5021++ nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_TS, csi->ts))
5022++ goto out;
5023++
5024++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_TA);
5025++ for (i = 0; i < ARRAY_SIZE(csi->ta); i++)
5026++ if (nla_put_u8(skb, i, csi->ta[i]))
5027++ goto out;
5028++ nla_nest_end(skb, b);
5029++
5030++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_I);
5031++ for (i = 0; i < ARRAY_SIZE(csi->data_i); i++)
5032++ if (nla_put_u16(skb, i, csi->data_i[i]))
5033++ goto out;
5034++ nla_nest_end(skb, b);
5035++
5036++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_Q);
5037++ for (i = 0; i < ARRAY_SIZE(csi->data_q); i++)
5038++ if (nla_put_u16(skb, i, csi->data_q[i]))
5039++ goto out;
5040++ nla_nest_end(skb, b);
5041++
5042++ nla_nest_end(skb, a);
5043++
5044++ list_del(&csi->node);
5045++ kfree(csi);
5046++ phy->csi.count--;
5047++
5048++ err = phy->csi.count;
5049++ }
5050++out:
5051++ spin_unlock_bh(&phy->csi.csi_lock);
5052++
5053++ return err;
5054++}
5055++
5056++static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
5057++ {
5058++ .info = {
5059++ .vendor_id = MTK_NL80211_VENDOR_ID,
5060++ .subcmd = MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL,
5061++ },
5062++ .flags = WIPHY_VENDOR_CMD_NEED_NETDEV |
5063++ WIPHY_VENDOR_CMD_NEED_RUNNING,
5064++ .doit = mt7915_vendor_csi_ctrl,
5065++ .dumpit = mt7915_vendor_csi_ctrl_dump,
5066++ .policy = csi_ctrl_policy,
5067++ .maxattr = MTK_VENDOR_ATTR_CSI_CTRL_MAX,
5068++ }
5069++};
5070++
5071++void mt7915_vendor_register(struct mt7915_phy *phy)
5072++{
5073++ phy->mt76->hw->wiphy->vendor_commands = mt7915_vendor_commands;
5074++ phy->mt76->hw->wiphy->n_vendor_commands = ARRAY_SIZE(mt7915_vendor_commands);
5075++}
5076+diff --git a/mt7915/vendor.h b/mt7915/vendor.h
5077+new file mode 100644
5078+index 00000000..9d3db2a7
5079+--- /dev/null
5080++++ b/mt7915/vendor.h
5081+@@ -0,0 +1,60 @@
5082++#ifndef __MT7915_VENDOR_H
5083++#define __MT7915_VENDOR_H
5084++
5085++#define MTK_NL80211_VENDOR_ID 0x0ce7
5086++
5087++enum mtk_nl80211_vendor_subcmds {
5088++ MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL = 0xc2,
5089++};
5090++
5091++enum mtk_vendor_attr_csi_ctrl {
5092++ MTK_VENDOR_ATTR_CSI_CTRL_UNSPEC,
5093++
5094++ MTK_VENDOR_ATTR_CSI_CTRL_CFG,
5095++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE,
5096++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE,
5097++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1,
5098++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2,
5099++ MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR,
5100++ MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL,
5101++
5102++ MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM,
5103++
5104++ MTK_VENDOR_ATTR_CSI_CTRL_DATA,
5105++
5106++ /* keep last */
5107++ NUM_MTK_VENDOR_ATTRS_CSI_CTRL,
5108++ MTK_VENDOR_ATTR_CSI_CTRL_MAX =
5109++ NUM_MTK_VENDOR_ATTRS_CSI_CTRL - 1
5110++};
5111++
5112++enum mtk_vendor_attr_csi_data {
5113++ MTK_VENDOR_ATTR_CSI_DATA_UNSPEC,
5114++ MTK_VENDOR_ATTR_CSI_DATA_PAD,
5115++
5116++ MTK_VENDOR_ATTR_CSI_DATA_VER,
5117++ MTK_VENDOR_ATTR_CSI_DATA_TS,
5118++ MTK_VENDOR_ATTR_CSI_DATA_RSSI,
5119++ MTK_VENDOR_ATTR_CSI_DATA_SNR,
5120++ MTK_VENDOR_ATTR_CSI_DATA_BW,
5121++ MTK_VENDOR_ATTR_CSI_DATA_CH_IDX,
5122++ MTK_VENDOR_ATTR_CSI_DATA_TA,
5123++ MTK_VENDOR_ATTR_CSI_DATA_I,
5124++ MTK_VENDOR_ATTR_CSI_DATA_Q,
5125++ MTK_VENDOR_ATTR_CSI_DATA_INFO,
5126++ MTK_VENDOR_ATTR_CSI_DATA_RSVD1,
5127++ MTK_VENDOR_ATTR_CSI_DATA_RSVD2,
5128++ MTK_VENDOR_ATTR_CSI_DATA_RSVD3,
5129++ MTK_VENDOR_ATTR_CSI_DATA_RSVD4,
5130++ MTK_VENDOR_ATTR_CSI_DATA_TX_ANT,
5131++ MTK_VENDOR_ATTR_CSI_DATA_RX_ANT,
5132++ MTK_VENDOR_ATTR_CSI_DATA_MODE,
5133++ MTK_VENDOR_ATTR_CSI_DATA_H_IDX,
5134++
5135++ /* keep last */
5136++ NUM_MTK_VENDOR_ATTRS_CSI_DATA,
5137++ MTK_VENDOR_ATTR_CSI_DATA_MAX =
5138++ NUM_MTK_VENDOR_ATTRS_CSI_DATA - 1
5139++};
5140++
5141++#endif
5142+--
5143+2.29.2
5144+
5145diff --git a/package/kernel/mt76/patches/1004-mt7915-air-monitor-support.patch b/package/kernel/mt76/patches/1004-mt7915-air-monitor-support.patch
5146new file mode 100644
5147index 0000000..2d9c6b8
5148--- /dev/null
5149+++ b/package/kernel/mt76/patches/1004-mt7915-air-monitor-support.patch
5150@@ -0,0 +1,551 @@
5151+From 40fd2c08e1505e643e838e109a5a6b70ba88f78e Mon Sep 17 00:00:00 2001
5152+From: Evelyn Tsai <evelyn.tsai@mediatek.com>
5153+Date: Mon, 20 Dec 2021 19:52:40 +0800
5154+Subject: [PATCH 4/4] mt7915: air monitor support
5155+
5156+---
5157+ mt7915/mac.c | 4 +
5158+ mt7915/main.c | 3 +
5159+ mt7915/mcu.h | 3 +
5160+ mt7915/mt7915.h | 34 +++++
5161+ mt7915/vendor.c | 359 ++++++++++++++++++++++++++++++++++++++++++++++++
5162+ mt7915/vendor.h | 38 +++++
5163+ 6 files changed, 441 insertions(+)
5164+
5165+diff --git a/mt7915/mac.c b/mt7915/mac.c
5166+index 6d5ec580..084a597e 100644
5167+--- a/mt7915/mac.c
5168++++ b/mt7915/mac.c
5169+@@ -791,6 +791,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
5170+ seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
5171+ qos_ctl = *ieee80211_get_qos_ctl(hdr);
5172+ }
5173++#ifdef CONFIG_MTK_VENDOR
5174++ if (phy->amnt_ctrl.enable)
5175++ mt7915_vendor_amnt_fill_rx(phy, skb);
5176++#endif
5177+ } else {
5178+ status->flag |= RX_FLAG_8023;
5179+ }
5180+diff --git a/mt7915/main.c b/mt7915/main.c
5181+index 31fceeed..8588d78d 100644
5182+--- a/mt7915/main.c
5183++++ b/mt7915/main.c
5184+@@ -686,6 +686,9 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
5185+ if (ret)
5186+ return ret;
5187+
5188++#ifdef CONFIG_MTK_VENDOR
5189++ mt7915_vendor_amnt_sta_remove(mvif->phy, sta);
5190++#endif
5191+ return mt7915_mcu_add_rate_ctrl(dev, vif, sta, false);
5192+ }
5193+
5194+diff --git a/mt7915/mcu.h b/mt7915/mcu.h
5195+index 2a02bad4..767cef62 100644
5196+--- a/mt7915/mcu.h
5197++++ b/mt7915/mcu.h
5198+@@ -293,7 +293,10 @@ enum {
5199+ MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
5200+ MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
5201+ MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
5202++#ifdef CONFIG_MTK_VENDOR
5203++ MCU_EXT_CMD_SMESH_CTRL = 0xae,
5204+ MCU_EXT_CMD_CSI_CTRL = 0xc2,
5205++#endif
5206+ };
5207+
5208+ enum {
5209+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
5210+index f3dcf666..2547b5dd 100644
5211+--- a/mt7915/mt7915.h
5212++++ b/mt7915/mt7915.h
5213+@@ -200,6 +200,35 @@ struct mt7915_hif {
5214+ int irq;
5215+ };
5216+
5217++#ifdef CONFIG_MTK_VENDOR
5218++#define MT7915_AIR_MONITOR_MAX_ENTRY 16
5219++#define MT7915_AIR_MONITOR_MAX_GROUP MT7915_AIR_MONITOR_MAX_ENTRY >> 2
5220++
5221++struct mt7915_air_monitor_group {
5222++ bool enable;
5223++ bool used[2];
5224++};
5225++
5226++struct mt7915_air_monitor_entry {
5227++ bool enable;
5228++
5229++ u8 group_idx;
5230++ u8 group_used_idx;
5231++ u8 muar_idx;
5232++ u8 addr[ETH_ALEN];
5233++ unsigned int last_seen;
5234++ s8 rssi[4];
5235++ struct ieee80211_sta *sta;
5236++};
5237++
5238++struct mt7915_air_monitor_ctrl {
5239++ u8 enable;
5240++
5241++ struct mt7915_air_monitor_group group[MT7915_AIR_MONITOR_MAX_GROUP];
5242++ struct mt7915_air_monitor_entry entry[MT7915_AIR_MONITOR_MAX_ENTRY];
5243++};
5244++#endif
5245++
5246+ struct mt7915_phy {
5247+ struct mt76_phy *mt76;
5248+ struct mt7915_dev *dev;
5249+@@ -255,6 +284,8 @@ struct mt7915_phy {
5250+ u32 interval;
5251+ u32 last_record;
5252+ } csi;
5253++
5254++ struct mt7915_air_monitor_ctrl amnt_ctrl;
5255+ #endif
5256+ };
5257+
5258+@@ -571,6 +602,9 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5259+ void mt7915_vendor_register(struct mt7915_phy *phy);
5260+ int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
5261+ u8 cfg, u8 v1, u32 v2, u8 *mac_addr);
5262++void mt7915_vendor_amnt_fill_rx(struct mt7915_phy *phy, struct sk_buff *skb);
5263++int mt7915_vendor_amnt_sta_remove(struct mt7915_phy *phy,
5264++ struct ieee80211_sta *sta);
5265+ #endif
5266+
5267+ #ifdef MTK_DEBUG
5268+diff --git a/mt7915/vendor.c b/mt7915/vendor.c
5269+index 98fd9c2d..b94d787e 100644
5270+--- a/mt7915/vendor.c
5271++++ b/mt7915/vendor.c
5272+@@ -430,6 +430,353 @@ out:
5273+ return err;
5274+ }
5275+
5276++static const struct nla_policy
5277++amnt_ctrl_policy[NUM_MTK_VENDOR_ATTRS_AMNT_CTRL] = {
5278++ [MTK_VENDOR_ATTR_AMNT_CTRL_SET] = {.type = NLA_NESTED },
5279++ [MTK_VENDOR_ATTR_AMNT_CTRL_DUMP] = { .type = NLA_NESTED },
5280++};
5281++
5282++static const struct nla_policy
5283++amnt_set_policy[NUM_MTK_VENDOR_ATTRS_AMNT_SET] = {
5284++ [MTK_VENDOR_ATTR_AMNT_SET_INDEX] = {.type = NLA_U8 },
5285++ [MTK_VENDOR_ATTR_AMNT_SET_MACADDR] = { .type = NLA_NESTED },
5286++};
5287++
5288++static const struct nla_policy
5289++amnt_dump_policy[NUM_MTK_VENDOR_ATTRS_AMNT_DUMP] = {
5290++ [MTK_VENDOR_ATTR_AMNT_DUMP_INDEX] = {.type = NLA_U8 },
5291++ [MTK_VENDOR_ATTR_AMNT_DUMP_LEN] = { .type = NLA_U8 },
5292++ [MTK_VENDOR_ATTR_AMNT_DUMP_RESULT] = { .type = NLA_NESTED },
5293++};
5294++
5295++struct mt7915_amnt_data {
5296++ u8 idx;
5297++ u8 addr[ETH_ALEN];
5298++ s8 rssi[4];
5299++ u32 last_seen;
5300++};
5301++
5302++struct mt7915_smesh {
5303++ u8 band;
5304++ u8 write;
5305++ u8 enable;
5306++ bool a2;
5307++ bool a1;
5308++ bool data;
5309++ bool mgnt;
5310++ bool ctrl;
5311++} __packed;
5312++
5313++struct mt7915_smesh_event {
5314++ u8 band;
5315++ __le32 value;
5316++} __packed;
5317++
5318++static int
5319++mt7915_vendor_smesh_ctrl(struct mt7915_phy *phy, u8 write,
5320++ u8 enable, u32 *value)
5321++{
5322++ struct mt7915_dev *dev = phy->dev;
5323++ struct mt7915_smesh req = {
5324++ .band = phy != &dev->phy,
5325++ .write = write,
5326++ .enable = enable,
5327++ .a2 = 1,
5328++ .a1 = 1,
5329++ .data = 1,
5330++ };
5331++ struct mt7915_smesh_event *res;
5332++ struct sk_buff *skb;
5333++ int ret = 0;
5334++
5335++ ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_EXT_CMD(SMESH_CTRL),
5336++ &req, sizeof(req), !write, &skb);
5337++
5338++ if (ret || write)
5339++ return ret;
5340++
5341++ res = (struct mt7915_smesh_event *) skb->data;
5342++
5343++ if (!value)
5344++ return -EINVAL;
5345++
5346++ *value = res->value;
5347++
5348++ dev_kfree_skb(skb);
5349++
5350++ return 0;
5351++}
5352++
5353++static int
5354++mt7915_vendor_amnt_muar(struct mt7915_phy *phy, u8 muar_idx, u8 *addr)
5355++{
5356++ struct mt7915_dev *dev = phy->dev;
5357++ struct {
5358++ u8 mode;
5359++ u8 force_clear;
5360++ u8 clear_bitmap[8];
5361++ u8 entry_count;
5362++ u8 write;
5363++ u8 band;
5364++
5365++ u8 index;
5366++ u8 bssid;
5367++ u8 addr[ETH_ALEN];
5368++ } __packed req = {
5369++ .entry_count = 1,
5370++ .write = 1,
5371++ .band = phy != &dev->phy,
5372++ .index = muar_idx,
5373++ };
5374++
5375++ ether_addr_copy(req.addr, addr);
5376++
5377++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MUAR_UPDATE), &req,
5378++ sizeof(req), true);
5379++}
5380++
5381++static int
5382++mt7915_vendor_amnt_set_en(struct mt7915_phy *phy, u8 enable)
5383++{
5384++ u32 status;
5385++ int ret;
5386++
5387++ ret = mt7915_vendor_smesh_ctrl(phy, 0, enable, &status);
5388++ if (ret)
5389++ return ret;
5390++
5391++ status = status & 0xff;
5392++
5393++ if (status == enable)
5394++ return 0;
5395++
5396++ ret = mt7915_vendor_smesh_ctrl(phy, 1, enable, &status);
5397++ if (ret)
5398++ return ret;
5399++
5400++ return 0;
5401++}
5402++
5403++static int
5404++mt7915_vendor_amnt_set_addr(struct mt7915_phy *phy, u8 index, u8 *addr)
5405++{
5406++ struct mt7915_air_monitor_ctrl *amnt_ctrl = &phy->amnt_ctrl;
5407++ struct mt7915_air_monitor_group *group;
5408++ struct mt7915_air_monitor_entry *entry = &amnt_ctrl->entry[index];
5409++ const u8 zero_addr[ETH_ALEN] = {};
5410++ int enable = !ether_addr_equal(addr, zero_addr);
5411++ int ret, i, j;
5412++
5413++ if (enable == 1 && entry->enable == 1) {
5414++ ether_addr_copy(entry->addr, addr);
5415++ } else if (enable == 1 && entry->enable == 0){
5416++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_GROUP; i++) {
5417++ group = &(amnt_ctrl->group[i]);
5418++ if (group->used[0] == 0)
5419++ j = 0;
5420++ else
5421++ j = 1;
5422++
5423++ group->enable = 1;
5424++ group->used[j] = 1;
5425++ entry->enable = 1;
5426++ entry->group_idx = i;
5427++ entry->group_used_idx = j;
5428++ entry->muar_idx = 32 + 2 * i + 2 * i + 2 * j;
5429++ ether_addr_copy(entry->addr, addr);
5430++ break;
5431++ }
5432++ } else {
5433++ group = &(amnt_ctrl->group[entry->group_idx]);
5434++
5435++ group->used[entry->group_used_idx] = 0;
5436++ if (group->used[0] == 0 && group->used[1] == 0)
5437++ group->enable = 0;
5438++
5439++ entry->enable = 0;
5440++ ether_addr_copy(entry->addr, addr);
5441++ }
5442++
5443++ amnt_ctrl->enable &= ~(1 << entry->group_idx);
5444++ amnt_ctrl->enable |= entry->enable << entry->group_idx;
5445++ ret = mt7915_vendor_amnt_muar(phy, entry->muar_idx, addr);
5446++ if (ret)
5447++ return ret;
5448++
5449++ return mt7915_vendor_amnt_set_en(phy, amnt_ctrl->enable);
5450++}
5451++
5452++void mt7915_vendor_amnt_fill_rx(struct mt7915_phy *phy, struct sk_buff *skb)
5453++{
5454++ struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
5455++ struct mt7915_air_monitor_ctrl *ctrl = &phy->amnt_ctrl;
5456++ struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb);
5457++ __le16 fc = hdr->frame_control;
5458++ u8 addr[ETH_ALEN];
5459++ int i;
5460++
5461++ if (!ieee80211_has_fromds(fc))
5462++ ether_addr_copy(addr, hdr->addr2);
5463++ else if (ieee80211_has_tods(fc))
5464++ ether_addr_copy(addr, hdr->addr4);
5465++ else
5466++ ether_addr_copy(addr, hdr->addr3);
5467++
5468++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_ENTRY; i++) {
5469++ struct mt7915_air_monitor_entry *entry;
5470++
5471++ if (ether_addr_equal(addr, ctrl->entry[i].addr)) {
5472++ entry = &ctrl->entry[i];
5473++ entry->rssi[0] = status->chain_signal[0];
5474++ entry->rssi[1] = status->chain_signal[1];
5475++ entry->rssi[2] = status->chain_signal[2];
5476++ entry->rssi[3] = status->chain_signal[3];
5477++ entry->last_seen = jiffies;
5478++ }
5479++ }
5480++
5481++ if (ieee80211_has_tods(fc) &&
5482++ !ether_addr_equal(hdr->addr3, phy->mt76->macaddr))
5483++ return;
5484++ else if (!ether_addr_equal(hdr->addr1, phy->mt76->macaddr))
5485++ return;
5486++}
5487++
5488++int mt7915_vendor_amnt_sta_remove(struct mt7915_phy *phy,
5489++ struct ieee80211_sta *sta)
5490++{
5491++ u8 zero[ETH_ALEN] = {};
5492++ int i;
5493++
5494++ if (!phy->amnt_ctrl.enable)
5495++ return 0;
5496++
5497++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_ENTRY; i++)
5498++ if (ether_addr_equal(sta->addr, phy->amnt_ctrl.entry[i].addr))
5499++ return mt7915_vendor_amnt_set_addr(phy, i, zero);
5500++
5501++ return 0;
5502++}
5503++
5504++static int
5505++mt7915_vendor_amnt_ctrl(struct wiphy *wiphy, struct wireless_dev *wdev,
5506++ const void *data, int data_len)
5507++{
5508++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
5509++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
5510++ struct nlattr *tb1[NUM_MTK_VENDOR_ATTRS_AMNT_CTRL];
5511++ struct nlattr *tb2[NUM_MTK_VENDOR_ATTRS_AMNT_SET];
5512++ struct nlattr *cur;
5513++ u8 index = 0, i = 0;
5514++ u8 mac_addr[ETH_ALEN] = {};
5515++ int err, rem;
5516++
5517++ err = nla_parse(tb1, MTK_VENDOR_ATTR_AMNT_CTRL_MAX, data, data_len,
5518++ amnt_ctrl_policy, NULL);
5519++ if (err)
5520++ return err;
5521++
5522++ if (!tb1[MTK_VENDOR_ATTR_AMNT_CTRL_SET])
5523++ return -EINVAL;
5524++
5525++ err = nla_parse_nested(tb2, MTK_VENDOR_ATTR_AMNT_SET_MAX,
5526++ tb1[MTK_VENDOR_ATTR_AMNT_CTRL_SET], amnt_set_policy, NULL);
5527++
5528++ if (!tb2[MTK_VENDOR_ATTR_AMNT_SET_INDEX] ||
5529++ !tb2[MTK_VENDOR_ATTR_AMNT_SET_MACADDR])
5530++ return -EINVAL;
5531++
5532++ index = nla_get_u8(tb2[MTK_VENDOR_ATTR_AMNT_SET_INDEX]);
5533++ nla_for_each_nested(cur, tb2[MTK_VENDOR_ATTR_AMNT_SET_MACADDR], rem) {
5534++ mac_addr[i++] = nla_get_u8(cur);
5535++ }
5536++
5537++ return mt7915_vendor_amnt_set_addr(phy, index, mac_addr);
5538++}
5539++
5540++static int
5541++mt7915_amnt_dump(struct mt7915_phy *phy, struct sk_buff *skb,
5542++ u8 amnt_idx, int *attrtype)
5543++{
5544++ struct mt7915_air_monitor_entry *entry =
5545++ &phy->amnt_ctrl.entry[amnt_idx];
5546++ struct mt7915_amnt_data data;
5547++ u32 last_seen = 0;
5548++
5549++ if (entry->enable == 0)
5550++ return 0;
5551++
5552++ last_seen = jiffies_to_msecs(jiffies - entry->last_seen);
5553++
5554++ data.idx = amnt_idx;
5555++ ether_addr_copy(data.addr, entry->addr);
5556++ data.rssi[0] = entry->rssi[0];
5557++ data.rssi[1] = entry->rssi[1];
5558++ data.rssi[2] = entry->rssi[2];
5559++ data.rssi[3] = entry->rssi[3];
5560++ data.last_seen = last_seen;
5561++
5562++ nla_put(skb, (*attrtype)++, sizeof(struct mt7915_amnt_data), &data);
5563++
5564++ return 1;
5565++}
5566++
5567++static int
5568++mt7915_vendor_amnt_ctrl_dump(struct wiphy *wiphy, struct wireless_dev *wdev,
5569++ struct sk_buff *skb, const void *data, int data_len,
5570++ unsigned long *storage)
5571++{
5572++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
5573++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
5574++ struct nlattr *tb1[NUM_MTK_VENDOR_ATTRS_AMNT_CTRL];
5575++ struct nlattr *tb2[NUM_MTK_VENDOR_ATTRS_AMNT_DUMP];
5576++ void *a, *b;
5577++ int err = 0, attrtype = 0, i, len = 0;
5578++ u8 amnt_idx;
5579++
5580++ if (*storage == 1)
5581++ return -ENOENT;
5582++ *storage = 1;
5583++
5584++ err = nla_parse(tb1, MTK_VENDOR_ATTR_AMNT_CTRL_MAX, data, data_len,
5585++ amnt_ctrl_policy, NULL);
5586++ if (err)
5587++ return err;
5588++
5589++ if (!tb1[MTK_VENDOR_ATTR_AMNT_CTRL_DUMP])
5590++ return -EINVAL;
5591++
5592++ err = nla_parse_nested(tb2, MTK_VENDOR_ATTR_AMNT_DUMP_MAX,
5593++ tb1[MTK_VENDOR_ATTR_AMNT_CTRL_DUMP],
5594++ amnt_dump_policy, NULL);
5595++ if (err)
5596++ return err;
5597++
5598++ if (!tb2[MTK_VENDOR_ATTR_AMNT_DUMP_INDEX])
5599++ return -EINVAL;
5600++
5601++ amnt_idx = nla_get_u8(tb2[MTK_VENDOR_ATTR_AMNT_DUMP_INDEX]);
5602++
5603++ a = nla_nest_start(skb, MTK_VENDOR_ATTR_AMNT_CTRL_DUMP);
5604++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_AMNT_DUMP_RESULT);
5605++
5606++ if (amnt_idx != 0xff) {
5607++ len += mt7915_amnt_dump(phy, skb, amnt_idx, &attrtype);
5608++ } else {
5609++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_ENTRY; i++) {
5610++ len += mt7915_amnt_dump(phy, skb, i, &attrtype);
5611++ }
5612++ }
5613++
5614++ nla_nest_end(skb, b);
5615++
5616++ nla_put_u8(skb, MTK_VENDOR_ATTR_AMNT_DUMP_LEN, len);
5617++
5618++ nla_nest_end(skb, a);
5619++
5620++ return len + 1;
5621++}
5622++
5623+ static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
5624+ {
5625+ .info = {
5626+@@ -442,6 +789,18 @@ static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
5627+ .dumpit = mt7915_vendor_csi_ctrl_dump,
5628+ .policy = csi_ctrl_policy,
5629+ .maxattr = MTK_VENDOR_ATTR_CSI_CTRL_MAX,
5630++ },
5631++ {
5632++ .info = {
5633++ .vendor_id = MTK_NL80211_VENDOR_ID,
5634++ .subcmd = MTK_NL80211_VENDOR_SUBCMD_AMNT_CTRL,
5635++ },
5636++ .flags = WIPHY_VENDOR_CMD_NEED_NETDEV |
5637++ WIPHY_VENDOR_CMD_NEED_RUNNING,
5638++ .doit = mt7915_vendor_amnt_ctrl,
5639++ .dumpit = mt7915_vendor_amnt_ctrl_dump,
5640++ .policy = amnt_ctrl_policy,
5641++ .maxattr = MTK_VENDOR_ATTR_AMNT_CTRL_MAX,
5642+ }
5643+ };
5644+
5645+diff --git a/mt7915/vendor.h b/mt7915/vendor.h
5646+index 9d3db2a7..976817f3 100644
5647+--- a/mt7915/vendor.h
5648++++ b/mt7915/vendor.h
5649+@@ -4,6 +4,7 @@
5650+ #define MTK_NL80211_VENDOR_ID 0x0ce7
5651+
5652+ enum mtk_nl80211_vendor_subcmds {
5653++ MTK_NL80211_VENDOR_SUBCMD_AMNT_CTRL = 0xae,
5654+ MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL = 0xc2,
5655+ };
5656+
5657+@@ -57,4 +58,41 @@ enum mtk_vendor_attr_csi_data {
5658+ NUM_MTK_VENDOR_ATTRS_CSI_DATA - 1
5659+ };
5660+
5661++enum mtk_vendor_attr_mnt_ctrl {
5662++ MTK_VENDOR_ATTR_AMNT_CTRL_UNSPEC,
5663++
5664++ MTK_VENDOR_ATTR_AMNT_CTRL_SET,
5665++ MTK_VENDOR_ATTR_AMNT_CTRL_DUMP,
5666++
5667++ /* keep last */
5668++ NUM_MTK_VENDOR_ATTRS_AMNT_CTRL,
5669++ MTK_VENDOR_ATTR_AMNT_CTRL_MAX =
5670++ NUM_MTK_VENDOR_ATTRS_AMNT_CTRL - 1
5671++};
5672++
5673++enum mtk_vendor_attr_mnt_set {
5674++ MTK_VENDOR_ATTR_AMNT_SET_UNSPEC,
5675++
5676++ MTK_VENDOR_ATTR_AMNT_SET_INDEX,
5677++ MTK_VENDOR_ATTR_AMNT_SET_MACADDR,
5678++
5679++ /* keep last */
5680++ NUM_MTK_VENDOR_ATTRS_AMNT_SET,
5681++ MTK_VENDOR_ATTR_AMNT_SET_MAX =
5682++ NUM_MTK_VENDOR_ATTRS_AMNT_SET - 1
5683++};
5684++
5685++enum mtk_vendor_attr_mnt_dump {
5686++ MTK_VENDOR_ATTR_AMNT_DUMP_UNSPEC,
5687++
5688++ MTK_VENDOR_ATTR_AMNT_DUMP_INDEX,
5689++ MTK_VENDOR_ATTR_AMNT_DUMP_LEN,
5690++ MTK_VENDOR_ATTR_AMNT_DUMP_RESULT,
5691++
5692++ /* keep last */
5693++ NUM_MTK_VENDOR_ATTRS_AMNT_DUMP,
5694++ MTK_VENDOR_ATTR_AMNT_DUMP_MAX =
5695++ NUM_MTK_VENDOR_ATTRS_AMNT_DUMP - 1
5696++};
5697++
5698+ #endif
5699+--
5700+2.29.2
5701+
5702--
57032.29.2
5704