developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From 39ee4e9fb5fd3ce678223147df9d9bef0ce822cd Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:15 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [spi-and-storage][999-2333-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB-and-GD5F1GQ5UExxG.patch] |
| 6 | |
| 7 | --- |
| 8 | drivers/mtd/nand/spi/gigadevice.c | 21 ++++++++++++++++++++- |
| 9 | 1 file changed, 20 insertions(+), 1 deletion(-) |
| 10 | |
| 11 | diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c |
| 12 | index 937a04ce6..ce88f0c91 100644 |
developer | 36be9bc | 2022-03-16 16:05:07 +0800 | [diff] [blame] | 13 | --- a/drivers/mtd/nand/spi/gigadevice.c |
| 14 | +++ b/drivers/mtd/nand/spi/gigadevice.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 15 | @@ -39,6 +39,15 @@ static SPINAND_OP_VARIANTS(read_cache_variants_f, |
developer | 36be9bc | 2022-03-16 16:05:07 +0800 | [diff] [blame] | 16 | SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), |
| 17 | SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); |
| 18 | |
| 19 | +/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */ |
| 20 | +static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants, |
| 21 | + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| 22 | + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| 23 | + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| 24 | + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| 25 | + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| 26 | + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| 27 | + |
| 28 | static SPINAND_OP_VARIANTS(write_cache_variants, |
| 29 | SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| 30 | SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 31 | @@ -236,6 +245,16 @@ static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, |
developer | 36be9bc | 2022-03-16 16:05:07 +0800 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | static const struct spinand_info gigadevice_spinand_table[] = { |
| 35 | + SPINAND_INFO("F50L1G41LB", |
| 36 | + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), |
| 37 | + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| 38 | + NAND_ECCREQ(8, 512), |
| 39 | + SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, |
| 40 | + &write_cache_variants, |
| 41 | + &update_cache_variants), |
| 42 | + 0, |
| 43 | + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| 44 | + gd5fxgq4xa_ecc_get_status)), |
| 45 | SPINAND_INFO("GD5F1GQ4xA", |
| 46 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), |
| 47 | NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 48 | @@ -290,7 +309,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { |
developer | 36be9bc | 2022-03-16 16:05:07 +0800 | [diff] [blame] | 49 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), |
| 50 | NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| 51 | NAND_ECCREQ(4, 512), |
| 52 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 53 | + SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, |
| 54 | &write_cache_variants, |
| 55 | &update_cache_variants), |
| 56 | SPINAND_HAS_QE_BIT, |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 57 | -- |
| 58 | 2.34.1 |
| 59 | |