developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
| 9 | #include "mt7988.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "MediaTek MT7988 GSW 10G SPIM-NAND RFB"; |
| 13 | compatible = "mediatek,mt7988a-gsw-10g-spim-snand", |
| 14 | /* Reserve this for DVFS if creating new dts */ |
| 15 | "mediatek,mt7988"; |
| 16 | |
| 17 | chosen { |
| 18 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 19 | earlycon=uart8250,mmio32,0x11000000 \ |
| 20 | pci=pcie_bus_perf"; |
| 21 | }; |
| 22 | |
| 23 | gsw: gsw@0 { |
| 24 | compatible = "mediatek,mt753x"; |
| 25 | mediatek,sysctrl = <ðwarp>; |
| 26 | #address-cells = <1>; |
| 27 | #size-cells = <0>; |
| 28 | }; |
| 29 | |
| 30 | memory { |
| 31 | reg = <0 0x40000000 0 0x10000000>; |
| 32 | }; |
| 33 | |
| 34 | nmbm_spim_nand { |
| 35 | compatible = "generic,nmbm"; |
| 36 | |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <1>; |
| 39 | |
| 40 | lower-mtd-device = <&spi_nand>; |
| 41 | forced-create; |
| 42 | |
| 43 | partitions { |
| 44 | compatible = "fixed-partitions"; |
| 45 | #address-cells = <1>; |
| 46 | #size-cells = <1>; |
| 47 | |
| 48 | partition@0 { |
| 49 | label = "BL2"; |
| 50 | reg = <0x00000 0x0100000>; |
| 51 | read-only; |
| 52 | }; |
| 53 | |
| 54 | partition@100000 { |
| 55 | label = "u-boot-env"; |
| 56 | reg = <0x0100000 0x0080000>; |
| 57 | }; |
| 58 | |
| 59 | factory: partition@180000 { |
| 60 | label = "Factory"; |
| 61 | reg = <0x180000 0x0400000>; |
| 62 | }; |
| 63 | |
| 64 | partition@580000 { |
| 65 | label = "FIP"; |
| 66 | reg = <0x580000 0x0200000>; |
| 67 | }; |
| 68 | |
| 69 | partition@780000 { |
| 70 | label = "ubi"; |
developer | baa8f60 | 2022-12-07 17:07:51 +0800 | [diff] [blame] | 71 | reg = <0x780000 0x7080000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 72 | }; |
| 73 | }; |
| 74 | }; |
| 75 | |
developer | 9ca473e | 2022-10-20 19:37:54 +0800 | [diff] [blame] | 76 | reg_3p3v: regulator-3p3v { |
| 77 | compatible = "regulator-fixed"; |
| 78 | regulator-name = "fixed-3.3V"; |
| 79 | regulator-min-microvolt = <3300000>; |
| 80 | regulator-max-microvolt = <3300000>; |
| 81 | regulator-boot-on; |
| 82 | regulator-always-on; |
| 83 | }; |
| 84 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 85 | wsys_adie: wsys_adie@0 { |
| 86 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 87 | compatible = "mediatek,rebb-mt7988-adie"; |
| 88 | adie_id = <7976>; |
| 89 | sku_type = <3000>; |
| 90 | }; |
| 91 | }; |
| 92 | |
| 93 | &fan { |
| 94 | pwms = <&pwm 0 50000 0>; |
| 95 | status = "okay"; |
| 96 | }; |
| 97 | |
| 98 | &i2c0 { |
| 99 | pinctrl-names = "default"; |
| 100 | pinctrl-0 = <&i2c0_pins>; |
| 101 | status = "okay"; |
| 102 | |
| 103 | rt5190a_64: rt5190a@64 { |
| 104 | compatible = "richtek,rt5190a"; |
| 105 | reg = <0x64>; |
| 106 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 107 | vin2-supply = <&rt5190_buck1>; |
| 108 | vin3-supply = <&rt5190_buck1>; |
| 109 | vin4-supply = <&rt5190_buck1>; |
| 110 | |
| 111 | regulators { |
| 112 | rt5190_buck1: buck1 { |
| 113 | regulator-name = "rt5190a-buck1"; |
| 114 | regulator-min-microvolt = <5090000>; |
| 115 | regulator-max-microvolt = <5090000>; |
| 116 | regulator-allowed-modes = |
| 117 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 118 | regulator-boot-on; |
| 119 | }; |
| 120 | buck2 { |
| 121 | regulator-name = "vcore"; |
| 122 | regulator-min-microvolt = <600000>; |
| 123 | regulator-max-microvolt = <1400000>; |
| 124 | regulator-boot-on; |
| 125 | }; |
| 126 | buck3 { |
| 127 | regulator-name = "proc"; |
| 128 | regulator-min-microvolt = <600000>; |
| 129 | regulator-max-microvolt = <1400000>; |
| 130 | regulator-boot-on; |
| 131 | }; |
| 132 | buck4 { |
| 133 | regulator-name = "rt5190a-buck4"; |
| 134 | regulator-min-microvolt = <850000>; |
| 135 | regulator-max-microvolt = <850000>; |
| 136 | regulator-allowed-modes = |
| 137 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 138 | regulator-boot-on; |
| 139 | }; |
| 140 | ldo { |
| 141 | regulator-name = "rt5190a-ldo"; |
| 142 | regulator-min-microvolt = <1200000>; |
| 143 | regulator-max-microvolt = <1200000>; |
| 144 | regulator-boot-on; |
| 145 | }; |
| 146 | }; |
| 147 | }; |
| 148 | }; |
| 149 | |
| 150 | &i2c1 { |
| 151 | pinctrl-names = "default"; |
| 152 | pinctrl-0 = <&i2c1_pins>; |
| 153 | status = "okay"; |
| 154 | }; |
| 155 | |
| 156 | &pwm { |
| 157 | status = "okay"; |
| 158 | }; |
| 159 | |
| 160 | &uart0 { |
| 161 | status = "okay"; |
| 162 | }; |
| 163 | |
developer | 97cfd79 | 2023-05-08 11:18:38 +0800 | [diff] [blame] | 164 | &uart1 { |
| 165 | pinctrl-names = "default"; |
| 166 | pinctrl-0 = <&uart1_pins>; |
| 167 | status = "okay"; |
| 168 | }; |
| 169 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 170 | &spi0 { |
| 171 | pinctrl-names = "default"; |
| 172 | pinctrl-0 = <&spi0_flash_pins>; |
| 173 | status = "okay"; |
| 174 | |
| 175 | spi_nand: spi_nand@0 { |
| 176 | #address-cells = <1>; |
| 177 | #size-cells = <1>; |
| 178 | compatible = "spi-nand"; |
| 179 | spi-cal-enable; |
| 180 | spi-cal-mode = "read-data"; |
| 181 | spi-cal-datalen = <7>; |
| 182 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 183 | spi-cal-addrlen = <5>; |
| 184 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 185 | reg = <0>; |
| 186 | spi-max-frequency = <52000000>; |
developer | 5fb8060 | 2023-05-02 18:54:53 +0800 | [diff] [blame] | 187 | spi-tx-bus-width = <4>; |
| 188 | spi-rx-bus-width = <4>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 189 | }; |
| 190 | }; |
| 191 | |
| 192 | &spi1 { |
| 193 | pinctrl-names = "default"; |
| 194 | /* pin shared with snfi */ |
| 195 | pinctrl-0 = <&spic_pins>; |
| 196 | status = "disabled"; |
| 197 | }; |
| 198 | |
| 199 | &pcie0 { |
| 200 | pinctrl-names = "default"; |
| 201 | pinctrl-0 = <&pcie0_pins>; |
| 202 | status = "okay"; |
| 203 | }; |
| 204 | |
| 205 | &pcie1 { |
| 206 | pinctrl-names = "default"; |
| 207 | pinctrl-0 = <&pcie1_pins>; |
| 208 | status = "okay"; |
| 209 | }; |
| 210 | |
| 211 | &pcie2 { |
| 212 | pinctrl-names = "default"; |
| 213 | pinctrl-0 = <&pcie2_pins>; |
| 214 | status = "disabled"; |
| 215 | }; |
| 216 | |
| 217 | &pcie3 { |
| 218 | pinctrl-names = "default"; |
| 219 | pinctrl-0 = <&pcie3_pins>; |
| 220 | status = "okay"; |
| 221 | }; |
| 222 | |
| 223 | &pio { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 224 | mdio0_pins: mdio0-pins { |
| 225 | mux { |
| 226 | function = "mdio"; |
| 227 | groups = "mdc_mdio0"; |
| 228 | }; |
| 229 | |
| 230 | conf { |
| 231 | groups = "mdc_mdio0"; |
| 232 | drive-strength = <MTK_DRIVE_8mA>; |
| 233 | }; |
| 234 | }; |
| 235 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 236 | gbe0_led0_pins: gbe0-pins { |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 237 | mux { |
| 238 | function = "led"; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 239 | groups = "gbe0_led0"; |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 240 | }; |
| 241 | }; |
| 242 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 243 | gbe1_led0_pins: gbe1-pins { |
| 244 | mux { |
| 245 | function = "led"; |
| 246 | groups = "gbe1_led0"; |
| 247 | }; |
| 248 | }; |
| 249 | |
| 250 | gbe2_led0_pins: gbe2-pins { |
| 251 | mux { |
| 252 | function = "led"; |
| 253 | groups = "gbe2_led0"; |
| 254 | }; |
| 255 | }; |
| 256 | |
| 257 | gbe3_led0_pins: gbe3-pins { |
| 258 | mux { |
| 259 | function = "led"; |
| 260 | groups = "gbe3_led0"; |
| 261 | }; |
| 262 | }; |
| 263 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 264 | i2c0_pins: i2c0-pins-g0 { |
| 265 | mux { |
| 266 | function = "i2c"; |
| 267 | groups = "i2c0_1"; |
| 268 | }; |
| 269 | }; |
| 270 | |
| 271 | i2c1_pins: i2c1-pins-g0 { |
| 272 | mux { |
| 273 | function = "i2c"; |
| 274 | groups = "i2c1_0"; |
| 275 | }; |
| 276 | }; |
| 277 | |
developer | 9ca473e | 2022-10-20 19:37:54 +0800 | [diff] [blame] | 278 | mmc0_pins_default: mmc0-pins-default { |
| 279 | mux { |
| 280 | function = "flash"; |
developer | 7d52c34 | 2022-11-03 11:46:34 +0800 | [diff] [blame] | 281 | groups = "sdcard"; |
developer | 9ca473e | 2022-10-20 19:37:54 +0800 | [diff] [blame] | 282 | }; |
| 283 | }; |
| 284 | |
| 285 | mmc0_pins_uhs: mmc0-pins-uhs { |
| 286 | mux { |
| 287 | function = "flash"; |
developer | 7d52c34 | 2022-11-03 11:46:34 +0800 | [diff] [blame] | 288 | groups = "sdcard"; |
developer | 9ca473e | 2022-10-20 19:37:54 +0800 | [diff] [blame] | 289 | }; |
| 290 | }; |
| 291 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 292 | pcie0_pins: pcie0-pins { |
| 293 | mux { |
| 294 | function = "pcie"; |
| 295 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 296 | "pcie_wake_n0_0"; |
| 297 | }; |
| 298 | }; |
| 299 | |
| 300 | pcie1_pins: pcie1-pins { |
| 301 | mux { |
| 302 | function = "pcie"; |
| 303 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 304 | "pcie_wake_n1_0"; |
| 305 | }; |
| 306 | }; |
| 307 | |
| 308 | pcie2_pins: pcie2-pins { |
| 309 | mux { |
| 310 | function = "pcie"; |
| 311 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 312 | "pcie_wake_n2_0"; |
| 313 | }; |
| 314 | }; |
| 315 | |
| 316 | pcie3_pins: pcie3-pins { |
| 317 | mux { |
| 318 | function = "pcie"; |
| 319 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 320 | "pcie_wake_n3_0"; |
| 321 | }; |
| 322 | }; |
| 323 | |
| 324 | spi0_flash_pins: spi0-pins { |
| 325 | mux { |
| 326 | function = "spi"; |
| 327 | groups = "spi0", "spi0_wp_hold"; |
| 328 | }; |
| 329 | }; |
| 330 | |
| 331 | spic_pins: spi1-pins { |
| 332 | mux { |
| 333 | function = "spi"; |
developer | 1ceb26a | 2023-02-16 15:43:43 +0800 | [diff] [blame] | 334 | groups = "spi1"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 335 | }; |
| 336 | }; |
developer | 97cfd79 | 2023-05-08 11:18:38 +0800 | [diff] [blame] | 337 | |
| 338 | uart1_pins: uart1-pins { |
| 339 | mux { |
| 340 | function = "uart"; |
| 341 | groups = "uart1_2"; |
| 342 | }; |
| 343 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 344 | }; |
| 345 | |
| 346 | &watchdog { |
| 347 | status = "disabled"; |
| 348 | }; |
| 349 | |
| 350 | ð { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 351 | pinctrl-names = "default"; |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 352 | pinctrl-0 = <&mdio0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 353 | status = "okay"; |
| 354 | |
| 355 | gmac0: mac@0 { |
| 356 | compatible = "mediatek,eth-mac"; |
| 357 | reg = <0>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 358 | mac-type = "xgdm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 359 | phy-mode = "10gbase-kr"; |
| 360 | |
| 361 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 362 | speed = <10000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 363 | full-duplex; |
| 364 | pause; |
| 365 | }; |
| 366 | }; |
| 367 | |
| 368 | gmac1: mac@1 { |
| 369 | compatible = "mediatek,eth-mac"; |
| 370 | reg = <1>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 371 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 372 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 373 | phy-handle = <&phy0>; |
| 374 | }; |
| 375 | |
| 376 | gmac2: mac@2 { |
| 377 | compatible = "mediatek,eth-mac"; |
| 378 | reg = <2>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 379 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 380 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 381 | phy-handle = <&phy1>; |
| 382 | }; |
| 383 | |
| 384 | mdio: mdio-bus { |
| 385 | #address-cells = <1>; |
| 386 | #size-cells = <0>; |
developer | c4d8da7 | 2023-03-16 14:37:28 +0800 | [diff] [blame] | 387 | clock-frequency = <10500000>; |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 388 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 389 | phy0: ethernet-phy@0 { |
| 390 | reg = <0>; |
| 391 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 392 | reset-gpios = <&pio 72 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 393 | reset-assert-us = <100000>; |
| 394 | reset-deassert-us = <221000>; |
developer | 301205c | 2023-05-24 15:39:32 +0800 | [diff] [blame^] | 395 | mdi-reversal = /bits/ 16 <1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 396 | }; |
| 397 | |
| 398 | phy1: ethernet-phy@8 { |
| 399 | reg = <8>; |
| 400 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 401 | reset-gpios = <&pio 71 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 402 | reset-assert-us = <100000>; |
| 403 | reset-deassert-us = <221000>; |
developer | 301205c | 2023-05-24 15:39:32 +0800 | [diff] [blame^] | 404 | mdi-reversal = /bits/ 16 <1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 405 | }; |
| 406 | }; |
| 407 | }; |
| 408 | |
| 409 | &hnat { |
| 410 | mtketh-wan = "eth1"; |
| 411 | mtketh-lan = "eth0"; |
| 412 | mtketh-lan2 = "eth2"; |
| 413 | mtketh-max-gmac = <3>; |
| 414 | status = "okay"; |
| 415 | }; |
| 416 | |
| 417 | &gsw { |
| 418 | mediatek,mdio = <&mdio>; |
| 419 | mediatek,portmap = "llllw"; |
| 420 | mediatek,mdio_master_pinmux = <1>; |
| 421 | interrupt-parent = <&gic>; |
| 422 | interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
| 423 | status = "okay"; |
| 424 | |
| 425 | port6: port@6 { |
| 426 | compatible = "mediatek,mt753x-port"; |
| 427 | mediatek,ssc-on; |
| 428 | phy-mode = "10gbase-kr"; |
| 429 | reg = <6>; |
| 430 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 431 | speed = <10000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 432 | full-duplex; |
| 433 | }; |
| 434 | }; |
| 435 | |
| 436 | mdio1: mdio-bus { |
| 437 | #address-cells = <1>; |
| 438 | #size-cells = <0>; |
| 439 | |
| 440 | gsw_phy0: ethernet-phy@0 { |
| 441 | compatible = "ethernet-phy-id03a2.9481"; |
| 442 | reg = <0>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 443 | pinctrl-names = "gbe-led"; |
| 444 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 445 | nvmem-cells = <&phy_calibration_p0>; |
| 446 | nvmem-cell-names = "phy-cal-data"; |
| 447 | }; |
| 448 | |
| 449 | gsw_phy1: ethernet-phy@1 { |
| 450 | compatible = "ethernet-phy-id03a2.9481"; |
| 451 | reg = <1>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 452 | pinctrl-names = "gbe-led"; |
| 453 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 454 | nvmem-cells = <&phy_calibration_p1>; |
| 455 | nvmem-cell-names = "phy-cal-data"; |
| 456 | }; |
| 457 | |
| 458 | gsw_phy2: ethernet-phy@2 { |
| 459 | compatible = "ethernet-phy-id03a2.9481"; |
| 460 | reg = <2>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 461 | pinctrl-names = "gbe-led"; |
| 462 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 463 | nvmem-cells = <&phy_calibration_p2>; |
| 464 | nvmem-cell-names = "phy-cal-data"; |
| 465 | }; |
| 466 | |
| 467 | gsw_phy3: ethernet-phy@3 { |
| 468 | compatible = "ethernet-phy-id03a2.9481"; |
| 469 | reg = <3>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 470 | pinctrl-names = "gbe-led"; |
| 471 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 472 | nvmem-cells = <&phy_calibration_p3>; |
| 473 | nvmem-cell-names = "phy-cal-data"; |
| 474 | }; |
| 475 | }; |
| 476 | }; |
developer | 9ca473e | 2022-10-20 19:37:54 +0800 | [diff] [blame] | 477 | |
| 478 | &mmc0 { |
| 479 | pinctrl-names = "default", "state_uhs"; |
| 480 | pinctrl-0 = <&mmc0_pins_default>; |
| 481 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 482 | bus-width = <4>; |
| 483 | max-frequency = <52000000>; |
| 484 | cap-sd-highspeed; |
| 485 | vmmc-supply = <®_3p3v>; |
| 486 | vqmmc-supply = <®_3p3v>; |
| 487 | no-mmc; |
| 488 | no-sdio; |
| 489 | status = "okay"; |
| 490 | }; |
developer | de8a106 | 2023-01-31 17:00:33 +0800 | [diff] [blame] | 491 | |
| 492 | &slot0 { |
| 493 | mt7996@0,0 { |
| 494 | reg = <0x0000 0 0 0 0>; |
| 495 | device_type = "pci"; |
| 496 | mediatek,mtd-eeprom = <&factory 0x0>; |
| 497 | }; |
| 498 | }; |