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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 2b9bc72cd9030fc01bb597e4c040a59b708b03e1 / . / target / linux / mediatek / patches-5.4 / 753-net-mt753x-phy-coverity-scan.patch
blob: c4d7d4c53fc31e4aca581b9c59525df3e11c0bff [file] [log] [blame]
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]1diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_common.c b/drivers/net/phy/mtk/mt753x/mt753x_common.c
2--- a/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:12:06.308223474 +0800
3+++ b/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:21:52.038450276 +0800
4@@ -49,6 +49,9 @@
5 case MAC_SPD_2500:
6 speed = "2.5Gbps";
7 break;
8+ default:
9+ dev_info(gsw->dev, "Invalid speed\n");
10+ return;
11 }
12
13 if (pmsr & MAC_LNK_STS) {
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]14diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_phy.c b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
15--- a/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-25 14:12:34.160149995 +0800
16+++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-29 14:12:28.261884707 +0800
17@@ -141,7 +141,7 @@
18 u16 dev1e_17a_tmp, dev1e_e0_tmp;
19
20 /* *** Iext/Rext Cal start ************ */
21- all_ana_cal_status = ANACAL_INIT;
22+ //all_ana_cal_status = ANACAL_INIT;
23 /* analog calibration enable, Rext calibration enable */
24 /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
25 /* 1e_dc[0]:rg_txvos_calen */
26@@ -185,7 +185,7 @@
27 all_ana_cal_status = ANACAL_FINISH;
28 //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
29 } else {
30- dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
31+ //dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
32 dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
33 if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
34 all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
35@@ -580,33 +580,35 @@
36 } else if (phyaddr == 1) {
37 if (calibration_pair == ANACAL_PAIR_A)
38 tx_amp_temp = tx_amp_temp - 1;
39- else if(calibration_pair == ANACAL_PAIR_B)
40- tx_amp_temp = tx_amp_temp ;
41+ //else if(calibration_pair == ANACAL_PAIR_B)
42+ // tx_amp_temp = tx_amp_temp;
43 else if(calibration_pair == ANACAL_PAIR_C)
44 tx_amp_temp = tx_amp_temp - 1;
45 else if(calibration_pair == ANACAL_PAIR_D)
46 tx_amp_temp = tx_amp_temp - 1;
47 } else if (phyaddr == 2) {
48- if (calibration_pair == ANACAL_PAIR_A)
49- tx_amp_temp = tx_amp_temp;
50- else if(calibration_pair == ANACAL_PAIR_B)
51+ //if (calibration_pair == ANACAL_PAIR_A)
52+ // tx_amp_temp = tx_amp_temp;
53+ //else if(calibration_pair == ANACAL_PAIR_B)
54+ if(calibration_pair == ANACAL_PAIR_B)
55 tx_amp_temp = tx_amp_temp - 1;
56- else if(calibration_pair == ANACAL_PAIR_C)
57- tx_amp_temp = tx_amp_temp;
58+ //else if(calibration_pair == ANACAL_PAIR_C)
59+ // tx_amp_temp = tx_amp_temp;
60 else if(calibration_pair == ANACAL_PAIR_D)
61 tx_amp_temp = tx_amp_temp - 1;
62- } else if (phyaddr == 3) {
63- tx_amp_temp = tx_amp_temp;
64+ //} else if (phyaddr == 3) {
65+ // tx_amp_temp = tx_amp_temp;
66 } else if (phyaddr == 4) {
67- if (calibration_pair == ANACAL_PAIR_A)
68- tx_amp_temp = tx_amp_temp;
69- else if(calibration_pair == ANACAL_PAIR_B)
70+ //if (calibration_pair == ANACAL_PAIR_A)
71+ // tx_amp_temp = tx_amp_temp;
72+ //else if(calibration_pair == ANACAL_PAIR_B)
73+ if(calibration_pair == ANACAL_PAIR_B)
74 tx_amp_temp = tx_amp_temp - 1;
75- else if(calibration_pair == ANACAL_PAIR_C)
76- tx_amp_temp = tx_amp_temp;
77- else if(calibration_pair == ANACAL_PAIR_D)
78- tx_amp_temp = tx_amp_temp;
79- }
80+ //else if(calibration_pair == ANACAL_PAIR_C)
81+ // tx_amp_temp = tx_amp_temp;
82+ //else if(calibration_pair == ANACAL_PAIR_D)
83+ // tx_amp_temp = tx_amp_temp;
84+ }
85 reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
86 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
87 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
88@@ -704,7 +706,7 @@
89 reg_backup = 0x0000;
90 reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
91 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
92- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
93+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
94 //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
95 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
96 reg_tmp = ((reg_backup & 0x3f) >> 0);
97@@ -712,7 +714,7 @@
98 reg_backup = (reg_backup & (~0x3f));
99 reg_backup |= (reg_tmp << 0);
100 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
101- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
102+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
103 //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
104 }
105 else if(calibration_pair == ANACAL_PAIR_B){
106@@ -722,7 +724,7 @@
107 reg_backup = 0x0000;
108 reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
109 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
110- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
111+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
112 //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
113 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
114 reg_tmp = ((reg_backup & 0x3f) >> 0);
115@@ -730,7 +732,7 @@
116 reg_backup = (reg_backup & (~0x3f));
117 reg_backup |= (reg_tmp << 0);
118 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
119- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
120+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
121 //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
122 }
123 else if(calibration_pair == ANACAL_PAIR_C){
124@@ -740,7 +742,7 @@
125 reg_backup = (reg_backup & (~0x3f00));
126 reg_backup |= (reg_tmp << 8);
127 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
128- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
129+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
130 //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
131 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
132 reg_tmp = ((reg_backup & 0x3f) >> 0);
133@@ -748,7 +750,7 @@
134 reg_backup = (reg_backup & (~0x3f));
135 reg_backup |= (reg_tmp << 0);
136 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
137- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
138+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
139 //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
140 }
141 else if(calibration_pair == ANACAL_PAIR_D){
142@@ -758,7 +760,7 @@
143 reg_backup = (reg_backup & (~0x3f00));
144 reg_backup |= (reg_tmp << 8);
145 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
146- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
147+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
148 //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
149 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
150 reg_tmp = ((reg_backup & 0x3f) >> 0);
151@@ -766,7 +768,7 @@
152 reg_backup = (reg_backup & (~0x3f));
153 reg_backup |= (reg_tmp << 0);
154 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
155- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
156+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
157 //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
158 }
159