Gitiles
Code Review Sign In
git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 2b101966085d8aa72734643c4045a77ee1b9d1ae / . / target / linux / mediatek / patches-5.4 / 413-mtd-spinand-gigadevice-Add-support-for-GD5FxGQxUExxG-GD5FxGQxUExxH-and-GD5FxGMxUExxG-series.patch
blob: 83e4c711a7050cc274115c68353e7ad3b45d6a9d [file] [log] [blame]
developera72492d2022-03-17 13:14:14 +0800[diff] [blame]1--- a/drivers/mtd/nand/spi/gigadevice.c
2+++ b/drivers/mtd/nand/spi/gigadevice.c
3@@ -39,8 +39,9 @@ static SPINAND_OP_VARIANTS(read_cache_va
4 SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
5 SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
6
7-/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
8-static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
9+/* For Q5 devices, QUADIO use different dummy byte settings */
10+/* Q5 1Gb */
11+static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
12 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
13 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
14 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
15@@ -48,6 +49,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read
16 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
17 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
18
19+/* Q5 2Gb & 4Gb */
20+static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
21+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
22+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
23+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
24+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
25+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
26+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
27+
28 static SPINAND_OP_VARIANTS(write_cache_variants,
29 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
30 SPINAND_PROG_LOAD(true, 0, NULL, 0));
31@@ -249,7 +259,7 @@ static const struct spinand_info gigadev
32 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
33 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
34 NAND_ECCREQ(8, 512),
35- SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
36+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
37 &write_cache_variants,
38 &update_cache_variants),
39 0,
40@@ -309,7 +319,87 @@ static const struct spinand_info gigadev
41 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
42 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
43 NAND_ECCREQ(4, 512),
44- SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
45+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
46+ &write_cache_variants,
47+ &update_cache_variants),
48+ SPINAND_HAS_QE_BIT,
49+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
50+ gd5fxgq5xexxg_ecc_get_status)),
51+ SPINAND_INFO("GD5F2GQ5UExxG",
52+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
53+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
54+ NAND_ECCREQ(4, 512),
55+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
56+ &write_cache_variants,
57+ &update_cache_variants),
58+ SPINAND_HAS_QE_BIT,
59+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
60+ gd5fxgq5xexxg_ecc_get_status)),
61+ SPINAND_INFO("GD5F4GQ6UExxG",
62+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
63+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
64+ NAND_ECCREQ(4, 512),
65+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
66+ &write_cache_variants,
67+ &update_cache_variants),
68+ SPINAND_HAS_QE_BIT,
69+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
70+ gd5fxgq5xexxg_ecc_get_status)),
71+ SPINAND_INFO("GD5F1GM7UExxG",
72+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
73+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
74+ NAND_ECCREQ(8, 512),
75+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
76+ &write_cache_variants,
77+ &update_cache_variants),
78+ SPINAND_HAS_QE_BIT,
79+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
80+ gd5fxgq4uexxg_ecc_get_status)),
81+ SPINAND_INFO("GD5F2GM7UExxG",
82+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
83+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
84+ NAND_ECCREQ(8, 512),
85+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
86+ &write_cache_variants,
87+ &update_cache_variants),
88+ SPINAND_HAS_QE_BIT,
89+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
90+ gd5fxgq4uexxg_ecc_get_status)),
91+ SPINAND_INFO("GD5F4GM8UExxG",
92+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
93+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
94+ NAND_ECCREQ(8, 512),
95+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
96+ &write_cache_variants,
97+ &update_cache_variants),
98+ SPINAND_HAS_QE_BIT,
99+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
100+ gd5fxgq4uexxg_ecc_get_status)),
101+ SPINAND_INFO("GD5F1GQ5UExxH",
102+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
103+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
104+ NAND_ECCREQ(4, 512),
105+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
106+ &write_cache_variants,
107+ &update_cache_variants),
108+ SPINAND_HAS_QE_BIT,
109+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
110+ gd5fxgq5xexxg_ecc_get_status)),
111+ SPINAND_INFO("GD5F2GQ5UExxH",
112+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
113+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
114+ NAND_ECCREQ(4, 512),
115+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
116+ &write_cache_variants,
117+ &update_cache_variants),
118+ SPINAND_HAS_QE_BIT,
119+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
120+ gd5fxgq5xexxg_ecc_get_status)),
121+ SPINAND_INFO("GD5F4GQ6UExxH",
122+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
123+ NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
124+ NAND_ECCREQ(4, 512),
125+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
126 &write_cache_variants,
127 &update_cache_variants),
128 SPINAND_HAS_QE_BIT,