| developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H |
| 4 | #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H |
| 5 | |
| 6 | #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) |
| 7 | #define MTK_SCPD_FWAIT_SRAM BIT(1) |
| 8 | #define MTK_SCPD_SRAM_ISO BIT(2) |
| 9 | #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) |
| 10 | #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) |
| 11 | #define MTK_SCPD_CLAMP_PROTECTION BIT(5) |
| 12 | #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) |
| 13 | |
| 14 | /** |
| 15 | * struct scpsys_domain_data - scp domain data for power on/off flow |
| 16 | * @sta_mask: The mask for power on/off status bit. |
| 17 | * @sta_2nd_mask: The mask for 2nd power on/off status bit. |
| 18 | * @pwr_sta_offs: the main power status register. |
| 19 | * @pwr_sta_2nd_offs: the 2nd power status register. |
| 20 | * @pwr_on_bit: The power on/off bit. |
| 21 | * @pwr_on_2nd_bit: The 2nd power on/off bit. |
| 22 | * @pwr_on_offs: The offset for main power control register. |
| 23 | * @pwr_on_2nd_offs: The offset for 2nd power control register. |
| 24 | * @sram_pdn_bit: The mask for sram power control bit. |
| 25 | * @sram_pdn_ack_bit: The sram power control acked bit. |
| 26 | * @sram_clk_iso_bit: The sram clk iso bit. |
| 27 | * @sram_clk_dis_bit: The sram clk disable bit. |
| 28 | * @sram_ctrl_offs: The sram power control register. |
| 29 | * @caps: The flag for active wake-up action. |
| 30 | * @bp_infracfg: bus protection for infracfg subsystem |
| 31 | */ |
| 32 | struct scpsys_domain_data { |
| 33 | u32 sta_mask; |
| 34 | u32 sta_2nd_mask; |
| 35 | int pwr_sta_offs; |
| 36 | int pwr_sta_2nd_offs; |
| 37 | u32 pwr_on_bit; |
| 38 | u32 pwr_on_2nd_bit; |
| 39 | int pwr_on_offs; |
| 40 | int pwr_on_2nd_offs; |
| 41 | u32 pwr_clamp_bit; |
| 42 | u32 pwr_rst_bit; |
| 43 | u32 sram_pdn_bit; |
| 44 | u32 sram_pdn_ack_bit; |
| 45 | u32 sram_clk_iso_bit; |
| 46 | u32 sram_clk_dis_bit; |
| 47 | int sram_ctrl_offs; |
| 48 | u32 sram_2nd_pdn_bit; |
| 49 | u32 sram_2nd_pdn_ack_bit; |
| 50 | u32 sram_2nd_clk_iso_bit; |
| 51 | u32 sram_2nd_clk_dis_bit; |
| 52 | int sram_2nd_ctrl_offs; |
| 53 | u8 caps; |
| 54 | |
| 55 | }; |
| 56 | |
| 57 | struct scpsys_soc_data { |
| 58 | const struct scpsys_domain_data *domains_data; |
| 59 | int num_domains; |
| 60 | }; |
| 61 | |
| 62 | #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ |